Cadence-DeHDL-Demo/hardware/Cadence/top/archive_libs/cnpower/p2v5/entity/vhdl.vhd
2025-01-07 19:29:47 -08:00

13 lines
269 B
VHDL

-- generated by newgenasym Mon Dec 10 11:16:54 2001
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity p2v5 is
generic (
size:positive:= 1
);
port (
A: INOUT STD_LOGIC_VECTOR (size-1 DOWNTO 0));
end p2v5;