Cadence-DeHDL-Demo/hardware/Cadence/top/archive_libs/oxflib/kkcon3/entity/vhdl.vhd
2025-01-07 19:29:47 -08:00

15 lines
391 B
VHDL

-- generated by newgenasym Thu Jul 3 10:38:57 2003
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity KKCON3 is
generic (
size:positive:= 1
);
port (
A1: INOUT STD_LOGIC_VECTOR (size-1 DOWNTO 0);
A2: INOUT STD_LOGIC_VECTOR (size-1 DOWNTO 0);
B1: INOUT STD_LOGIC_VECTOR (size-1 DOWNTO 0));
end KKCON3;