Cadence-DeHDL-Demo/hardware/Cadence/top/archive_libs/oxflib/sf#2d0603s300#2d2/entity/verilog.v
2025-01-07 19:29:47 -08:00

14 lines
171 B
Verilog

// generated by newgenasym Fri Feb 23 09:44:50 2024
module \sf-0603s300-2 (\1 , \2 );
inout \1 ;
inout \2 ;
initial
begin
end
endmodule