11 lines
245 B
VHDL
11 lines
245 B
VHDL
-- generated by newgenasym Fri Feb 23 09:44:50 2024
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity \sf-0603s300-2\ is
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port (
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\1\: INOUT STD_LOGIC;
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\2\: INOUT STD_LOGIC);
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end \sf-0603s300-2\;
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