Cadence-DeHDL-Demo/hardware/Cadence/top/archive_libs/oxflib/shf#2d105#2d01#2dl#2dd#2dsm/entity/verilog.v
2025-01-07 19:29:47 -08:00

22 lines
337 B
Verilog

// generated by newgenasym Fri Jun 21 10:18:56 2024
module \shf-105-01-l-d-sm (\1 , \10 , \2 , \3 , \4 , \5 , \6 , \7 , \8 , \9 );
inout \1 ;
inout \10 ;
inout \2 ;
inout \3 ;
inout \4 ;
inout \5 ;
inout \6 ;
inout \7 ;
inout \8 ;
inout \9 ;
initial
begin
end
endmodule