Cadence-DeHDL-Demo/hardware/Cadence/top/archive_libs/oxflib/shf#2d105#2d01#2dl#2dd#2dsm/entity/vhdl.vhd
2025-01-07 19:29:47 -08:00

19 lines
525 B
VHDL

-- generated by newgenasym Fri Jun 21 10:18:56 2024
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity \shf-105-01-l-d-sm\ is
port (
\1\: INOUT STD_LOGIC;
\10\: INOUT STD_LOGIC;
\2\: INOUT STD_LOGIC;
\3\: INOUT STD_LOGIC;
\4\: INOUT STD_LOGIC;
\5\: INOUT STD_LOGIC;
\6\: INOUT STD_LOGIC;
\7\: INOUT STD_LOGIC;
\8\: INOUT STD_LOGIC;
\9\: INOUT STD_LOGIC);
end \shf-105-01-l-d-sm\;