Cadence-DeHDL-Demo/hardware/Cadence/top/archive_libs/oxflib/ss16fp/entity/verilog.v
2025-01-07 19:29:47 -08:00

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Verilog

// generated by newgenasym Fri Jun 21 11:27:11 2024
module ss16fp (a, c);
inout a;
inout c;
initial
begin
end
endmodule