Cadence-DeHDL-Demo/hardware/Cadence/top/archive_libs/oxflib/ss16fp/entity/vhdl.vhd
2025-01-07 19:29:47 -08:00

11 lines
227 B
VHDL

-- generated by newgenasym Fri Jun 21 11:27:11 2024
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity ss16fp is
port (
A: INOUT STD_LOGIC;
C: INOUT STD_LOGIC);
end ss16fp;