81 lines
1.4 KiB
Verilog
81 lines
1.4 KiB
Verilog
// generated by newgenasym Thu Apr 20 16:50:53 2023
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module atmga128 (aref, avcc, gnd1, gnd2, gnd3, pa0, pa1, pa2, pa3, pa4, pa5, pa6,
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pa7, pb0, pb1, pb2, pb3, pb4, pb5, pb6, pb7, pc0, pc1, pc2, pc3,
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pc4, pc5, pc6, pc7, pd0, pd1, pd2, pd3, pd4, pd5, pd6, pd7, pe0,
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pe1, pe2, pe3, pe4, pe5, pe6, pe7, \pen* , pf0, pf1, pf2, pf3, pf4,
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pf5, pf6, pf7, pg0, pg1, pg2, pg3, pg4, \reset* , vcc1, vcc2,
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xtal1, xtal2);
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inout aref;
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inout avcc;
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input gnd1;
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input gnd2;
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input gnd3;
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inout pa0;
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inout pa1;
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inout pa2;
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inout pa3;
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inout pa4;
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inout pa5;
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inout pa6;
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inout pa7;
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inout pb0;
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inout pb1;
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inout pb2;
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inout pb3;
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inout pb4;
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inout pb5;
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inout pb6;
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inout pb7;
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inout pc0;
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inout pc1;
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inout pc2;
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inout pc3;
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inout pc4;
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inout pc5;
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inout pc6;
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inout pc7;
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inout pd0;
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inout pd1;
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inout pd2;
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inout pd3;
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inout pd4;
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inout pd5;
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inout pd6;
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inout pd7;
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inout pe0;
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inout pe1;
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inout pe2;
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inout pe3;
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inout pe4;
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inout pe5;
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inout pe6;
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inout pe7;
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inout \pen* ;
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inout pf0;
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inout pf1;
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inout pf2;
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inout pf3;
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inout pf4;
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inout pf5;
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inout pf6;
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inout pf7;
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inout pg0;
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inout pg1;
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inout pg2;
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inout pg3;
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inout pg4;
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inout \reset* ;
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input vcc1;
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input vcc2;
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inout xtal1;
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inout xtal2;
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initial
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begin
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end
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endmodule
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