73 lines
2.3 KiB
VHDL
73 lines
2.3 KiB
VHDL
-- generated by newgenasym Thu Apr 20 16:50:53 2023
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity atmga128 is
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port (
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AREF: INOUT STD_LOGIC;
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AVCC: INOUT STD_LOGIC;
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GND1: IN STD_LOGIC;
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GND2: IN STD_LOGIC;
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GND3: IN STD_LOGIC;
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PA0: INOUT STD_LOGIC;
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PA1: INOUT STD_LOGIC;
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PA2: INOUT STD_LOGIC;
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PA3: INOUT STD_LOGIC;
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PA4: INOUT STD_LOGIC;
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PA5: INOUT STD_LOGIC;
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PA6: INOUT STD_LOGIC;
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PA7: INOUT STD_LOGIC;
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PB0: INOUT STD_LOGIC;
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PB1: INOUT STD_LOGIC;
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PB2: INOUT STD_LOGIC;
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PB3: INOUT STD_LOGIC;
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PB4: INOUT STD_LOGIC;
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PB5: INOUT STD_LOGIC;
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PB6: INOUT STD_LOGIC;
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PB7: INOUT STD_LOGIC;
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PC0: INOUT STD_LOGIC;
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PC1: INOUT STD_LOGIC;
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PC2: INOUT STD_LOGIC;
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PC3: INOUT STD_LOGIC;
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PC4: INOUT STD_LOGIC;
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PC5: INOUT STD_LOGIC;
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PC6: INOUT STD_LOGIC;
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PC7: INOUT STD_LOGIC;
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PD0: INOUT STD_LOGIC;
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PD1: INOUT STD_LOGIC;
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PD2: INOUT STD_LOGIC;
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PD3: INOUT STD_LOGIC;
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PD4: INOUT STD_LOGIC;
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PD5: INOUT STD_LOGIC;
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PD6: INOUT STD_LOGIC;
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PD7: INOUT STD_LOGIC;
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PE0: INOUT STD_LOGIC;
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PE1: INOUT STD_LOGIC;
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PE2: INOUT STD_LOGIC;
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PE3: INOUT STD_LOGIC;
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PE4: INOUT STD_LOGIC;
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PE5: INOUT STD_LOGIC;
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PE6: INOUT STD_LOGIC;
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PE7: INOUT STD_LOGIC;
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\pen*\: INOUT STD_LOGIC;
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PF0: INOUT STD_LOGIC;
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PF1: INOUT STD_LOGIC;
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PF2: INOUT STD_LOGIC;
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PF3: INOUT STD_LOGIC;
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PF4: INOUT STD_LOGIC;
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PF5: INOUT STD_LOGIC;
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PF6: INOUT STD_LOGIC;
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PF7: INOUT STD_LOGIC;
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PG0: INOUT STD_LOGIC;
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PG1: INOUT STD_LOGIC;
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PG2: INOUT STD_LOGIC;
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PG3: INOUT STD_LOGIC;
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PG4: INOUT STD_LOGIC;
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\reset*\: INOUT STD_LOGIC;
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VCC1: IN STD_LOGIC;
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VCC2: IN STD_LOGIC;
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XTAL1: INOUT STD_LOGIC;
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XTAL2: INOUT STD_LOGIC);
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end atmga128;
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