Incorrect voltage divider network on U29 DCDC converter #11

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opened 2026-07-07 23:09:19 +00:00 by allspice-wayne · 0 comments

allspice-wayne commented

2026-07-07 23:09:19 +00:00

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[🚨 Error] Component U29, pin 11: FB2 is connected to a voltage divider network (R282, R281) that produces approximately 0.94V output, but the design specification indicates 1.8V is required. The resistor values are incorrect for the intended 1.8V output.

Pin 11 (FB2) is connected to net N25830704 (from schematic)
FB2 connects to a voltage divider consisting of R282 (10K) from the output to FB2, and R281 (56.2K) from FB2 to ground (from schematic)
FB2 regulation voltage is 0.8V typical (from datasheet ISL9307IRTAANFZ-T, page 5)
The output voltage is calculated as Vout = 0.8V × (1 + R282/R281) = 0.8V × (1 + 10K/56.2K) = 0.942V (reasoning)
The text note indicates the output should be 1.8V @ 1.5A max (from schematic)
The DCD2 output connects through R287 (0 ohm) to the 1P8V net, confirming the intended output is 1.8V (from schematic)
For 1.8V output, the resistor ratio should be R_TOP/R_BOT = (1.8V/0.8V) - 1 = 1.25 (reasoning)
The actual ratio is R282/R281 = 10K/56.2K = 0.178, which does not match the required 1.25 ratio (reasoning)
To achieve 1.8V output, either R282 should be changed to approximately 70K (keeping R281 = 56.2K), or R281 should be changed to approximately 8K (keeping R282 = 10K) (reasoning)
The feedback resistor values are incorrect and will produce 0.94V instead of the intended 1.8V (reasoning)

_{Replace a datasheet: 📤 U29}

_{^{💬 Reply to this comment and mention @DRCY to give feedback that DRCY will incorporate on the next run.}}

Originally posted by @DRCY in https://hub.allspice.io/AllSpice-Demos/SystemCap-Demo-Project/pulls/8/files#diff-dcdcb94003e38cba372049b9bb4e30b1d34e6b5f-issuecomment-52773

[🚨 Error] **Component `U29`, pin `11`: FB2 is connected to a voltage divider network (R282, R281) that produces approximately 0.94V output, but the design specification indicates 1.8V is required. The resistor values are incorrect for the intended 1.8V output.** !thumbnail[](parallella.sdax){ diff="AllSpice-Demos/Parallella-AI-Demo:e3bd227a2e06a51e009f1a792a46dc8301aad123...c43f795f4858df4442aa64dee09c27eb5a1d49f0" pr="8" doc-id="899dffe5006059bf8b9b" diff-visibility="full" variant="default" view-coords="63.08,37.70,70.58,45.20" aspect-ratio="1.33" } - Pin 11 (FB2) is connected to net N25830704 *(from schematic)* - FB2 connects to a voltage divider consisting of R282 (10K) from the output to FB2, and R281 (56.2K) from FB2 to ground *(from schematic)* - FB2 regulation voltage is 0.8V typical *(from datasheet [ISL9307IRTAANFZ-T](<https://www.renesas.com/us/en/document/dst/isl9307-datasheet#page=5>), page 5)* - The output voltage is calculated as Vout = 0.8V × (1 + R282/R281) = 0.8V × (1 + 10K/56.2K) = 0.942V *(reasoning)* - The text note indicates the output should be 1.8V @ 1.5A max *(from schematic)* - The DCD2 output connects through R287 (0 ohm) to the 1P8V net, confirming the intended output is 1.8V *(from schematic)* - For 1.8V output, the resistor ratio should be R_TOP/R_BOT = (1.8V/0.8V) - 1 = 1.25 *(reasoning)* - The actual ratio is R282/R281 = 10K/56.2K = 0.178, which does not match the required 1.25 ratio *(reasoning)* - To achieve 1.8V output, either R282 should be changed to approximately 70K (keeping R281 = 56.2K), or R281 should be changed to approximately 8K (keeping R282 = 10K) *(reasoning)* - The feedback resistor values are incorrect and will produce 0.94V instead of the intended 1.8V *(reasoning)* Replace a datasheet: [📤 U29](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/ISL9307IRTAANFZ-T) 💬 Reply to this comment and mention @DRCY to give feedback that DRCY will incorporate on the next run. _Originally posted by @DRCY in https://hub.allspice.io/AllSpice-Demos/SystemCap-Demo-Project/pulls/8/files#diff-dcdcb94003e38cba372049b9bb4e30b1d34e6b5f-issuecomment-52773_