[Action: Emmy] Bank 34 VCCO (U2) is on unsourced net VD_GPIO, probably a typo for VDD_GPIO #16

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opened 2026-10-28 18:39:55 +00:00 by DRCY · 0 comments

DRCYAI commented

2026-10-28 18:39:55 +00:00

Owner: Emmy
Source: DRCY review comment 59310 on PR #13 (parallella.sdax, page 09-PL BANKS 34 & 35)
Severity: Error (bank 34 has no I/O supply)

Problem

All six Zynq bank 34 VCCO balls on U2 (VCCO_34_1..6: N19, R15, T18, V14, W17, Y20) and the bank 34 decoupling caps C126-C134 (pin 1) sit on a net named VD_GPIO. Across the whole design, VD_GPIO has only those 15 pins and appears only on page 9. No regulator, connector, 0 ohm link or other page connects to it, so nothing powers it.

The real I/O rail is VDD_GPIO. U30 VOLDO2 feeds it through R333 (0 ohm). It powers U2 bank 13 VCCO (T8, U11, W7, Y10) and U37 (TPD12S016) VCCA. On the same page it also feeds the bank 34 pull-ups R18 and R20. The two names differ by one letter, so a typo is the likely cause. That is an inference: the netlist can't show what the designer meant.

Impact

Bank 34 I/O won't work: GPIO0-11 on J11, the HDMI data/sync/clock lines to U26 (ADV7513), HDMI_INT, PS_I2C_SCL, PROG_IO and TURBO_MODE.
Pull-ups to the powered VDD_GPIO rail (R18, R20, R22, R328) would back-feed the unpowered bank through its I/O clamp diodes.

Action items

Confirm which voltage bank 34 is meant to run at.
If it is VDD_GPIO: rename the VD_GPIO power port/net on page 9 to VDD_GPIO.
If it is a different rail: connect VD_GPIO to that regulator, and check that the R18/R20 pull-ups (now on VDD_GPIO) match the bank 34 voltage.
Check that the chosen rail voltage suits the I/O standards used on bank 34 (HR bank, 1.2-3.3 V).
Reply on review comment 59310 and close this issue once the fix is in.

Open question

It is not yet known whether PR #13 introduced VD_GPIO or it was already in base commit e3bd227. To find out, compare page 9 between e3bd227 and c43f795.

**Owner:** Emmy **Source:** DRCY review comment 59310 on PR #13 (parallella.sdax, page 09-PL BANKS 34 & 35) **Severity:** Error (bank 34 has no I/O supply) ## Problem All six Zynq bank 34 VCCO balls on U2 (VCCO_34_1..6: N19, R15, T18, V14, W17, Y20) and the bank 34 decoupling caps C126-C134 (pin 1) sit on a net named **VD_GPIO**. Across the whole design, VD_GPIO has only those 15 pins and appears only on page 9. No regulator, connector, 0 ohm link or other page connects to it, so nothing powers it. The real I/O rail is **VDD_GPIO**. U30 VOLDO2 feeds it through R333 (0 ohm). It powers U2 bank 13 VCCO (T8, U11, W7, Y10) and U37 (TPD12S016) VCCA. On the same page it also feeds the bank 34 pull-ups **R18** and **R20**. The two names differ by one letter, so a typo is the likely cause. That is an inference: the netlist can't show what the designer meant. ## Impact - Bank 34 I/O won't work: GPIO0-11 on J11, the HDMI data/sync/clock lines to U26 (ADV7513), HDMI_INT, PS_I2C_SCL, PROG_IO and TURBO_MODE. - Pull-ups to the powered VDD_GPIO rail (R18, R20, R22, R328) would back-feed the unpowered bank through its I/O clamp diodes. ## Action items 1. Confirm which voltage bank 34 is meant to run at. 2. If it is VDD_GPIO: rename the VD_GPIO power port/net on page 9 to VDD_GPIO. 3. If it is a different rail: connect VD_GPIO to that regulator, and check that the R18/R20 pull-ups (now on VDD_GPIO) match the bank 34 voltage. 4. Check that the chosen rail voltage suits the I/O standards used on bank 34 (HR bank, 1.2-3.3 V). 5. Reply on review comment 59310 and close this issue once the fix is in. ## Open question It is not yet known whether PR #13 introduced VD_GPIO or it was already in base commit e3bd227. To find out, compare page 9 between e3bd227 and c43f795.