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Altium-component-library-demo
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Altium-component-library-demo/.allspice/pull_request_template.md

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AllSpice component review template Optional description

This short description prepends any pull request. It is fully markdown compatible. See markdown guide for examples of what you can do!

Resolved Issues

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Description

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Design Review Checklist

Process

  • Commits in correct branch
  • File names follow standard
  • Update project README page

System

  • Power
    • Supply rated for necessary country specifications
    • Estimated total worst-case power supply draw
  • Connectors
    • Sufficient Current and Voltage rating
    • Mating connectors have matching pinout
    • Same contact material specified for mating connectors
  • Testing
    • Test procedure written
  • Environmental
    • Specified min/max operating temperature
    • Specified min/max storage temperature
    • Specified min/max humidity
  • ROHS compliance requirement review

Components

  • Components meet environmental specifications
  • All components have quantity, reference designator and description
  • Suggested and alternate manufacturers listed
  • Price and stock checked for each component
  • Component derating
    • Voltage
    • Current
    • Power at worst-case operating temperature
    • Temperature at worst-case power

Schematics

  • Microcontrollers / ICs
    • Check the data sheet errata and apnotes for weird IC behaviors
  • Busses
  • Analog
    • Sufficient power rails for analog circuits
    • Amplifiers checked for stability
    • Consider signal rate-of-rise and fall for noise radiation
  • General
    • Sufficient bulk capacitance calculated
    • Polarized components checked
    • Electrolytic/tantalum capacitors checked for no reverse voltage
    • Electrolytic/tantalum capacitors temperature/voltage derating sufficient for MTBF
    • Check pin numbers of all custom-generated parts
    • Check reverse base-emitter current/voltage on bipolar transistors
    • Power nets use preferred and consistent naming (ex. no 3.3V vs +3.3V)
    • Debug resources added by design (leds, serial ports, etc.) even if unpopulated by default

PCB

  • Manufacturing
    • PCB manufacturing requirements noted on fab layer
      • Plating specified
        • Plating material
        • Plating thickness
      • Layer stack-up specified
      • Minimum trace/space specified
      • Minimum hole size specified
      • Controlled impedance specified
      • Blind or buried vias specified
  • Footprints
    • Pin 1 marked in a consistent manner
    • Component polarity marked
      • Diodes, LEDs
      • Electrolytic, tantalum capacitors
      • Keyed components like connectors
    • Footprint dimensions cross-checked with datasheet recommendation
    • Sufficient thermal pads on high-power components or nets
  • Clearance
    • Keep-out areas honored
      • Around mounting holes
      • For programming tools
      • For assembly tools (wrenches, screwdrivers etc.)
      • For connectors
    • Trace-to-trace clearance based upon voltage rating
    • Component size based upon voltage rating
  • Mechanical
    • CAD file uploaded
    • Clearance above connectors
    • Clearance below through-hole components
    • Mounting holes electrically isolated if necessary
      • Mounting holes have via stitching
    • Hole diameters leave margin for plating
  • Electrical
    • ERC passes
    • Isolation barriers are large enough
  • Signal integrity
    • Gaps in ground planes checked and minimized
    • High-speed signals avoid gaps in ground planes
    • Stubs minimized for high-speed signals
    • Differential pair spacing based upon impedance matching
    • Via fencing of sensitive RF transission lines done with the proper via spacing (< 1/20 lambda)
    • Option for a shielding can over sensitive circuitry e.g. RF?
  • Copper pour
    • All planes have been poured
    • Planes and pours checked for high-impedance paths
    • No pour between adjacent pins on ICs
  • Traces
    • Trace-pad connections sufficiently obtuse (angle 90 deg or more)
    • Trace widths sufficient for the current draw and max heating
    • No connections between adjacent pins on ICs
    • Vias for internal power traces sufficiently large
    • Mitered bends or soft curves (r > 3 trace width) for impedance sensitive traces
  • Thermal
    • Temperature sensitive components placed away from hot components
    • Thermal vias in thermal pads
  • Silk screen
    • Notes and documentation
      • Updated revision number
      • Updated date
    • No silk screen over pads / vias
    • Text is readable from at most two directions
    • Silk screen size / font will legible after printing
    • Connector pin-outs labeled
    • Fuse size and type marked on PCB
    • Functional groups marked
    • Functionality labeled
      • Test points
      • LEDs
      • Buttons
      • Connectors/terminals
      • Jumpers/fuses