Replaced Z1 and Z2 with SMD #10

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AllSpiceAlice wants to merge 1 commits from dd/research_path_a into main
5 changed files with 3398 additions and 2766 deletions
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@valentina Is this connector correctly positioned?

!thumbnail[](SingleBoardComputer.kicad_pcb){ diff="AllSpice/SingleBoardComputer:a543d861d15983c59209cc625f0323032248ab68...fd403cb83b124bd5df7b3ab76f0425ec6a0b175c" pr="10" layers="82,81,63,61,60,59,58,57,33,37,1,32,34" diff-visibility="full" variant="default" view-coords="39.9,34.1,48.0,37.8" aspect-ratio="1.404" } @valentina Is this connector correctly positioned?

View File

@ -376,18 +376,23 @@
"rule_severities": { "rule_severities": {
"bus_definition_conflict": "error", "bus_definition_conflict": "error",
"bus_entry_needed": "error", "bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error", "bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error", "bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error", "different_unit_footprint": "error",
"different_unit_net": "error", "different_unit_net": "error",
"duplicate_reference": "error", "duplicate_reference": "error",
"duplicate_sheet_names": "error", "duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error", "extra_units": "error",
"global_label_dangling": "warning", "global_label_dangling": "warning",
"hier_label_mismatch": "error", "hier_label_mismatch": "error",
"label_dangling": "error", "label_dangling": "error",
"lib_symbol_issues": "warning", "lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning", "multiple_net_names": "warning",
"net_not_bus_member": "warning", "net_not_bus_member": "warning",
"no_connect_connected": "warning", "no_connect_connected": "warning",
@ -397,6 +402,7 @@
"pin_to_pin": "warning", "pin_to_pin": "warning",
"power_pin_not_driven": "error", "power_pin_not_driven": "error",
"similar_labels": "warning", "similar_labels": "warning",
"simulation_model_issue": "error",
"unannotated": "error", "unannotated": "error",
"unit_value_mismatch": "error", "unit_value_mismatch": "error",
"unresolved_variable": "error", "unresolved_variable": "error",
@ -452,6 +458,8 @@
"schematic": { "schematic": {
"annotate_start_num": 0, "annotate_start_num": 0,
"drawing": { "drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0, "default_line_thickness": 6.0,
"default_text_size": 50.0, "default_text_size": 50.0,
"field_names": [], "field_names": [],
@ -483,7 +491,11 @@
"page_layout_descr_file": "", "page_layout_descr_file": "",
"plot_directory": "", "plot_directory": "",
"spice_adjust_passive_values": false, "spice_adjust_passive_values": false,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"", "spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65, "subpart_first_id": 65,
"subpart_id_separator": 0 "subpart_id_separator": 0
}, },