Reduce Power Draw to <15 W to Meet USB-C Spec

AleksaBjelogrlic commented

2021-11-29 22:15:16 +00:00

(Migrated from github.com)

The PCIe prototype should draw <12 W to leave ample room for the Thunderbolt stuff. It currently draws 14.5 W - Will need the new FPGA module to hit this goal.

AleksaBjelogrlic commented

2022-07-19 11:10:49 +00:00

(Migrated from github.com)

Will need to draw even less, max power sourceable through the m.2 connector on the Thunderbolt adapter is 9.24W (2.8A @3.3V), 9W to be safe and not trip OCP with a random spike. On rev 2 with the xdma core and ddr3, getting to 9W is impossible. Workaround is to directly connect the USB voltage to a boost converter (it droops to 4.75V under load) to get a stable 5V.

AleksaBjelogrlic commented

2022-07-19 11:12:40 +00:00

(Migrated from github.com)

Connection of the USB voltage does not work, as turning on the front end causes the voltage to droop below the undervoltage threshold. Will experiment with a large bulk cap or some sort of soft start mechanism to avoid this. We are still well within the 15W that we must be able to source, so I am confident that It is the voltage troop caused by the sun switching on of the front end That is the problem and not the overall current draw.

AleksaBjelogrlic commented

2022-07-19 11:14:28 +00:00

(Migrated from github.com)

Note that using 3.3 volts from the m.2 connection as initially designed for would still be possible with the much lower power consumption of the upcoming litex based FPGA design, as it will eliminate the power consumption by the DDR3 chips and DDR3 core within the FPGA.

AleksaBjelogrlic commented

2023-09-27 16:59:41 +00:00

(Migrated from github.com)

Done, also added a 12V to 5.2V buck on the PCIe cards to avoid violating the 3A maximum on the 3.3V rail

Reduce Power Draw to <15 W to Meet USB-C Spec #207