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53 lines
2.3 KiB
Markdown
53 lines
2.3 KiB
Markdown
# JLCPCB Constraints for 2 layer boards
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In order to make the boards as easy to manufacture as possible. I will choose the [2 layer boards constraints on JLCPCB](https://jlcpcb.com/capabilities/pcb-capabilities). Even though they were later manufactured using 4 layers for the sole reason of being easier to route.
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### PCB constraints
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- Minimum clearance: 0.128mm
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- Minimum track width: 0.128mm
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- Minimum connection width: 0mm
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- Minimum annular width: 0.1mm
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- Minimum via diameter: 0.5mm
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- Copper to hole clearance: 0.254mm (I mistakenly used 0.25mm! This has not been fixed as it would require retracking all the boards. The manufacturer has not complained about those 0.004mm)
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- Copper to edge clearance: 0.4mm (Some boards were manufactured with 0mm clearance, but the gerbers were later fixed)
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- Minimum through hole: 0.3mm
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- Hole to hole clearance: 0.254mm (I mistakenly used 0.25mm)
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- uVias: not used
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<p align="center">
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<img src="https://github.com/Hanqaqa/Easyduino/blob/master/Assets/JLCPCB%20Constraints/JLCPCB_2Layer_Constraints.PNG" width="60%">
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</p>
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### Assembly constraints
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- 0402 maximum package for Economic assemble. Around $15 or 15€ cheaper than the Standard Assembly which allows 0201 parts.
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- Check Confirm Parts Placement. They changed the polarity of my Tantalum capacitors on the Easyduino UNO without contacting me!! I had to resolder them later.
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## Stackup constraints
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I chose the [JLC04161H-7628](https://jlcpcb.com/impedance) stackup with the following characteristics:
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<p align="center">
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<img src="https://github.com/Hanqaqa/Easyduino/blob/master/Assets/JLCPCB%20Constraints/ImpedanceStackup.PNG" width="60%">
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</p>
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With Signal Layer (Layer 1) and a GND layer (L2) below. And with 0.2mm tracks and separated 0.15mm gives a differential pair impedance of approximately 90 Ohms.
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<p align="center">
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<img src="https://github.com/Hanqaqa/Easyduino/blob/master/Assets/JLCPCB%20Constraints/ImpedanceStackupCalculation.PNG" width="60%">
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</p>
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## Fill zones constraints
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<p align="center">
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<img src="https://github.com/Hanqaqa/Easyduino/blob/master/Assets/JLCPCB%20Constraints/FillZoneClearances.PNG" width="60%">
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</p>
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## CPL (Component Placement List)
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JLCPCB asks for the start of the position-top-pos.csv generated file by KiCad to be changed to:
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```
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Designator,Val,Package,Mid X ,Mid Y ,Rotation,Layer
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``` |