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45 lines
1.2 KiB
Plaintext
45 lines
1.2 KiB
Plaintext
{ Machine generated file created by SPI }
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{ Last modified was 15:34:23 Tuesday, July 27, 2021 }
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{ NOTE: Do not modify the contents of this file. If this is regenerated by }
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{ SPI, your modifications will be overwritten. }
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START_GLOBAL
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view_pcb './worklib/52/physical'
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design_name '52'
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design_library '52_lib'
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library '52_lib' 'standard'
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temp_dir 'temp'
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cpm_version '17.2'
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session_name 'ProjectMgr6752'
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physical_path './worklib/52/physical'
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END_GLOBAL
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START_PKGRXL
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regenerate_physical_net_name 'OFF'
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electrical_constraints 'ON'
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f2b_overwrite_constraints 'OFF'
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END_PKGRXL
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START_DESIGNSYNC
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replace_symbol '0'
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etch_removal 'NO'
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ignore_fixed 'NO'
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create_user_prop 'NO'
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run_packager 'YES'
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run_netrev 'NO'
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backannotate_forward 'YES'
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show_report 'NO'
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last_board_file 'pcb.brd'
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END_DESIGNSYNC
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START_COMPBROWSER
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Detail_Tab_Order 'PTF' 'Graphics' 'Properties' 'Attributes' 'Manufacturer Parts' 'History'
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Online_Model_Classification_Name 'Allegro Flash Model' 'Allegro Footprint Model' 'Allegro Format Model' 'Allegro Mechanical Model' 'Allegro Padstack Model' 'Allegro Shape Model' 'ConceptHDL Cell Model' 'Datasheet Model'
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END_COMPBROWSER
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START_CONSTRAINT_MGR
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EDIT_PHYSICAL_SPACING_CONSTRAINTS 'ON'
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END_CONSTRAINT_MGR
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