mirror of
https://github.com/EEVengers/ThunderScope.git
synced 2025-04-01 04:46:34 +00:00
Placed most of the FPGA decoupling
This commit is contained in:
Aleksa Bjelogrlic
parent
cd212bd7c9
commit
10f9c97653
Hardware/KiCad/Thunderscope_Rev5
LOADING design file
@ -4,196 +4,35 @@
|
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"active_layer_preset": "",
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"auto_track_width": false,
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"hidden_netclasses": [
|
||||
"Default",
|
||||
"FE_100Z_Diff",
|
||||
"FE_50Z",
|
||||
"LVDS",
|
||||
"LVDS_ADC",
|
||||
"LVDS_ADC_CLK",
|
||||
"PWR"
|
||||
],
|
||||
"hidden_nets": [
|
||||
"",
|
||||
"/Front End Trim and Bias/U5-",
|
||||
"Net-(U4-VBIAS)",
|
||||
"/ADC/+1V8A",
|
||||
"/ADC/+1V8D",
|
||||
"/VCM",
|
||||
"/FPGA/MGT_TX0_N",
|
||||
"/FPGA/MGT_TX0_P",
|
||||
"/FPGA/MGT_TX1_N",
|
||||
"/FPGA/MGT_TX1_P",
|
||||
"/FPGA/MGT_TX2_N",
|
||||
"/FPGA/MGT_TX2_P",
|
||||
"/FPGA/MGT_TX3_N",
|
||||
"/FPGA/MGT_TX3_P",
|
||||
"Net-(U7-IC1P)",
|
||||
"Net-(U7-IC1N)",
|
||||
"/Clock Generator/INTREF",
|
||||
"Net-(U7-IC2P)",
|
||||
"Net-(U7-IC2N)",
|
||||
"/Clock Generator/ADC_CLK_R_P",
|
||||
"/ADC/ADC_CLK_P",
|
||||
"/ADC/ADC_CLK_N",
|
||||
"/Clock Generator/ADC_CLK_R_N",
|
||||
"Net-(U13-VOUT)",
|
||||
"Net-(U13-C1-)",
|
||||
"Net-(U13-C1+)",
|
||||
"Net-(U13-CPOUT)",
|
||||
"Net-(U14-NR{slash}SS)",
|
||||
"Net-(U15-NR{slash}SS)",
|
||||
"/ACQ and FE Voltage Regs/+5V_R_PGA",
|
||||
"Net-(U17-VIN)",
|
||||
"Net-(U18H-VCCADC_0)",
|
||||
"Net-(C174-Pad2)",
|
||||
"Net-(U20-FB)",
|
||||
"Net-(U21-FB)",
|
||||
"Net-(C178-Pad2)",
|
||||
"Net-(U22-SS_CTRL)",
|
||||
"Net-(U22-NR{slash}SS)",
|
||||
"Net-(U23-FB)",
|
||||
"Net-(C186-Pad2)",
|
||||
"/CH1/ATTEN_50X_R",
|
||||
"/CH2/ATTEN_50X_R",
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||||
"/CH3/ATTEN_50X_R",
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"/CH4/ATTEN_50X_R",
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"/CH4/TERM_1M_R",
|
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"/CH4/ATTEN_50X",
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||||
"Net-(C1023_1-Pad1)",
|
||||
"Net-(C1023_2-Pad1)",
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||||
"Net-(C1023_3-Pad1)",
|
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"/CH4/BUF_IN",
|
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"/CH4/ATTEN_OUT_R",
|
||||
"/CH4/SW_NO",
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||||
"/CH4/SW_COM",
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||||
"/CH4/BUF_IN_AUX",
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"/CH4/OPA_OUT",
|
||||
"/CH4/DC_FB",
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"/CH4/+VPGA",
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"/TRIM_1",
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"/TRIM_2",
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"/TRIM_3",
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||||
"/TRIM_4",
|
||||
"/CH4/PGA_BIAS",
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"+2V5",
|
||||
"Net-(C1023_4-Pad1)",
|
||||
"Net-(D1000_1-K)",
|
||||
"/CH4/OUT_R_N",
|
||||
"Net-(J4-Pad2)",
|
||||
"/CH4/OUT_R_P",
|
||||
"/FPGA/TCK",
|
||||
"/FPGA/TDI",
|
||||
"/FPGA/TMS",
|
||||
"/FPGA/TDO",
|
||||
"unconnected-(J8-Pad31)",
|
||||
"unconnected-(J8-Pad23)",
|
||||
"unconnected-(J8-Pad45)",
|
||||
"unconnected-(J8-Pad67)",
|
||||
"AGND",
|
||||
"+3V3",
|
||||
"+1V8",
|
||||
"+1V2_MGT",
|
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"+1V0",
|
||||
"+1V0_MGT",
|
||||
"unconnected-(J8-Pad39)",
|
||||
"-5V",
|
||||
"unconnected-(J8-Pad47)",
|
||||
"unconnected-(J8-Pad21)",
|
||||
"unconnected-(J8-Pad55)",
|
||||
"unconnected-(J8-Pad43)",
|
||||
"unconnected-(J8-Pad29)",
|
||||
"unconnected-(J8-Pad33)",
|
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"unconnected-(J8-Pad7)",
|
||||
"unconnected-(J8-Pad41)",
|
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"unconnected-(J8-Pad27)",
|
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"+VBIAS",
|
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"unconnected-(J8-Pad57)",
|
||||
"unconnected-(J8-Pad11)",
|
||||
"unconnected-(J8-Pad37)",
|
||||
"+3V3_PGA",
|
||||
"unconnected-(J8-Pad68)",
|
||||
"unconnected-(J8-Pad25)",
|
||||
"unconnected-(J8-Pad1)",
|
||||
"unconnected-(J8-Pad53)",
|
||||
"unconnected-(J8-Pad35)",
|
||||
"unconnected-(J8-Pad9)",
|
||||
"unconnected-(J8-Pad75)",
|
||||
"unconnected-(J8-Pad51)",
|
||||
"/CH1/TERM_50Z",
|
||||
"/CH2/TERM_50Z",
|
||||
"/CH3/TERM_50Z",
|
||||
"/CH4/TERM_50Z",
|
||||
"/CH1/BNC_IN",
|
||||
"/CH2/BNC_IN",
|
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"/CH3/BNC_IN",
|
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"+1V8APLL",
|
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"/CH4/BNC_IN",
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"+5V2",
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"-VBIAS",
|
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"/CH1/TERM_50Z_R",
|
||||
"/CH2/TERM_50Z_R",
|
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"/CH3/TERM_50Z_R",
|
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"/CH4/ATTEN_IN",
|
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"/CH4/TERM_1M",
|
||||
"/CH4/TERM_50Z_R",
|
||||
"/CH4/ATTEN_OUT",
|
||||
"Net-(U17-SW)",
|
||||
"Net-(U20-SW)",
|
||||
"Net-(U21-SW)",
|
||||
"Net-(U23-SW)",
|
||||
"unconnected-(P1-PadB12)",
|
||||
"unconnected-(P1-PadA32)",
|
||||
"unconnected-(P1-PadB30)",
|
||||
"unconnected-(P1-PadA19)",
|
||||
"/Front End Trim and Bias/TRIM_SCL",
|
||||
"/Front End Trim and Bias/TRIM_SCL_5V",
|
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"/Front End Trim and Bias/TRIM_SDA",
|
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"/Front End Trim and Bias/TRIM_SDA_5V",
|
||||
"Net-(D1000_2-K)",
|
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"Net-(D1000_3-K)",
|
||||
"Net-(D1000_4-K)",
|
||||
"/CH4/DC_CPLn",
|
||||
"/ADC/ADC_CSn",
|
||||
"/ADC/ADC_RSTn",
|
||||
"/ADC/ADC_PD",
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"/CH1_N",
|
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"/CH1_P",
|
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"/CH2_N",
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"/CH2_P",
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"/CH3_P",
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"/CH3_N",
|
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"/CH4_P",
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"/CH4_N",
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"/FPGA/MGT_RX0_N",
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"/FPGA/MGT_RX0_P",
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"/FPGA/MGT_RX1_N",
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"/FPGA/MGT_RX1_P",
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"/FPGA/MGT_RX2_N",
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"/FPGA/MGT_RX2_P",
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"/FPGA/MGT_RX3_N",
|
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"/FPGA/MGT_RX3_P",
|
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"Net-(U7-OC1P)",
|
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"Net-(U7-RSTN)",
|
||||
"/Clock Generator/PLL_RSTn",
|
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"/FPGA/FPGA IO Banks/PLL_SCL",
|
||||
"/FPGA/FPGA IO Banks/PLL_SDA",
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"+1V8_ACQ",
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"/Clock Generator/IF1",
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"/Clock Generator/IF0",
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"/Clock Generator/AC0",
|
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"/Clock Generator/AC1",
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||||
"/Clock Generator/AC2",
|
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"/Clock Generator/TEST",
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"Net-(U13-VFB)",
|
||||
"Net-(U14-FB)",
|
||||
"Net-(U15-FB)",
|
||||
"Net-(U17-FB)",
|
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"/FPGA/FPGA IO Banks/PUDC",
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"Net-(U18D-INIT_B_0)",
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||||
"Net-(U18D-PROGRAM_B_0)",
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||||
"Net-(U18E-MGTRREF_216)",
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||||
"Net-(U20-EN)",
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||||
"Net-(U22-FB)",
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"/TERM_1",
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"/TERM_2",
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"/TERM_3",
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@ -206,335 +45,21 @@
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"/PGA_CSn_2",
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"/PGA_CSn_3",
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"/PGA_CSn_4",
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"/CH4/ATTEN_1X",
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"/CH4/BUF_R_BIAS",
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"/CH4/BUF_OUT",
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"/CH4/BUF_OUT_R",
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||||
"/CH4/BUF_IN_BIAS",
|
||||
"/DC_CPL_1",
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"/DC_CPL_2",
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"/DC_CPL_3",
|
||||
"/DC_CPL_4",
|
||||
"/ADC/ADC_SDATA",
|
||||
"/ADC/ADC_SCLK",
|
||||
"Net-(U18D-DONE_0)",
|
||||
"unconnected-(U1-NC-Pad1)",
|
||||
"/Front End Trim and Bias/VOUT4",
|
||||
"/Front End Trim and Bias/VOUT1",
|
||||
"GND",
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||||
"+5V",
|
||||
"/Front End Trim and Bias/VOUT3",
|
||||
"/Front End Trim and Bias/VOUT2",
|
||||
"unconnected-(U3-RDY-Pad5)",
|
||||
"unconnected-(U5-N2-Pad8)",
|
||||
"unconnected-(U5-N1-Pad1)",
|
||||
"/ADC/D3B_P",
|
||||
"/ADC/D2A_P",
|
||||
"/ADC/D1B_N",
|
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"/ADC/LCLK_N",
|
||||
"/ADC/D2B_N",
|
||||
"/ADC/D1A_N",
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||||
"/ADC/D3A_N",
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"/ADC/D3A_P",
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||||
"/ADC/FCLK_N",
|
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"/ADC/D2B_P",
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"/ADC/D1A_P",
|
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"/ADC/D2A_N",
|
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"/ADC/D4B_P",
|
||||
"/ADC/D3B_N",
|
||||
"/ADC/D1B_P",
|
||||
"/ADC/D4A_N",
|
||||
"/ADC/FCLK_P",
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||||
"/ADC/LCLK_P",
|
||||
"/ADC/D4A_P",
|
||||
"/ADC/D4B_N",
|
||||
"unconnected-(U7-OC5P{slash}NC-Pad53)",
|
||||
"unconnected-(U7-OC2P{slash}NC-Pad6)",
|
||||
"unconnected-(U7-OC8N-Pad40)",
|
||||
"unconnected-(U7-XB-Pad13)",
|
||||
"unconnected-(U7-OC5N{slash}NC-Pad52)",
|
||||
"unconnected-(U7-OC9P-Pad37)",
|
||||
"unconnected-(U7-IC3P-Pad20)",
|
||||
"unconnected-(U7-OC10P{slash}NC-Pad35)",
|
||||
"unconnected-(U7-OC4P-Pad55)",
|
||||
"unconnected-(U7-OC3N-Pad3)",
|
||||
"unconnected-(U7-XA-Pad12)",
|
||||
"unconnected-(U7-OC1N-Pad9)",
|
||||
"unconnected-(U7-OC10N{slash}NC-Pad34)",
|
||||
"unconnected-(U7-OC8P-Pad41)",
|
||||
"unconnected-(U7-OC3P-Pad2)",
|
||||
"unconnected-(U7-OC9N-Pad38)",
|
||||
"unconnected-(U7-OC7P{slash}NC-Pad45)",
|
||||
"unconnected-(U7-OC4N-Pad56)",
|
||||
"unconnected-(U7-OC2N{slash}NC-Pad5)",
|
||||
"unconnected-(U7-OC7N{slash}NC-Pad44)",
|
||||
"unconnected-(U16-NC-Pad4)",
|
||||
"unconnected-(U18C-IO_L9P_T1_DQS_34-PadN1)",
|
||||
"unconnected-(U18C-IO_L3N_T0_DQS_34-PadK1)",
|
||||
"unconnected-(U18C-IO_L9N_T1_DQS_34-PadP1)",
|
||||
"unconnected-(U18C-IO_L7N_T1_34-PadM1)",
|
||||
"/FPGA/FPGA IO Banks/FE_PG",
|
||||
"unconnected-(U18C-IO_L2P_T0_34-PadJ5)",
|
||||
"unconnected-(U18C-IO_L22P_T3_34-PadR7)",
|
||||
"unconnected-(U18C-IO_L19N_T3_VREF_34-PadP5)",
|
||||
"unconnected-(U18C-IO_L11P_T1_SRCC_34-PadN3)",
|
||||
"unconnected-(U18C-IO_L1P_T0_34-PadK6)",
|
||||
"unconnected-(U18C-IO_L10P_T1_34-PadM4)",
|
||||
"/FPGA/FPGA IO Banks/QSPI_DQ2",
|
||||
"unconnected-(U18C-IO_L20N_T3_34-PadU5)",
|
||||
"/FPGA/FPGA IO Banks/QSPI_DQ0",
|
||||
"unconnected-(U18C-IO_L7P_T1_34-PadM2)",
|
||||
"unconnected-(U18C-IO_L3P_T0_DQS_34-PadK2)",
|
||||
"unconnected-(U18C-IO_L5N_T0_34-PadL3)",
|
||||
"unconnected-(U18E-MGTREFCLK0P_216-PadD6)",
|
||||
"unconnected-(U18E-MGTREFCLK0N_216-PadD5)",
|
||||
"unconnected-(U18C-IO_0_34-PadJ6)",
|
||||
"unconnected-(U18C-IO_L19P_T3_34-PadP6)",
|
||||
"/FPGA/FPGA IO Banks/QSPI_DQ1",
|
||||
"unconnected-(U18C-IO_L16N_T2_34-PadV2)",
|
||||
"unconnected-(U18C-IO_L6N_T0_VREF_34-PadM5)",
|
||||
"unconnected-(U18C-IO_L14P_T2_SRCC_34-PadR3)",
|
||||
"unconnected-(U18C-IO_L16P_T2_34-PadV3)",
|
||||
"unconnected-(U18C-IO_L21N_T3_DQS_34-PadT5)",
|
||||
"unconnected-(U18C-IO_L18N_T2_34-PadV4)",
|
||||
"unconnected-(U18C-IO_L24P_T3_34-PadV8)",
|
||||
"unconnected-(U18C-IO_L2N_T0_34-PadJ4)",
|
||||
"unconnected-(U18C-IO_L1N_T0_34-PadK5)",
|
||||
"/PGA_SDIO",
|
||||
"unconnected-(U18C-IO_L12P_T1_MRCC_34-PadP4)",
|
||||
"unconnected-(U18C-IO_L17N_T2_34-PadT3)",
|
||||
"unconnected-(U18C-IO_L20P_T3_34-PadU6)",
|
||||
"unconnected-(U18C-IO_L4P_T0_34-PadK3)",
|
||||
"unconnected-(U18C-IO_L4N_T0_34-PadL2)",
|
||||
"unconnected-(U18C-IO_L18P_T2_34-PadU4)",
|
||||
"unconnected-(U18C-IO_L23N_T3_34-PadV6)",
|
||||
"unconnected-(U18A-IO_0_14-PadL14)",
|
||||
"unconnected-(U18C-IO_L6P_T0_34-PadL5)",
|
||||
"unconnected-(U18C-IO_L14N_T2_SRCC_34-PadT2)",
|
||||
"unconnected-(U18B-IO_25_15-PadH14)",
|
||||
"unconnected-(U18C-IO_L15N_T2_DQS_34-PadU1)",
|
||||
"unconnected-(U18C-IO_25_34-PadR6)",
|
||||
"unconnected-(U18C-IO_L11N_T1_SRCC_34-PadN2)",
|
||||
"unconnected-(U18C-IO_L21P_T3_DQS_34-PadR5)",
|
||||
"unconnected-(U18C-IO_L10N_T1_34-PadN4)",
|
||||
"/PGA_SCLK",
|
||||
"unconnected-(U18C-IO_L17P_T2_34-PadT4)",
|
||||
"unconnected-(U18C-IO_L22N_T3_34-PadT7)",
|
||||
"unconnected-(U18C-IO_L8N_T1_34-PadN6)",
|
||||
"unconnected-(U18C-IO_L13P_T2_MRCC_34-PadR2)",
|
||||
"unconnected-(U18C-IO_L5P_T0_34-PadL4)",
|
||||
"unconnected-(U18C-IO_L15P_T2_DQS_34-PadU2)",
|
||||
"unconnected-(U18C-IO_L12N_T1_MRCC_34-PadP3)",
|
||||
"unconnected-(U18C-IO_L23P_T3_34-PadU7)",
|
||||
"unconnected-(U18C-IO_L8P_T1_34-PadM6)",
|
||||
"unconnected-(U18C-IO_L13N_T2_MRCC_34-PadR1)",
|
||||
"/FPGA/FPGA IO Banks/QSPI_DQ3",
|
||||
"unconnected-(U18C-IO_L24N_T3_34-PadV7)",
|
||||
"unconnected-(U22-PG-Pad5)",
|
||||
"unconnected-(U23-PG-Pad6)",
|
||||
"Net-(D1001_1-K)",
|
||||
"Net-(D1001_2-K)",
|
||||
"Net-(D1001_3-K)",
|
||||
"Net-(D1001_4-K)",
|
||||
"Net-(C1058_1-Pad1)",
|
||||
"Net-(C1058_2-Pad1)",
|
||||
"Net-(C1058_3-Pad1)",
|
||||
"Net-(C1058_4-Pad1)",
|
||||
"+VUSB",
|
||||
"Net-(D1-R)",
|
||||
"Net-(D1-G)",
|
||||
"Net-(D1-B)",
|
||||
"+3V3_ACQ",
|
||||
"/MGT_CLK1_N",
|
||||
"/MGT_CLK1_P",
|
||||
"/REFINOUT",
|
||||
"Net-(C74-Pad2)",
|
||||
"Net-(U8-FB)",
|
||||
"Net-(U14-EN)",
|
||||
"/TS-PCIe Components/+12V_PCIe_R",
|
||||
"Net-(U11-BST)",
|
||||
"Net-(U11-SW)",
|
||||
"Net-(U11-FB)",
|
||||
"Net-(U13-VIN)",
|
||||
"Net-(C119-Pad2)",
|
||||
"Net-(D1000_1-A)",
|
||||
"Net-(D1000_2-A)",
|
||||
"Net-(D1000_3-A)",
|
||||
"/CH4/DC_FB_TRIM",
|
||||
"Net-(D1000_4-A)",
|
||||
"/TS-USB4 Components/REFINOUT1",
|
||||
"/TS-USB4 Components/SYNC1",
|
||||
"/TS-PCIe Components/REFINOUT2",
|
||||
"/TS-PCIe Components/SYNC2",
|
||||
"/TS-USB4 Components/+VUSB_M2",
|
||||
"/SPRING",
|
||||
"Net-(U8-SW)",
|
||||
"/TS-PCIe Components/JTAG1",
|
||||
"/TS-PCIe Components/JTAG3",
|
||||
"/TS-PCIe Components/3.3Vaux",
|
||||
"/TS-PCIe Components/+12V_PCIe",
|
||||
"/TS-PCIe Components/JTAG4",
|
||||
"/TS-PCIe Components/PRSNT1#",
|
||||
"/TS-PCIe Components/WAKE#",
|
||||
"/TS-PCIe Components/PRSNT2#_1",
|
||||
"/TS-PCIe Components/PRSNT2#_4",
|
||||
"Net-(D1001_1-A)",
|
||||
"/TS-PCIe Components/SMDAT",
|
||||
"/TS-PCIe Components/JTAG5",
|
||||
"/TS-PCIe Components/SMCLK",
|
||||
"/TS-PCIe Components/JTAG2",
|
||||
"/FPGA/FPGA Voltage Regs/PG_1V8",
|
||||
"/SYNC",
|
||||
"/FPGA/LED_G",
|
||||
"/COMP",
|
||||
"/FPGA/PROBE_COMP",
|
||||
"/PERST#",
|
||||
"/FPGA/FPGA IO Banks/ACQ_PG",
|
||||
"/FPGA/SYNC_REn",
|
||||
"/FPGA/SYNC_DE",
|
||||
"Net-(U10-RO)",
|
||||
"/FPGA/LED_R",
|
||||
"/FPGA/LED_B",
|
||||
"/FPGA/FPGA Config and Transceivers/QSPI_CS",
|
||||
"Net-(U17-EN)",
|
||||
"/FPGA/FPGA IO Banks/HWID0",
|
||||
"/FPGA/FPGA IO Banks/HWID1",
|
||||
"/FPGA/FPGA IO Banks/HWID2",
|
||||
"/VARIANT",
|
||||
"/FPGA/FPGA IO Banks/ACQ_EN",
|
||||
"/ACQ and FE Voltage Regs/FE_EN",
|
||||
"/FPGA/FPGA Voltage Regs/PG_1V0",
|
||||
"/FPGA/FPGA Config and Transceivers/QSPI_CLK",
|
||||
"unconnected-(U8-PG-Pad6)",
|
||||
"unconnected-(U9-NC-Pad4)",
|
||||
"unconnected-(U10-NC-Pad6)",
|
||||
"unconnected-(U10-NC-Pad3)",
|
||||
"unconnected-(U10-NC-Pad13)",
|
||||
"unconnected-(U10-NC-Pad5)",
|
||||
"unconnected-(U18B-IO_0_15-PadD10)",
|
||||
"/FPGA/CLK25",
|
||||
"/ACQ and FE Voltage Regs/+VUSB_R_ACQ",
|
||||
"/ACQ and FE Voltage Regs/+2V5_R_ACQ",
|
||||
"/CH1/TERM_1M_R",
|
||||
"/CH2/TERM_1M_R",
|
||||
"/CH3/TERM_1M_R",
|
||||
"/CH1/ATTEN_50X",
|
||||
"Net-(D1001_2-A)",
|
||||
"Net-(D1001_3-A)",
|
||||
"/CH2/ATTEN_50X",
|
||||
"/CH3/ATTEN_50X",
|
||||
"Net-(D1001_4-A)",
|
||||
"unconnected-(P1-PadA9)",
|
||||
"unconnected-(P1-PadA10)",
|
||||
"unconnected-(P1-PadB8)",
|
||||
"Net-(Q1002_1-G)",
|
||||
"Net-(Q1002_2-G)",
|
||||
"Net-(Q1002_3-G)",
|
||||
"/CH1/BUF_IN",
|
||||
"/CH1/ATTEN_OUT_R",
|
||||
"/CH2/BUF_IN",
|
||||
"/CH2/ATTEN_OUT_R",
|
||||
"/CH3/BUF_IN",
|
||||
"/CH3/ATTEN_OUT_R",
|
||||
"/CH1/SW_COM",
|
||||
"/CH1/SW_NO",
|
||||
"/CH2/SW_COM",
|
||||
"/CH2/SW_NO",
|
||||
"/CH3/SW_NO",
|
||||
"/CH3/SW_COM",
|
||||
"/CH1/BUF_IN_AUX",
|
||||
"/CH2/BUF_IN_AUX",
|
||||
"/CH3/BUF_IN_AUX",
|
||||
"/CH1/DC_FB",
|
||||
"/CH1/OPA_OUT",
|
||||
"/CH2/DC_FB",
|
||||
"/CH2/OPA_OUT",
|
||||
"/CH3/DC_FB",
|
||||
"/CH3/OPA_OUT",
|
||||
"/CH1/+VPGA",
|
||||
"/CH2/+VPGA",
|
||||
"/CH3/+VPGA",
|
||||
"/CH1/PGA_BIAS",
|
||||
"/CH2/PGA_BIAS",
|
||||
"/CH3/PGA_BIAS",
|
||||
"Net-(Q1002_4-G)",
|
||||
"Net-(Q1003_1-G)",
|
||||
"Net-(Q1003_2-G)",
|
||||
"Net-(Q1003_3-G)",
|
||||
"Net-(Q1003_4-G)",
|
||||
"Net-(Q1004_1-G)",
|
||||
"/CH1/OUT_R_N",
|
||||
"/CH2/OUT_R_N",
|
||||
"/CH3/OUT_R_N",
|
||||
"/CH1/OUT_R_P",
|
||||
"/CH2/OUT_R_P",
|
||||
"/CH3/OUT_R_P",
|
||||
"/CH1/TERM_1M",
|
||||
"/CH1/ATTEN_IN",
|
||||
"/CH2/TERM_1M",
|
||||
"/CH2/ATTEN_IN",
|
||||
"/CH3/TERM_1M",
|
||||
"/CH3/ATTEN_IN",
|
||||
"/CH1/ATTEN_1X",
|
||||
"/CH1/ATTEN_OUT",
|
||||
"/CH2/ATTEN_OUT",
|
||||
"/CH2/ATTEN_1X",
|
||||
"/CH3/ATTEN_1X",
|
||||
"/CH3/ATTEN_OUT",
|
||||
"Net-(Q1004_2-G)",
|
||||
"Net-(Q1004_3-G)",
|
||||
"Net-(Q1004_4-G)",
|
||||
"unconnected-(U1008_1-AUX_N-Pad2)",
|
||||
"unconnected-(U1008_1-AUX_P-Pad1)",
|
||||
"unconnected-(U1008_1-AUX_VCM-Pad16)",
|
||||
"/CH1/DC_CPLn",
|
||||
"unconnected-(U1008_2-AUX_VCM-Pad16)",
|
||||
"/CH2/DC_CPLn",
|
||||
"unconnected-(U1008_2-AUX_P-Pad1)",
|
||||
"unconnected-(U1008_2-AUX_N-Pad2)",
|
||||
"/CH3/DC_CPLn",
|
||||
"/CH1/BUF_R_BIAS",
|
||||
"/CH2/BUF_R_BIAS",
|
||||
"/CH3/BUF_R_BIAS",
|
||||
"/CH1/BUF_OUT",
|
||||
"/CH1/BUF_OUT_R",
|
||||
"/CH2/BUF_OUT_R",
|
||||
"/CH2/BUF_OUT",
|
||||
"/CH3/BUF_OUT",
|
||||
"/CH3/BUF_OUT_R",
|
||||
"/CH1/BUF_IN_BIAS",
|
||||
"/CH2/BUF_IN_BIAS",
|
||||
"/CH3/BUF_IN_BIAS",
|
||||
"/CH1/DC_FB_TRIM",
|
||||
"/CH2/DC_FB_TRIM",
|
||||
"/CH3/DC_FB_TRIM",
|
||||
"unconnected-(U1008_3-AUX_P-Pad1)",
|
||||
"unconnected-(U1008_3-AUX_VCM-Pad16)",
|
||||
"unconnected-(U1008_3-AUX_N-Pad2)",
|
||||
"unconnected-(U1008_4-AUX_VCM-Pad16)",
|
||||
"unconnected-(U1008_4-AUX_N-Pad2)",
|
||||
"unconnected-(U1008_4-AUX_P-Pad1)",
|
||||
"unconnected-(U1009_1-NC-Pad16)",
|
||||
"unconnected-(U1009_1-NC-Pad13)",
|
||||
"unconnected-(U1009_1-NC-Pad9)",
|
||||
"unconnected-(U1009_2-NC-Pad16)",
|
||||
"unconnected-(U1009_2-NC-Pad9)",
|
||||
"unconnected-(U1009_2-NC-Pad13)",
|
||||
"unconnected-(U1009_3-NC-Pad16)",
|
||||
"unconnected-(U1009_3-NC-Pad13)",
|
||||
"unconnected-(U1009_3-NC-Pad9)",
|
||||
"unconnected-(U1009_4-NC-Pad13)",
|
||||
"unconnected-(U1009_4-NC-Pad9)",
|
||||
"unconnected-(U1009_4-NC-Pad16)",
|
||||
"unconnected-(U1011_1-N2-Pad8)",
|
||||
"unconnected-(U1011_1-N1-Pad1)",
|
||||
"unconnected-(U1011_2-N2-Pad8)",
|
||||
"unconnected-(U1011_2-N1-Pad1)",
|
||||
"unconnected-(U1011_3-N1-Pad1)",
|
||||
"unconnected-(U1011_3-N2-Pad8)",
|
||||
"unconnected-(U1011_4-N2-Pad8)",
|
||||
"unconnected-(U1011_4-N1-Pad1)",
|
||||
"unconnected-(U18A-IO_L5P_T0_D06_14-PadJ14)"
|
||||
"/FPGA/LED_B"
|
||||
],
|
||||
"high_contrast_mode": 0,
|
||||
"net_color_mode": 1,
|
||||
@ -549,7 +74,7 @@
|
||||
"selection_filter": {
|
||||
"dimensions": false,
|
||||
"footprints": true,
|
||||
"graphics": false,
|
||||
"graphics": true,
|
||||
"keepouts": false,
|
||||
"lockedItems": false,
|
||||
"otherItems": false,
|
||||
@ -579,7 +104,7 @@
|
||||
"conflict_shadows",
|
||||
"shapes"
|
||||
],
|
||||
"visible_layers": "00000000_00000000_00000000_00000001",
|
||||
"visible_layers": "00000000_00000000_00000000_02000025",
|
||||
"zone_display_mode": 0
|
||||
},
|
||||
"git": {
|
||||
|
||||
@ -548,18 +548,26 @@
|
||||
"via_drill": 0.2032,
|
||||
"wire_width": 6
|
||||
},
|
||||
{
|
||||
"clearance": 0.127,
|
||||
"name": "50Z",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 0,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.213
|
||||
},
|
||||
{
|
||||
"clearance": 0.127,
|
||||
"name": "FE_100Z_Diff",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 5,
|
||||
"priority": 6,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)"
|
||||
},
|
||||
{
|
||||
"clearance": 0.127,
|
||||
"name": "FE_50Z",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 7,
|
||||
"priority": 8,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.213,
|
||||
"via_diameter": 2.0,
|
||||
@ -569,40 +577,40 @@
|
||||
"clearance": 0.127,
|
||||
"name": "LVDS_ADC",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 2,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)"
|
||||
},
|
||||
{
|
||||
"name": "LVDS_ADC_CLK",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 0,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)"
|
||||
},
|
||||
{
|
||||
"clearance": 0.127,
|
||||
"name": "LVDS_SYNC",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 4,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)"
|
||||
},
|
||||
{
|
||||
"clearance": 0.127,
|
||||
"name": "LVDS_USRIO",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 3,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)"
|
||||
},
|
||||
{
|
||||
"name": "PCIe",
|
||||
"name": "LVDS_ADC_CLK",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 1,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)"
|
||||
},
|
||||
{
|
||||
"clearance": 0.127,
|
||||
"name": "LVDS_SYNC",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 5,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)"
|
||||
},
|
||||
{
|
||||
"clearance": 0.127,
|
||||
"name": "LVDS_USRIO",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 4,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)"
|
||||
},
|
||||
{
|
||||
"name": "PCIe",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 2,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)"
|
||||
},
|
||||
{
|
||||
"clearance": 0.127,
|
||||
"name": "PWR",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 6,
|
||||
"priority": 7,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.254,
|
||||
"via_diameter": 0.4064,
|
||||
@ -722,6 +730,30 @@
|
||||
{
|
||||
"netclass": "LVDS_ADC",
|
||||
"pattern": "/ADC/LCLK*"
|
||||
},
|
||||
{
|
||||
"netclass": "50Z",
|
||||
"pattern": "*s/SYNC*"
|
||||
},
|
||||
{
|
||||
"netclass": "50Z",
|
||||
"pattern": "/SYNC"
|
||||
},
|
||||
{
|
||||
"netclass": "50Z",
|
||||
"pattern": "*s/REFINOUT*"
|
||||
},
|
||||
{
|
||||
"netclass": "50Z",
|
||||
"pattern": "/REFINOUT"
|
||||
},
|
||||
{
|
||||
"netclass": "50Z",
|
||||
"pattern": "*U7-*C1P*"
|
||||
},
|
||||
{
|
||||
"netclass": "50Z",
|
||||
"pattern": "*U10-R*"
|
||||
}
|
||||
]
|
||||
},
|
||||
|
||||
Loading…
Reference in New Issue
Block a user