AllSpiceMirrors/ThunderScope
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Fixed ADC inversion

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This commit is contained in:
Aleksa 2022-02-12 22:24:32 -05:00
parent 1828184354
commit 257a5dbada
5 changed files with 47 additions and 33 deletions
Firmware/Artix7_PCIe/dso_top
dso_top.bin
dso_top.srcs/sources_1
bd/design_1/ui
bd_1f5defd0.uibd_d985a9f1.ui
imports/hdl
dso_top.v
dso_top.xpr

BIN
Firmware/Artix7_PCIe/dso_top/dso_top.bin
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Binary file not shown.

40
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
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@ -1,7 +1,7 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"1.0",
"Default View_TopLeft":"548,-140",
"Default View_TopLeft":"-332,24",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:9.0 non-TLS
# -string -flagsOSRD
@ -24,26 +24,40 @@ preplace inst Memory -pg 1 -lvl 2 -x 1480 -y 290 -defaultsOSRD
preplace inst Datamover -pg 1 -lvl 1 -x 190 -y 180 -defaultsOSRD
preplace inst AXI_LITE_IO -pg 1 -lvl 2 -x 1480 -y 90 -defaultsOSRD
preplace inst PCIe -pg 1 -lvl 1 -x 190 -y 372 -defaultsOSRD
preplace inst PCIe|util_ds_buf_0 -pg 1 -lvl 1 -x 280 -y 382 -defaultsOSRD
preplace inst PCIe|axi_dwidth_converter_0 -pg 1 -lvl 3 -x 950 -y 492 -defaultsOSRD
preplace inst PCIe|xdma_0 -pg 1 -lvl 2 -x 600 -y 442 -defaultsOSRD
preplace netloc sys_rst_n_0_1 1 0 1 -10J 380n
preplace netloc xdma_0_axi_aclk 1 0 3 -10 270 390 200 NJ
preplace netloc Datamover_s2mm_err_0 1 1 2 360J 170 1630J
preplace netloc Datamover_s2mm_wr_xfer_cmplt_0 1 1 2 370J 180 NJ
preplace netloc xdma_0_axi_aclk 1 0 3 0 270 1300 200 NJ
preplace netloc Datamover_s2mm_err_0 1 1 2 1270J 170 1630J
preplace netloc Datamover_s2mm_wr_xfer_cmplt_0 1 1 2 1280J 180 NJ
preplace netloc gpio2_io_i_0_1 1 0 2 NJ 80 NJ
preplace netloc PCIe_axi_aresetn 1 1 2 410 190 1630J
preplace netloc PCIe_axi_aresetn 1 1 2 1320 190 1630J
preplace netloc S01_ARESETN_0_1 1 0 1 NJ 200
preplace netloc s2mm_halt_0_1 1 0 1 NJ 220
preplace netloc AXI_LITE_IO_gpio_io_o_0 1 2 1 NJ 100
preplace netloc AXI_LITE_IO_AXI_STR_TXD_0 1 2 1 NJ 80
preplace netloc PCIe_M_AXI_LITE 1 1 1 1260 60n
preplace netloc xdma_0_pcie_mgt 1 1 2 1330J 370 NJ
preplace netloc Datamover_M_AXI_S2MM 1 1 1 1290 160n
preplace netloc CLK_IN_D_0_1 1 0 1 0J 360n
preplace netloc xdma_0_M_AXI 1 1 1 1310 260n
preplace netloc mig_7series_0_DDR3 1 2 1 NJ 290
preplace netloc S_AXIS_S2MM_0_1 1 0 1 NJ 160
preplace netloc S_AXIS_S2MM_CMD_0_1 1 0 1 NJ 140
preplace netloc xdma_0_M_AXI 1 1 1 400 260n
preplace netloc CLK_IN_D_0_1 1 0 1 -10J 360n
preplace netloc mig_7series_0_DDR3 1 2 1 NJ 290
preplace netloc AXI_LITE_IO_AXI_STR_TXD_0 1 2 1 NJ 80
preplace netloc PCIe_M_AXI_LITE 1 1 1 350 60n
preplace netloc xdma_0_pcie_mgt 1 1 2 420J 370 NJ
preplace netloc Datamover_M_AXI_S2MM 1 1 1 380 160n
preplace netloc PCIe|util_ds_buf_0_IBUF_OUT 1 1 1 430 372n
preplace netloc PCIe|xdma_0_axi_aclk 1 2 2 790 412 1110J
preplace netloc PCIe|PCIe_axi_aresetn 1 2 2 770 572 NJ
preplace netloc PCIe|sys_rst_n_0_1 1 0 2 NJ 452 N
preplace netloc PCIe|CLK_IN_D_0_1 1 0 1 NJ 382
preplace netloc PCIe|xdma_0_pcie_mgt 1 2 2 N 402 NJ
preplace netloc PCIe|xdma_0_M_AXI1 1 2 1 780 362n
preplace netloc PCIe|PCIe_M_AXI_LITE 1 2 2 N 382 NJ
preplace netloc PCIe|xdma_0_M_AXI 1 3 1 1120 362n
levelinfo -pg 1 -30 190 1480 1650
pagesize -pg 1 -db -bbox -sgen -200 0 1830 610
levelinfo -hier PCIe * 280 600 950 *
pagesize -pg 1 -db -bbox -sgen -220 0 1840 610
pagesize -hier PCIe -db -bbox -sgen 100 302 1150 582
"
}
{

8
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/ui/bd_d985a9f1.ui
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@ -1,7 +1,7 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"0.988235",
"Default View_TopLeft":"-294,-53",
"Default View_TopLeft":"-349,40",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:9.0 non-TLS
# -string -flagsOSRD
@ -25,11 +25,11 @@ preplace netloc xdma_0_axi_aclk 1 0 3 NJ 100 300 240 620
preplace netloc S00_ARESETN_1 1 0 3 NJ 120 310 220 610
preplace netloc util_vector_logic_0_Res 1 1 2 290 230 630J
preplace netloc mig_7series_0_ui_clk 1 2 3 640 290 NJ 290 1240
preplace netloc axi_crossbar_0_M00_AXI 1 2 1 610 100n
preplace netloc S01_AXI_1 1 0 2 NJ 80 320
preplace netloc axi_clock_converter_0_M_AXI 1 3 1 960 140n
preplace netloc S00_AXI_1 1 0 2 NJ 60 330
preplace netloc axi_crossbar_0_M00_AXI 1 2 1 610 100n
preplace netloc mig_7series_0_DDR3 1 4 1 N 140
preplace netloc S00_AXI_1 1 0 2 NJ 60 330
preplace netloc axi_clock_converter_0_M_AXI 1 3 1 960 140n
levelinfo -pg 1 -30 140 470 800 1110 1280
pagesize -pg 1 -db -bbox -sgen -180 -140 1370 760
"

30
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/imports/hdl/dso_top.v
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@ -113,17 +113,17 @@ module dso_top
end
assign probe_comp = probe_div_clk;
// reg[63:0] twos_comp;
// always @(*) begin
// twos_comp[63:56] <= {data_deser[63],~data_deser[62:56]};
// twos_comp[55:48] <= {data_deser[55],~data_deser[54:48]};
// twos_comp[47:40] <= {data_deser[47],~data_deser[46:40]};
// twos_comp[39:32] <= {data_deser[39],~data_deser[38:32]};
// twos_comp[31:24] <= {data_deser[31],~data_deser[30:24]};
// twos_comp[23:16] <= {~data_deser[23],data_deser[22:16]};
// twos_comp[15:8] <= {data_deser[15],~data_deser[14:8]};
// twos_comp[7:0] <= {data_deser[7],~data_deser[6:0]};
// end
reg[63:0] twos_comp;
always @(*) begin
twos_comp[63:56] <= ~data_deser[63:56];
twos_comp[55:48] <= ~data_deser[55:48];
twos_comp[47:40] <= ~data_deser[47:40];
twos_comp[39:32] <= ~data_deser[39:32];
twos_comp[31:24] <= ~data_deser[31:24];
twos_comp[23:16] <= data_deser[23:16];
twos_comp[15:8] <= ~data_deser[15:8];
twos_comp[7:0] <= ~data_deser[7:0];
end
wire[1:0] channel_mux;
reg [2:0] channel_mux_cdc_0;
@ -139,10 +139,10 @@ module dso_top
always @(*)
begin
case(channel_mux)
2'b00: adc_data <= {data_deser[63:0]};
2'b01: adc_data <= {data_deser[63:56],data_deser[31:24],data_deser[55:48],data_deser[23:16],data_deser[47:40],data_deser[15:8],data_deser[39:32],data_deser[7:0]};
2'b10: adc_data <= {data_deser[63:56],data_deser[47:40],data_deser[31:24],data_deser[15:8],data_deser[55:48],data_deser[39:32],data_deser[23:16],data_deser[7:0]};
2'b11: adc_data <= {data_deser[63:56],data_deser[47:40],data_deser[31:24],data_deser[15:8],data_deser[55:48],data_deser[39:32],data_deser[23:16],data_deser[7:0]};
2'b00: adc_data <= {twos_comp[63:0]};
2'b01: adc_data <= {twos_comp[63:56],twos_comp[31:24],twos_comp[55:48],twos_comp[23:16],twos_comp[47:40],twos_comp[15:8],twos_comp[39:32],twos_comp[7:0]};
2'b10: adc_data <= {twos_comp[63:56],twos_comp[47:40],twos_comp[31:24],twos_comp[15:8],twos_comp[55:48],twos_comp[39:32],twos_comp[23:16],twos_comp[7:0]};
2'b11: adc_data <= {twos_comp[63:56],twos_comp[47:40],twos_comp[31:24],twos_comp[15:8],twos_comp[55:48],twos_comp[39:32],twos_comp[23:16],twos_comp[7:0]};
endcase
end

2
Firmware/Artix7_PCIe/dso_top/dso_top.xpr
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@ -6,7 +6,7 @@
<Project Version="7" Minor="49" Path="C:/Users/Aleksa/Documents/EEVengers/Firmware/Artix7_PCIe/dso_top/dso_top.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="76aeefaed230471a9993f78fa3eb617c"/>
<Option Name="Id" Val="7e3f8705bf184e3597552c98dd889925"/>
<Option Name="Part" Val="xc7a100tfgg484-2"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>