mirror of
https://github.com/EEVengers/ThunderScope.git
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Got delay tuner to write to rules file
This commit is contained in:
Aleksa Bjelogrlic
parent
6622021a9f
commit
2b4dbd54a7
@ -11,9 +11,6 @@
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(rule FE_100Z_Diff_Vias
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(condition "A.hasNetclass('FE_100Z_Diff')")
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(constraint via_count (min 0) (opt 0) (max 0)))
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(rule "FE_100Z_Diff_Skew"
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(condition "A.hasNetclass('FE_100Z_Diff')")
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(constraint skew (min -0.1mm)(opt 0mm)(max 0.1mm)))
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(rule LVDS_SYNC_Inner
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(layer inner)
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@ -25,9 +22,6 @@
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(condition "A.hasNetclass('LVDS_SYNC')")
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(constraint diff_pair_gap (min 0.13022mm)(opt 0.13022mm)(max 0.13022mm))
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(constraint track_width (min 0.127mm)(opt 0.127mm)(max 0.127mm)))
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(rule "LVDS_SYNC_Skew"
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(condition "A.hasNetclass('LVDS_SYNC')")
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(constraint skew (min -0.1mm)(opt 0mm)(max 0.1mm)))
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(rule LVDS_USRIO_Inner
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(layer inner)
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@ -39,9 +33,6 @@
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(condition "A.hasNetclass('LVDS_USRIO')")
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(constraint diff_pair_gap (min 0.13022mm)(opt 0.13022mm)(max 0.13022mm))
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(constraint track_width (min 0.127mm)(opt 0.127mm)(max 0.127mm)))
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(rule "LVDS_USRIO_Skew"
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(condition "A.hasNetclass('LVDS_USRIO')")
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(constraint skew (min -0.1mm)(opt 0mm)(max 0.1mm)))
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(rule LVDS_ADC_Inner
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(layer inner)
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@ -53,9 +44,6 @@
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(condition "A.hasNetclass('LVDS_ADC')")
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(constraint diff_pair_gap (opt 0.13022mm))
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(constraint track_width (min 0.127mm)(opt 0.127mm)(max 0.127mm)))
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(rule "LVDS_ADC_Skew"
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(condition "A.hasNetclass('LVDS_ADC')")
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(constraint skew (min -0.1mm)(opt 0mm)(max 0.1mm)))
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(rule PCIe_Inner
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(layer inner)
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@ -95,3 +83,66 @@
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(rule "Distance between test points"
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(constraint courtyard_clearance (min 0.5mm))
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(condition "A.Reference =='TP*' && B.Reference == 'TP*"))
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# DELAY TUNER RULES
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(rule "/ADC/D1A_N length"
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(condition "A.NetName == '/ADC/D1A_N'")
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(constraint length (min 34.82806759315393mm) (opt 34.82806759315393mm) (max 34.82806759315393mm)))
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(rule "/ADC/D1A_P length"
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(condition "A.NetName == '/ADC/D1A_P'")
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(constraint length (min 36.89469188869957mm) (opt 36.89469188869957mm) (max 36.89469188869957mm)))
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(rule "/ADC/D1B_N length"
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(condition "A.NetName == '/ADC/D1B_N'")
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(constraint length (min 37.06227302964431mm) (opt 37.06227302964431mm) (max 37.06227302964431mm)))
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(rule "/ADC/D1B_P length"
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(condition "A.NetName == '/ADC/D1B_P'")
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(constraint length (min 36.71416456519255mm) (opt 36.71416456519255mm) (max 36.71416456519255mm)))
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(rule "/ADC/D2A_N length"
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(condition "A.NetName == '/ADC/D2A_N'")
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(constraint length (min 42.020571046942656mm) (opt 42.020571046942656mm) (max 42.020571046942656mm)))
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(rule "/ADC/D2A_P length"
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(condition "A.NetName == '/ADC/D2A_P'")
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(constraint length (min 41.35842775131061mm) (opt 41.35842775131061mm) (max 41.35842775131061mm)))
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(rule "/ADC/D2B_N length"
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(condition "A.NetName == '/ADC/D2B_N'")
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(constraint length (min 41.29252808590692mm) (opt 41.29252808590692mm) (max 41.29252808590692mm)))
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(rule "/ADC/D2B_P length"
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(condition "A.NetName == '/ADC/D2B_P'")
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(constraint length (min 42.03297780523148mm) (opt 42.03297780523148mm) (max 42.03297780523148mm)))
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(rule "/ADC/D3A_N length"
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(condition "A.NetName == '/ADC/D3A_N'")
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(constraint length (min 41.6693159408959mm) (opt 41.6693159408959mm) (max 41.6693159408959mm)))
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(rule "/ADC/D3A_P length"
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(condition "A.NetName == '/ADC/D3A_P'")
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(constraint length (min 41.86207021460058mm) (opt 41.86207021460058mm) (max 41.86207021460058mm)))
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(rule "/ADC/D3B_N length"
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(condition "A.NetName == '/ADC/D3B_N'")
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(constraint length (min 38.44886312448925mm) (opt 38.44886312448925mm) (max 38.44886312448925mm)))
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(rule "/ADC/D3B_P length"
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(condition "A.NetName == '/ADC/D3B_P'")
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(constraint length (min 37.88444552639311mm) (opt 37.88444552639311mm) (max 37.88444552639311mm)))
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(rule "/ADC/D4A_N length"
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(condition "A.NetName == '/ADC/D4A_N'")
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(constraint length (min 37.35392175347736mm) (opt 37.35392175347736mm) (max 37.35392175347736mm)))
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(rule "/ADC/D4A_P length"
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(condition "A.NetName == '/ADC/D4A_P'")
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(constraint length (min 38.16009133011448mm) (opt 38.16009133011448mm) (max 38.16009133011448mm)))
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(rule "/ADC/D4B_N length"
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(condition "A.NetName == '/ADC/D4B_N'")
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(constraint length (min 41.093570433057806mm) (opt 41.093570433057806mm) (max 41.093570433057806mm)))
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(rule "/ADC/D4B_P length"
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(condition "A.NetName == '/ADC/D4B_P'")
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(constraint length (min 43.79806393193124mm) (opt 43.79806393193124mm) (max 43.79806393193124mm)))
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(rule "/ADC/FCLK_N length"
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(condition "A.NetName == '/ADC/FCLK_N'")
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(constraint length (min 40.077205197875166mm) (opt 40.077205197875166mm) (max 40.077205197875166mm)))
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(rule "/ADC/FCLK_P length"
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(condition "A.NetName == '/ADC/FCLK_P'")
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(constraint length (min 39.56034683988622mm) (opt 39.56034683988622mm) (max 39.56034683988622mm)))
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(rule "/ADC/LCLK_N length"
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(condition "A.NetName == '/ADC/LCLK_N'")
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(constraint length (min 41.051585243776046mm) (opt 41.051585243776046mm) (max 41.051585243776046mm)))
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(rule "/ADC/LCLK_P length"
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(condition "A.NetName == '/ADC/LCLK_P'")
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(constraint length (min 42.10714864282774mm) (opt 42.10714864282774mm) (max 42.10714864282774mm)))
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LOADING design file
@ -1,6 +1,6 @@
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{
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"board": {
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"active_layer": 5,
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"active_layer": 0,
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"active_layer_preset": "",
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"auto_track_width": true,
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"hidden_netclasses": [
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@ -111,7 +111,7 @@
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"conflict_shadows",
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"shapes"
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],
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"visible_layers": "ffffffff_ffffffff_ffffffff_ffffffff",
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"visible_layers": "00000000_00000000_00000000_00000040",
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"zone_display_mode": 0
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},
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"git": {
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@ -714,6 +714,14 @@
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{
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"netclass": "LVDS_ADC_CLK",
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"pattern": "/ADC/ADC_CLK*"
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},
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{
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"netclass": "LVDS_ADC",
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"pattern": "/ADC/FCLK*"
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},
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{
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"netclass": "LVDS_ADC",
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"pattern": "/ADC/LCLK*"
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}
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]
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},
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@ -1,145 +1,81 @@
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#Top: dso_top Floorplan: impl_1 Part: xc7a50tcsg325-2
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#Generated by: Aleksa on: Wed Mar 26 11:01:00 2025
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#Build: Vivado v2024.1 by: xbuild on: Wed May 22 18:37:14 MDT 2024
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#Top: thunderscope Floorplan: impl_1 Part: xc7a50tcsg325-2
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#Generated by: eevengers-dev0 on: Wed Mar 26 13:38:03 2025
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#Build: Vivado v2024.2 by: xbuild on: Fri Nov 08 22:34:34 MST 2024
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#Package Version: FINAL 2014-03-07
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#Package Pin Delay Version: VERS. 2.0 2014-03-07
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IO Bank,Pin Number,Site,Site Type,Min Trace Delay (ps),Max Trace Delay (ps),Prohibit,Interface,Signal Name,Direction,DiffPair Type,DiffPair Signal,IO Standard,Drive (mA),Slew Rate,OUTPUT_IMPEDANCE,PRE_EMPHASIS,LVDS_PRE_EMPHASIS,OFFSET_CONTROL,EQUALIZATION,Pull Type,DQS_BIAS,IN_TERM,DIFF_TERM,OFFCHIP_TERM,Board Signal,Board Voltage
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15,F15,IOB_X0Y57,IO_L21N_T3_DQS_A18_15,90.795,91.708,,DDR3_54576,DDR3_dqs_n[3],INOUT,N,DDR3_dqs_p[3],DIFF_SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
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15,A17,IOB_X0Y69,IO_L15N_T2_DQS_ADV_B_15,123.839,125.084,,DDR3_54576,DDR3_dqs_n[2],INOUT,N,DDR3_dqs_p[2],DIFF_SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
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15,A9,IOB_X0Y93,IO_L3N_T0_DQS_AD1N_15,125.068,126.325,,DDR3_54576,DDR3_dqs_n[1],INOUT,N,DDR3_dqs_p[1],DIFF_SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
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15,B15,IOB_X0Y81,IO_L9N_T1_DQS_AD3N_15,118.589,119.781,,DDR3_54576,DDR3_dqs_n[0],INOUT,N,DDR3_dqs_p[0],DIFF_SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
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15,G15,IOB_X0Y58,IO_L21P_T3_DQS_15,95.207,96.163,,DDR3_54576,DDR3_dqs_p[3],INOUT,P,DDR3_dqs_n[3],DIFF_SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
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15,B16,IOB_X0Y70,IO_L15P_T2_DQS_15,123.314,124.553,,DDR3_54576,DDR3_dqs_p[2],INOUT,P,DDR3_dqs_n[2],DIFF_SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
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15,B9,IOB_X0Y94,IO_L3P_T0_DQS_AD1P_15,128.732,130.026,,DDR3_54576,DDR3_dqs_p[1],INOUT,P,DDR3_dqs_n[1],DIFF_SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
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15,C14,IOB_X0Y82,IO_L9P_T1_DQS_AD3P_15,113.213,114.351,,DDR3_54576,DDR3_dqs_p[0],INOUT,P,DDR3_dqs_n[0],DIFF_SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
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14,M17,IOB_X0Y35,IO_L7N_T1_D10_14,70.439,71.147,,DDR3_54576,DDR3_ba[2],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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14,R18,IOB_X0Y20,IO_L15P_T2_DQS_RDWR_B_14,68.577,69.266,,DDR3_54576,DDR3_ba[1],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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14,N17,IOB_X0Y31,IO_L9N_T1_DQS_D13_14,62.937,63.570,,DDR3_54576,DDR3_ba[0],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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14,T13,IOB_X0Y11,IO_L19N_T3_A09_D25_VREF_14,56.644,57.213,,DDR3_54576,DDR3_addr[12],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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14,V14,IOB_X0Y9,IO_L20N_T3_A07_D23_14,58.718,59.308,,DDR3_54576,DDR3_addr[11],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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14,N18,IOB_X0Y30,IO_L10P_T1_D14_14,64.701,65.351,,DDR3_54576,DDR3_addr[10],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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14,T17,IOB_X0Y18,IO_L16P_T2_CSI_B_14,67.255,67.930,,DDR3_54576,DDR3_addr[9],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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14,V17,IOB_X0Y13,IO_L18N_T2_A11_D27_14,72.742,73.473,,DDR3_54576,DDR3_addr[8],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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14,V16,IOB_X0Y14,IO_L18P_T2_A12_D28_14,76.242,77.008,,DDR3_54576,DDR3_addr[7],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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14,T18,IOB_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14,66.180,66.845,,DDR3_54576,DDR3_addr[6],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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14,V13,IOB_X0Y7,IO_L21N_T3_DQS_A06_D22_14,74.081,74.826,,DDR3_54576,DDR3_addr[5],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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14,V12,IOB_X0Y8,IO_L21P_T3_DQS_14,79.558,80.357,,DDR3_54576,DDR3_addr[4],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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14,V11,IOB_X0Y3,IO_L23N_T3_A02_D18_14,67.185,67.860,,DDR3_54576,DDR3_addr[3],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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14,T14,IOB_X0Y24,IO_L13P_T2_MRCC_14,54.103,54.647,,DDR3_54576,DDR3_addr[2],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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14,T15,IOB_X0Y23,IO_L13N_T2_MRCC_14,54.608,55.157,,DDR3_54576,DDR3_addr[1],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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14,T12,IOB_X0Y6,IO_L22P_T3_A05_D21_14,61.271,61.887,,DDR3_54576,DDR3_addr[0],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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15,G16,IOB_X0Y59,IO_L20N_T3_A19_15,94.726,95.678,,DDR3_54576,DDR3_dm[3],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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15,D18,IOB_X0Y65,IO_L17N_T2_A25_15,97.096,98.072,,DDR3_54576,DDR3_dm[2],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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15,B10,IOB_X0Y90,IO_L5P_T0_AD9P_15,124.999,126.256,,DDR3_54576,DDR3_dm[1],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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15,B12,IOB_X0Y86,IO_L7P_T1_AD2P_15,144.833,146.288,,DDR3_54576,DDR3_dm[0],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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14,L18,IOB_X0Y41,IO_L4N_T0_D05_14,83.486,84.325,,DDR3_54576,DDR3_cke[0],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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14,U9,IOB_X0Y2,IO_L24P_T3_A01_D17_14,94.090,95.035,,DDR3_54576,DDR3_ck_p[0],OUT,P,DDR3_ck_n[0],DIFF_SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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14,V9,IOB_X0Y1,IO_L24N_T3_A00_D16_14,97.830,98.813,,DDR3_54576,DDR3_ck_n[0],OUT,N,DDR3_ck_p[0],DIFF_SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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14,M15,IOB_X0Y37,IO_L6N_T0_D08_VREF_14,55.036,55.589,,DDR3_54576,DDR3_cs_n[0],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
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15,G14,IOB_X0Y56,IO_L22P_T3_A17_15,85.587,86.447,,DDR3_54576,DDR3_dq[31],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
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15,H18,IOB_X0Y53,IO_L23N_T3_FWE_B_15,96.244,97.212,,DDR3_54576,DDR3_dq[30],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
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15,F14,IOB_X0Y55,IO_L22N_T3_A16_15,85.983,86.847,,DDR3_54576,DDR3_dq[29],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
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15,H16,IOB_X0Y60,IO_L20P_T3_A20_15,94.014,94.959,,DDR3_54576,DDR3_dq[28],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
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15,E18,IOB_X0Y51,IO_L24N_T3_RS0_15,117.489,118.670,,DDR3_54576,DDR3_dq[27],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
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15,H17,IOB_X0Y54,IO_L23P_T3_FOE_B_15,89.808,90.710,,DDR3_54576,DDR3_dq[26],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
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15,F17,IOB_X0Y52,IO_L24P_T3_RS1_15,113.680,114.823,,DDR3_54576,DDR3_dq[25],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
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15,G17,IOB_X0Y62,IO_L19P_T3_A22_15,96.655,97.626,,DDR3_54576,DDR3_dq[24],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
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15,C17,IOB_X0Y64,IO_L18P_T2_A24_15,125.986,127.252,,DDR3_54576,DDR3_dq[23],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
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15,D15,IOB_X0Y73,IO_L13N_T2_MRCC_15,115.357,116.516,,DDR3_54576,DDR3_dq[22],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
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15,C18,IOB_X0Y63,IO_L18N_T2_A23_15,117.502,118.683,,DDR3_54576,DDR3_dq[21],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
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15,C16,IOB_X0Y68,IO_L16P_T2_A28_15,125.838,127.102,,DDR3_54576,DDR3_dq[20],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
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15,E17,IOB_X0Y66,IO_L17P_T2_A26_15,105.980,107.045,,DDR3_54576,DDR3_dq[19],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
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15,E16,IOB_X0Y72,IO_L14P_T2_SRCC_15,122.725,123.958,,DDR3_54576,DDR3_dq[18],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
|
||||
15,D16,IOB_X0Y71,IO_L14N_T2_SRCC_15,115.025,116.181,,DDR3_54576,DDR3_dq[17],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
|
||||
15,B17,IOB_X0Y67,IO_L16N_T2_A27_15,125.534,126.795,,DDR3_54576,DDR3_dq[16],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
|
||||
15,B11,IOB_X0Y91,IO_L4N_T0_15,135.822,137.187,,DDR3_54576,DDR3_dq[15],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
|
||||
15,D9,IOB_X0Y96,IO_L2P_T0_AD8P_15,154.432,155.984,,DDR3_54576,DDR3_dq[14],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
|
||||
15,C11,IOB_X0Y92,IO_L4P_T0_15,138.682,140.076,,DDR3_54576,DDR3_dq[13],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
|
||||
15,C8,IOB_X0Y97,IO_L1N_T0_AD0N_15,153.433,154.975,,DDR3_54576,DDR3_dq[12],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
|
||||
15,D11,IOB_X0Y88,IO_L6P_T0_15,127.012,128.288,,DDR3_54576,DDR3_dq[11],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
|
||||
15,D8,IOB_X0Y98,IO_L1P_T0_AD0P_15,164.869,166.526,,DDR3_54576,DDR3_dq[10],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
|
||||
15,C9,IOB_X0Y95,IO_L2N_T0_AD8N_15,152.506,154.038,,DDR3_54576,DDR3_dq[9],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
|
||||
15,A10,IOB_X0Y89,IO_L5N_T0_AD9N_15,129.097,130.394,,DDR3_54576,DDR3_dq[8],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
|
||||
15,B14,IOB_X0Y80,IO_L10P_T1_AD11P_15,115.232,116.390,,DDR3_54576,DDR3_dq[7],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
|
||||
15,D13,IOB_X0Y78,IO_L11P_T1_SRCC_15,139.431,140.833,,DDR3_54576,DDR3_dq[6],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
|
||||
15,A13,IOB_X0Y84,IO_L8P_T1_AD10P_15,146.431,147.902,,DDR3_54576,DDR3_dq[5],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
|
||||
15,A14,IOB_X0Y83,IO_L8N_T1_AD10N_15,150.892,152.408,,DDR3_54576,DDR3_dq[4],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
|
||||
15,C13,IOB_X0Y77,IO_L11N_T1_SRCC_15,144.216,145.665,,DDR3_54576,DDR3_dq[3],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
|
||||
15,A15,IOB_X0Y79,IO_L10N_T1_AD11N_15,130.198,131.506,,DDR3_54576,DDR3_dq[2],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
|
||||
15,A12,IOB_X0Y85,IO_L7N_T1_AD2N_15,147.956,149.443,,DDR3_54576,DDR3_dq[1],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
|
||||
15,D14,IOB_X0Y75,IO_L12N_T1_MRCC_15,130.430,131.741,,DDR3_54576,DDR3_dq[0],INOUT,,,SSTL135,,FAST,,,,,,,,UNTUNED_SPLIT_50,,FP_VTT_50,,
|
||||
14,K17,IOB_X0Y42,IO_L4P_T0_D04_14,87.480,88.359,,DDR3_54576,DDR3_odt[0],OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
|
||||
14,K18,IOB_X0Y43,IO_L3N_T0_DQS_EMCCLK_14,91.343,92.261,,DDR3_54576,DDR3_cas_n,OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
|
||||
14,K15,IOB_X0Y39,IO_L5N_T0_D07_14,68.532,69.221,,DDR3_54576,DDR3_ras_n,OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
|
||||
14,U11,IOB_X0Y4,IO_L23P_T3_A03_D19_14,65.496,66.154,,DDR3_54576,DDR3_reset_n,OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
|
||||
14,M16,IOB_X0Y36,IO_L7P_T1_D09_14,65.586,66.245,,DDR3_54576,DDR3_we_n,OUT,,,SSTL135,,FAST,,,,,,,,,,FP_VTT_50,,
|
||||
216,H2,OPAD_X0Y1,MGTPTXP0_216,67.731,68.412,,pcie_mgt_54576,pcie_mgt_txp[3],OUT,,,,12,,,,,,,,,,,,,
|
||||
216,F2,OPAD_X0Y3,MGTPTXP1_216,61.657,62.276,,pcie_mgt_54576,pcie_mgt_txp[2],OUT,,,,12,,,,,,,,,,,,,
|
||||
216,D2,OPAD_X0Y5,MGTPTXP2_216,57.101,57.675,,pcie_mgt_54576,pcie_mgt_txp[1],OUT,,,,12,,,,,,,,,,,,,
|
||||
216,B2,OPAD_X0Y7,MGTPTXP3_216,64.535,65.183,,pcie_mgt_54576,pcie_mgt_txp[0],OUT,,,,12,,,,,,,,,,,,,
|
||||
216,E3,IPAD_X1Y6,MGTPRXN0_216,58.321,58.907,,pcie_mgt_54576,pcie_mgt_rxn[3],IN,,,,,,,,,,,,,,,,,
|
||||
216,A3,IPAD_X1Y12,MGTPRXN1_216,68.415,69.102,,pcie_mgt_54576,pcie_mgt_rxn[2],IN,,,,,,,,,,,,,,,,,
|
||||
216,C3,IPAD_X1Y24,MGTPRXN2_216,64.693,65.343,,pcie_mgt_54576,pcie_mgt_rxn[1],IN,,,,,,,,,,,,,,,,,
|
||||
216,G3,IPAD_X1Y30,MGTPRXN3_216,75.680,76.441,,pcie_mgt_54576,pcie_mgt_rxn[0],IN,,,,,,,,,,,,,,,,,
|
||||
216,E4,IPAD_X1Y7,MGTPRXP0_216,56.509,57.076,,pcie_mgt_54576,pcie_mgt_rxp[3],IN,,,,,,,,,,,,,,,,,
|
||||
216,A4,IPAD_X1Y13,MGTPRXP1_216,66.648,67.318,,pcie_mgt_54576,pcie_mgt_rxp[2],IN,,,,,,,,,,,,,,,,,
|
||||
216,C4,IPAD_X1Y25,MGTPRXP2_216,62.679,63.308,,pcie_mgt_54576,pcie_mgt_rxp[1],IN,,,,,,,,,,,,,,,,,
|
||||
216,G4,IPAD_X1Y31,MGTPRXP3_216,73.902,74.645,,pcie_mgt_54576,pcie_mgt_rxp[0],IN,,,,,,,,,,,,,,,,,
|
||||
216,H1,OPAD_X0Y0,MGTPTXN0_216,67.597,68.276,,pcie_mgt_54576,pcie_mgt_txn[3],OUT,,,,12,,,,,,,,,,,,,
|
||||
216,F1,OPAD_X0Y2,MGTPTXN1_216,61.622,62.241,,pcie_mgt_54576,pcie_mgt_txn[2],OUT,,,,12,,,,,,,,,,,,,
|
||||
216,D1,OPAD_X0Y4,MGTPTXN2_216,58.519,59.107,,pcie_mgt_54576,pcie_mgt_txn[1],OUT,,,,12,,,,,,,,,,,,,
|
||||
216,B1,OPAD_X0Y6,MGTPTXN3_216,65.871,66.533,,pcie_mgt_54576,pcie_mgt_txn[0],OUT,,,,12,,,,,,,,,,,,,
|
||||
34,N6,IOB_X1Y33,IO_L8N_T1_34,60.767,61.378,,GPIO_39501,dc_cpl[3],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,M2,IOB_X1Y36,IO_L7P_T1_34,60.545,61.153,,GPIO_39501,dc_cpl[2],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,T2,IOB_X1Y21,IO_L14N_T2_SRCC_34,67.811,68.492,,GPIO_39501,dc_cpl[1],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,M6,IOB_X1Y34,IO_L8P_T1_34,49.945,50.447,,GPIO_39501,dc_cpl[0],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
216,B5,IPAD_X1Y17,MGTREFCLK1N_216,60.241,60.846,,pcie_54576,pcie_clk_n[0],IN,N,pcie_clk_p[0],,,,,,,,,,,,,,,
|
||||
216,B6,IPAD_X1Y16,MGTREFCLK1P_216,59.986,60.589,,pcie_54576,pcie_clk_p[0],IN,P,pcie_clk_n[0],,,,,,,,,,,,,,,
|
||||
34,L2,IOB_X1Y41,IO_L4N_T0_34,56.432,56.999,,RST.PCIE_PERSTN_54576,pcie_perstn,IN,,,LVCMOS33,,,,,,,,,,,,,,
|
||||
34,P3,IOB_X1Y25,IO_L12N_T1_MRCC_34,45.567,46.025,,,term[3],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,N2,IOB_X1Y27,IO_L11N_T1_SRCC_34,54.556,55.104,,,term[2],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,P5,IOB_X1Y11,IO_L19N_T3_VREF_34,28.656,28.944,,,term[1],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,J4,IOB_X1Y45,IO_L2N_T0_34,58.644,59.233,,,term[0],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,T7,IOB_X1Y5,IO_L22N_T3_34,50.189,50.694,,,adc_data_n[7],IN,N,adc_data_p[7],LVDS_25,,,,,,,,,,,,,,
|
||||
34,U5,IOB_X1Y9,IO_L20N_T3_34,58.073,58.656,,,adc_data_n[6],IN,N,adc_data_p[6],LVDS_25,,,,,,,,,,,,,,
|
||||
34,T3,IOB_X1Y15,IO_L17N_T2_34,47.680,48.159,,,adc_data_n[5],IN,N,adc_data_p[5],LVDS_25,,,,,,,,,,,,,,
|
||||
34,T5,IOB_X1Y7,IO_L21N_T3_DQS_34,42.458,42.884,,,adc_data_n[4],IN,N,adc_data_p[4],LVDS_25,,,,,,,,,,,,,,
|
||||
34,V7,IOB_X1Y1,IO_L24N_T3_34,65.965,66.628,,,adc_data_n[3],IN,N,adc_data_p[3],LVDS_25,,,,,,,,,,,,,,
|
||||
34,V6,IOB_X1Y3,IO_L23N_T3_34,59.607,60.206,,,adc_data_n[2],IN,N,adc_data_p[2],LVDS_25,,,,,,,,,,,,,,
|
||||
34,V2,IOB_X1Y17,IO_L16N_T2_34,73.837,74.579,,,adc_data_n[1],IN,N,adc_data_p[1],LVDS_25,,,,,,,,,,,,,,
|
||||
34,V4,IOB_X1Y13,IO_L18N_T2_34,59.810,60.411,,,adc_data_n[0],IN,N,adc_data_p[0],LVDS_25,,,,,,,,,,,,,,
|
||||
34,N1,IOB_X1Y32,IO_L9P_T1_DQS_34,66.267,66.933,,,pga_cs[3],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,R3,IOB_X1Y22,IO_L14P_T2_SRCC_34,64.924,65.576,,,pga_cs[2],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,K1,IOB_X1Y43,IO_L3N_T0_DQS_34,61.140,61.754,,,pga_cs[1],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,R6,IOB_X1Y0,IO_25_34,24.967,25.218,,,pga_cs[0],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,M1,IOB_X1Y35,IO_L7N_T1_34,61.644,62.264,,,atten[3],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,M5,IOB_X1Y37,IO_L6N_T0_VREF_34,29.605,29.903,,,atten[2],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,P1,IOB_X1Y31,IO_L9N_T1_DQS_34,67.490,68.168,,,atten[1],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,L4,IOB_X1Y40,IO_L5P_T0_34,41.862,42.282,,,atten[0],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,R7,IOB_X1Y6,IO_L22P_T3_34,48.728,49.218,,,adc_data_p[7],IN,P,adc_data_n[7],LVDS_25,,,,,,,,,,,,,,
|
||||
34,U6,IOB_X1Y10,IO_L20P_T3_34,65.998,66.661,,,adc_data_p[6],IN,P,adc_data_n[6],LVDS_25,,,,,,,,,,,,,,
|
||||
34,T4,IOB_X1Y16,IO_L17P_T2_34,56.431,56.998,,,adc_data_p[5],IN,P,adc_data_n[5],LVDS_25,,,,,,,,,,,,,,
|
||||
34,R5,IOB_X1Y8,IO_L21P_T3_DQS_34,49.535,50.033,,,adc_data_p[4],IN,P,adc_data_n[4],LVDS_25,,,,,,,,,,,,,,
|
||||
34,V8,IOB_X1Y2,IO_L24P_T3_34,63.908,64.550,,,adc_data_p[3],IN,P,adc_data_n[3],LVDS_25,,,,,,,,,,,,,,
|
||||
34,U7,IOB_X1Y4,IO_L23P_T3_34,58.503,59.091,,,adc_data_p[2],IN,P,adc_data_n[2],LVDS_25,,,,,,,,,,,,,,
|
||||
34,V3,IOB_X1Y18,IO_L16P_T2_34,78.813,79.605,,,adc_data_p[1],IN,P,adc_data_n[1],LVDS_25,,,,,,,,,,,,,,
|
||||
34,U4,IOB_X1Y14,IO_L18P_T2_34,60.807,61.418,,,adc_data_p[0],IN,P,adc_data_n[0],LVDS_25,,,,,,,,,,,,,,
|
||||
34,P6,IOB_X1Y12,IO_L19P_T3_34,42.815,43.245,,,sync,OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,L3,IOB_X1Y39,IO_L5N_T0_34,50.497,51.005,,,spi_sdio,OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,K2,IOB_X1Y44,IO_L3P_T0_DQS_34,64.117,64.761,,,spi_sclk,OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,K3,IOB_X1Y42,IO_L4P_T0_34,57.141,57.716,,,probe_comp,OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,M4,IOB_X1Y30,IO_L10P_T1_34,49.318,49.814,,,acq_en,OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,J5,IOB_X1Y46,IO_L2P_T0_34,71.434,72.152,,,adc_cs,OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,U1,IOB_X1Y19,IO_L15N_T2_DQS_34,75.322,76.079,,,adc_fclk_n,IN,N,adc_fclk_p,LVDS_25,,,,,,,,,,,,,,
|
||||
34,U2,IOB_X1Y20,IO_L15P_T2_DQS_34,77.796,78.578,,,adc_fclk_p,IN,P,adc_fclk_n,LVDS_25,,,,,,,,,,,,,,
|
||||
34,R1,IOB_X1Y23,IO_L13N_T2_MRCC_34,66.761,67.432,,,adc_lclk_n,IN,N,adc_lclk_p,LVDS_25,,,,,,,,,,,,,,
|
||||
34,R2,IOB_X1Y24,IO_L13P_T2_MRCC_34,62.355,62.982,,,adc_lclk_p,IN,P,adc_lclk_n,LVDS_25,,,,,,,,,,,,,,
|
||||
34,K6,IOB_X1Y48,IO_L1P_T0_34,70.989,71.703,,,fe_en,OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,K5,IOB_X1Y47,IO_L1N_T0_34,58.181,58.766,,,i2c_scl,OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,N4,IOB_X1Y29,IO_L10N_T1_34,58.189,58.774,,,i2c_sda,OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,U17,IOB_X0Y17,IO_L16N_T2_A15_D31_14,63.701,64.341,,,led,OUT,,,SSTL135,,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
34,N3,IOB_X1Y28,IO_L11P_T1_SRCC_34,53.012,53.545,,,osc_oe,OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
216,H2,OPAD_X0Y1,MGTPTXP0_216,67.731,68.412,,pcie_7x_mgt_25966,pcie_x4_tx_p[3],OUT,,,,12,,,,,,,,,,,,,
|
||||
216,F2,OPAD_X0Y3,MGTPTXP1_216,61.657,62.276,,pcie_7x_mgt_25966,pcie_x4_tx_p[2],OUT,,,,12,,,,,,,,,,,,,
|
||||
216,D2,OPAD_X0Y5,MGTPTXP2_216,57.101,57.675,,pcie_7x_mgt_25966,pcie_x4_tx_p[1],OUT,,,,12,,,,,,,,,,,,,
|
||||
216,B2,OPAD_X0Y7,MGTPTXP3_216,64.535,65.183,,pcie_7x_mgt_25966,pcie_x4_tx_p[0],OUT,,,,12,,,,,,,,,,,,,
|
||||
216,H1,OPAD_X0Y0,MGTPTXN0_216,67.597,68.276,,pcie_7x_mgt_25966,pcie_x4_tx_n[3],OUT,,,,12,,,,,,,,,,,,,
|
||||
216,F1,OPAD_X0Y2,MGTPTXN1_216,61.622,62.241,,pcie_7x_mgt_25966,pcie_x4_tx_n[2],OUT,,,,12,,,,,,,,,,,,,
|
||||
216,D1,OPAD_X0Y4,MGTPTXN2_216,58.519,59.107,,pcie_7x_mgt_25966,pcie_x4_tx_n[1],OUT,,,,12,,,,,,,,,,,,,
|
||||
216,B1,OPAD_X0Y6,MGTPTXN3_216,65.871,66.533,,pcie_7x_mgt_25966,pcie_x4_tx_n[0],OUT,,,,12,,,,,,,,,,,,,
|
||||
216,E4,IPAD_X1Y7,MGTPRXP0_216,56.509,57.076,,pcie_7x_mgt_25966,pcie_x4_rx_p[3],IN,,,,,,,,,,,,,,,,,
|
||||
216,A4,IPAD_X1Y13,MGTPRXP1_216,66.648,67.318,,pcie_7x_mgt_25966,pcie_x4_rx_p[2],IN,,,,,,,,,,,,,,,,,
|
||||
216,C4,IPAD_X1Y25,MGTPRXP2_216,62.679,63.308,,pcie_7x_mgt_25966,pcie_x4_rx_p[1],IN,,,,,,,,,,,,,,,,,
|
||||
216,G4,IPAD_X1Y31,MGTPRXP3_216,73.902,74.645,,pcie_7x_mgt_25966,pcie_x4_rx_p[0],IN,,,,,,,,,,,,,,,,,
|
||||
216,E3,IPAD_X1Y6,MGTPRXN0_216,58.321,58.907,,pcie_7x_mgt_25966,pcie_x4_rx_n[3],IN,,,,,,,,,,,,,,,,,
|
||||
216,A3,IPAD_X1Y12,MGTPRXN1_216,68.415,69.102,,pcie_7x_mgt_25966,pcie_x4_rx_n[2],IN,,,,,,,,,,,,,,,,,
|
||||
216,C3,IPAD_X1Y24,MGTPRXN2_216,64.693,65.343,,pcie_7x_mgt_25966,pcie_x4_rx_n[1],IN,,,,,,,,,,,,,,,,,
|
||||
216,G3,IPAD_X1Y30,MGTPRXN3_216,75.680,76.441,,pcie_7x_mgt_25966,pcie_x4_rx_n[0],IN,,,,,,,,,,,,,,,,,
|
||||
34,L2,IOB_X1Y41,IO_L4N_T0_34,56.432,56.999,,RST.sys_rst_n_25966,pcie_x4_rst_n,IN,,,LVCMOS33,,,,,,,,PULLUP,,,,,,
|
||||
15,E18,IOB_X0Y51,IO_L24N_T3_RS0_15,117.489,118.670,,,adc_data_d_n[7],IN,N,adc_data_d_p[7],LVDS_25,,,,,,,,,,,true,,,
|
||||
15,H18,IOB_X0Y53,IO_L23N_T3_FWE_B_15,96.244,97.212,,,adc_data_d_n[6],IN,N,adc_data_d_p[6],LVDS_25,,,,,,,,,,,true,,,
|
||||
15,F15,IOB_X0Y57,IO_L21N_T3_DQS_A18_15,90.795,91.708,,,adc_data_d_n[5],IN,N,adc_data_d_p[5],LVDS_25,,,,,,,,,,,true,,,
|
||||
15,G16,IOB_X0Y59,IO_L20N_T3_A19_15,94.726,95.678,,,adc_data_d_n[4],IN,N,adc_data_d_p[4],LVDS_25,,,,,,,,,,,true,,,
|
||||
15,C18,IOB_X0Y63,IO_L18N_T2_A23_15,117.502,118.683,,,adc_data_d_n[3],IN,N,adc_data_d_p[3],LVDS_25,,,,,,,,,,,true,,,
|
||||
15,B17,IOB_X0Y67,IO_L16N_T2_A27_15,125.534,126.795,,,adc_data_d_n[2],IN,N,adc_data_d_p[2],LVDS_25,,,,,,,,,,,true,,,
|
||||
15,A17,IOB_X0Y69,IO_L15N_T2_DQS_ADV_B_15,123.839,125.084,,,adc_data_d_n[1],IN,N,adc_data_d_p[1],LVDS_25,,,,,,,,,,,true,,,
|
||||
15,D16,IOB_X0Y71,IO_L14N_T2_SRCC_15,115.025,116.181,,,adc_data_d_n[0],IN,N,adc_data_d_p[0],LVDS_25,,,,,,,,,,,true,,,
|
||||
15,F17,IOB_X0Y52,IO_L24P_T3_RS1_15,113.680,114.823,,,adc_data_d_p[7],IN,P,adc_data_d_n[7],LVDS_25,,,,,,,,,,,true,,,
|
||||
15,H17,IOB_X0Y54,IO_L23P_T3_FOE_B_15,89.808,90.710,,,adc_data_d_p[6],IN,P,adc_data_d_n[6],LVDS_25,,,,,,,,,,,true,,,
|
||||
15,G15,IOB_X0Y58,IO_L21P_T3_DQS_15,95.207,96.163,,,adc_data_d_p[5],IN,P,adc_data_d_n[5],LVDS_25,,,,,,,,,,,true,,,
|
||||
15,H16,IOB_X0Y60,IO_L20P_T3_A20_15,94.014,94.959,,,adc_data_d_p[4],IN,P,adc_data_d_n[4],LVDS_25,,,,,,,,,,,true,,,
|
||||
15,C17,IOB_X0Y64,IO_L18P_T2_A24_15,125.986,127.252,,,adc_data_d_p[3],IN,P,adc_data_d_n[3],LVDS_25,,,,,,,,,,,true,,,
|
||||
15,C16,IOB_X0Y68,IO_L16P_T2_A28_15,125.838,127.102,,,adc_data_d_p[2],IN,P,adc_data_d_n[2],LVDS_25,,,,,,,,,,,true,,,
|
||||
15,B16,IOB_X0Y70,IO_L15P_T2_DQS_15,123.314,124.553,,,adc_data_d_p[1],IN,P,adc_data_d_n[1],LVDS_25,,,,,,,,,,,true,,,
|
||||
15,E16,IOB_X0Y72,IO_L14P_T2_SRCC_15,122.725,123.958,,,adc_data_d_p[0],IN,P,adc_data_d_n[0],LVDS_25,,,,,,,,,,,true,,,
|
||||
14,T13,IOB_X0Y11,IO_L19N_T3_A09_D25_VREF_14,56.644,57.213,,,fe_control_attenuation[3],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,U16,IOB_X0Y15,IO_L17N_T2_A13_D29_14,66.814,67.486,,,fe_control_attenuation[2],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,T18,IOB_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14,66.180,66.845,,,fe_control_attenuation[1],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,T15,IOB_X0Y23,IO_L13N_T2_MRCC_14,54.608,55.157,,,fe_control_attenuation[0],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,V17,IOB_X0Y13,IO_L18N_T2_A11_D27_14,72.742,73.473,,,fe_control_coupling[3],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,U17,IOB_X0Y17,IO_L16N_T2_A15_D31_14,63.701,64.341,,,fe_control_coupling[2],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,R17,IOB_X0Y21,IO_L14N_T2_SRCC_14,57.043,57.617,,,fe_control_coupling[1],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,R15,IOB_X0Y25,IO_L12N_T1_MRCC_14,58.704,59.294,,,fe_control_coupling[0],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,R13,IOB_X0Y12,IO_L19P_T3_A10_D26_14,72.503,73.231,,,fe_control_term[3],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,U15,IOB_X0Y16,IO_L17P_T2_A14_D30_14,70.152,70.857,,,fe_control_term[2],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,R18,IOB_X0Y20,IO_L15P_T2_DQS_RDWR_B_14,68.577,69.266,,,fe_control_term[1],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,T14,IOB_X0Y24,IO_L13P_T2_MRCC_14,54.103,54.647,,,fe_control_term[0],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,U14,IOB_X0Y10,IO_L20P_T3_A08_D24_14,61.902,62.524,,,main_spi_cs_n[4],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,V16,IOB_X0Y14,IO_L18P_T2_A12_D28_14,76.242,77.008,,,main_spi_cs_n[3],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,T17,IOB_X0Y18,IO_L16P_T2_CSI_B_14,67.255,67.930,,,main_spi_cs_n[2],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,R16,IOB_X0Y22,IO_L14P_T2_SRCC_14,63.779,64.420,,,main_spi_cs_n[1],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,P16,IOB_X0Y27,IO_L11N_T1_SRCC_14,55.847,56.409,,,main_spi_cs_n[0],OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,J16,IOB_X0Y45,IO_L2N_T0_D03_14,68.517,69.206,,,spiflash4x_dq[3],INOUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,J15,IOB_X0Y46,IO_L2P_T0_D02_14,81.023,81.837,,,spiflash4x_dq[2],INOUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,L17,IOB_X0Y47,IO_L1N_T0_D01_DIN_14,58.389,58.976,,,spiflash4x_dq[1],INOUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,K16,IOB_X0Y48,IO_L1P_T0_D00_MOSI_14,66.138,66.803,,,spiflash4x_dq[0],INOUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,U11,IOB_X0Y4,IO_L23P_T3_A03_D19_14,65.496,66.154,,,adc_control_acq_en,OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,U12,IOB_X0Y5,IO_L22N_T3_A04_D20_14,59.741,60.341,,,adc_control_osc_oe,OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
15,D18,IOB_X0Y65,IO_L17N_T2_A25_15,97.096,98.072,,,adc_data_fclk_n,IN,N,adc_data_fclk_p,LVDS_25,,,,,,,,,,,true,,,
|
||||
15,E17,IOB_X0Y66,IO_L17P_T2_A26_15,105.980,107.045,,,adc_data_fclk_p,IN,P,adc_data_fclk_n,LVDS_25,,,,,,,,,,,true,,,
|
||||
15,D15,IOB_X0Y73,IO_L13N_T2_MRCC_15,115.357,116.516,,,adc_data_lclk_n,IN,N,adc_data_lclk_p,LVDS_25,,,,,,,,,,,true,,,
|
||||
15,E15,IOB_X0Y74,IO_L13P_T2_MRCC_15,111.083,112.199,,,adc_data_lclk_p,IN,P,adc_data_lclk_n,LVDS_25,,,,,,,,,,,true,,,
|
||||
14,P14,IOB_X0Y26,IO_L12P_T1_MRCC_14,54.554,55.102,,,clk25,IN,,,LVCMOS33,,,,,,,,,,,,,,
|
||||
14,N16,IOB_X0Y32,IO_L9P_T1_DQS_14,56.000,56.563,,,fe_control_fe_en,OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,M15,IOB_X0Y37,IO_L6N_T0_D08_VREF_14,55.036,55.589,,,fe_probe_compensation,OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,V13,IOB_X0Y7,IO_L21N_T3_DQS_A06_D22_14,74.081,74.826,,,i2c_scl,INOUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,T12,IOB_X0Y6,IO_L22P_T3_A05_D21_14,61.271,61.887,,,i2c_sda,INOUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,M16,IOB_X0Y36,IO_L7P_T1_D09_14,65.586,66.245,,,main_spi_clk,OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,M17,IOB_X0Y35,IO_L7N_T1_D10_14,70.439,71.147,,,main_spi_mosi,OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
216,B5,IPAD_X1Y17,MGTREFCLK1N_216,60.241,60.846,,,pcie_x4_clk_n,IN,N,pcie_x4_clk_p,,,,,,,,,,,,,,,
|
||||
216,B6,IPAD_X1Y16,MGTREFCLK1P_216,59.986,60.589,,,pcie_x4_clk_p,IN,P,pcie_x4_clk_n,,,,,,,,,,,,,,,
|
||||
14,N18,IOB_X0Y30,IO_L10P_T1_D14_14,64.701,65.351,,,user_led_n,OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
14,L15,IOB_X0Y38,IO_L6P_T0_FCS_B_14,57.750,58.330,,,spiflash4x_cs_n,OUT,,,LVCMOS33,12,SLOW,,,,,,,,,,FP_VTT_50,,
|
||||
0,L9,IPAD_X0Y1,VN_0,110.355,111.464,,,,,,,,,,,,,,,,,,,,,
|
||||
0,K10,IPAD_X0Y0,VP_0,118.640,119.832,,,,,,,,,,,,,,,,,,,,,
|
||||
0,F12,,DONE_0,112.015,113.141,,,,,,,,,,,,,,,,,,,,,
|
||||
@ -158,58 +94,122 @@ IO Bank,Pin Number,Site,Site Type,Min Trace Delay (ps),Max Trace Delay (ps),Proh
|
||||
0,T9,,TDI_0,47.166,47.641,,,,,,,,,,,,,,,,,,,,,
|
||||
0,T8,,TDO_0,50.865,51.377,,,,,,,,,,,,,,,,,,,,,
|
||||
0,F13,,M2_0,118.626,119.818,,,,,,,,,,,,,,,,,,,,,
|
||||
0,E12,,CFGBVS_0,114.065,115.212,,,,,,,,,,,,,,,,,,,,GND,GND
|
||||
0,E12,,CFGBVS_0,114.065,115.212,,,,,,,,,,,,,,,,,,,,CFGBVS_0,
|
||||
0,P10,,PROGRAM_B_0,34.922,35.273,,,,,,,,,,,,,,,,,,,,,
|
||||
0,R8,,TMS_0,40.282,40.687,,,,,,,,,,,,,,,,,,,,,
|
||||
0,E10,,VCCO_0,,,,,,,,,,,,,,,,,,,,,,VCCO_0,1.80
|
||||
0,R10,,VCCO_0,,,,,,,,,,,,,,,,,,,,,,VCCO_0,1.80
|
||||
0,E10,,VCCO_0,,,,,,,,,,,,,,,,,,,,,,VCCO_0,
|
||||
0,R10,,VCCO_0,,,,,,,,,,,,,,,,,,,,,,VCCO_0,
|
||||
14,L14,IOB_X0Y49,IO_0_14,33.197,33.531,,,,,,,,,,,,,,,,,,,,,
|
||||
14,K16,IOB_X0Y48,IO_L1P_T0_D00_MOSI_14,66.138,66.803,,,,,,,,,,,,,,,,,,,,,
|
||||
14,L17,IOB_X0Y47,IO_L1N_T0_D01_DIN_14,58.389,58.976,,,,,,,,,,,,,,,,,,,,,
|
||||
14,J15,IOB_X0Y46,IO_L2P_T0_D02_14,81.023,81.837,,,,,,,,,,,,,,,,,,,,,
|
||||
14,J16,IOB_X0Y45,IO_L2N_T0_D03_14,68.517,69.206,,,,,,,,,,,,,,,,,,,,,
|
||||
14,J18,IOB_X0Y44,IO_L3P_T0_DQS_PUDC_B_14,97.992,98.977,,,,,,,,,,,,,,,,,,,,,
|
||||
14,K18,IOB_X0Y43,IO_L3N_T0_DQS_EMCCLK_14,91.343,92.261,,,,,,,,,,,,,,,,,,,,,
|
||||
14,K17,IOB_X0Y42,IO_L4P_T0_D04_14,87.480,88.359,,,,,,,,,,,,,,,,,,,,,
|
||||
14,L18,IOB_X0Y41,IO_L4N_T0_D05_14,83.486,84.325,,,,,,,,,,,,,,,,,,,,,
|
||||
14,J14,IOB_X0Y40,IO_L5P_T0_D06_14,63.773,64.414,,,,,,,,,,,,,,,,,,,,,
|
||||
14,L15,IOB_X0Y38,IO_L6P_T0_FCS_B_14,57.750,58.330,,,,,,,,,,,,,,,,,,,,,
|
||||
14,K15,IOB_X0Y39,IO_L5N_T0_D07_14,68.532,69.221,,,,,,,,,,,,,,,,,,,,,
|
||||
14,M14,IOB_X0Y34,IO_L8P_T1_D11_14,59.215,59.810,,,,,,,,,,,,,,,,,,,,,
|
||||
14,N14,IOB_X0Y33,IO_L8N_T1_D12_14,71.391,72.108,,,,,,,,,,,,,,,,,,,,,
|
||||
14,N16,IOB_X0Y32,IO_L9P_T1_DQS_14,56.000,56.563,,,,,,,,,,,,,,,,,,,,,
|
||||
14,N17,IOB_X0Y31,IO_L9N_T1_DQS_D13_14,62.937,63.570,,,,,,,,,,,,,,,,,,,,,
|
||||
14,P18,IOB_X0Y29,IO_L10N_T1_D15_14,78.110,78.895,,,,,,,,,,,,,,,,,,,,,
|
||||
14,P15,IOB_X0Y28,IO_L11P_T1_SRCC_14,49.423,49.920,,,,,,,,,,,,,,,,,,,,,
|
||||
14,P16,IOB_X0Y27,IO_L11N_T1_SRCC_14,55.847,56.409,,,,,,,,,,,,,,,,,,,,,
|
||||
14,P14,IOB_X0Y26,IO_L12P_T1_MRCC_14,54.554,55.102,,,,,,,,,,,,,,,,,,,,,
|
||||
14,R15,IOB_X0Y25,IO_L12N_T1_MRCC_14,58.704,59.294,,,,,,,,,,,,,,,,,,,,,
|
||||
14,R16,IOB_X0Y22,IO_L14P_T2_SRCC_14,63.779,64.420,,,,,,,,,,,,,,,,,,,,,
|
||||
14,R17,IOB_X0Y21,IO_L14N_T2_SRCC_14,57.043,57.617,,,,,,,,,,,,,,,,,,,,,
|
||||
14,U15,IOB_X0Y16,IO_L17P_T2_A14_D30_14,70.152,70.857,,,,,,,,,,,,,,,,,,,,,
|
||||
14,U16,IOB_X0Y15,IO_L17N_T2_A13_D29_14,66.814,67.486,,,,,,,,,,,,,,,,,,,,,
|
||||
14,R13,IOB_X0Y12,IO_L19P_T3_A10_D26_14,72.503,73.231,,,,,,,,,,,,,,,,,,,,,
|
||||
14,U14,IOB_X0Y10,IO_L20P_T3_A08_D24_14,61.902,62.524,,,,,,,,,,,,,,,,,,,,,
|
||||
14,U12,IOB_X0Y5,IO_L22N_T3_A04_D20_14,59.741,60.341,,,,,,,,,,,,,,,,,,,,,
|
||||
14,V14,IOB_X0Y9,IO_L20N_T3_A07_D23_14,58.718,59.308,,,,,,,,,,,,,,,,,,,,,
|
||||
14,V12,IOB_X0Y8,IO_L21P_T3_DQS_14,79.558,80.357,,,,,,,,,,,,,,,,,,,,,
|
||||
14,V11,IOB_X0Y3,IO_L23N_T3_A02_D18_14,67.185,67.860,,,,,,,,,,,,,,,,,,,,,
|
||||
14,U9,IOB_X0Y2,IO_L24P_T3_A01_D17_14,94.090,95.035,,,,,,,,,,,,,,,,,,,,,
|
||||
14,V9,IOB_X0Y1,IO_L24N_T3_A00_D16_14,97.830,98.813,,,,,,,,,,,,,,,,,,,,,
|
||||
14,U10,IOB_X0Y0,IO_25_14,72.593,73.322,,,,,,,,,,,,,,,,,,,,,
|
||||
14,L16,,VCCO_14,,,,,,,,,,,,,,,,,,,,,,VCCO_14,1.35
|
||||
14,P17,,VCCO_14,,,,,,,,,,,,,,,,,,,,,,VCCO_14,1.35
|
||||
14,R14,,VCCO_14,,,,,,,,,,,,,,,,,,,,,,VCCO_14,1.35
|
||||
14,T11,,VCCO_14,,,,,,,,,,,,,,,,,,,,,,VCCO_14,1.35
|
||||
14,U8,,VCCO_14,,,,,,,,,,,,,,,,,,,,,,VCCO_14,1.35
|
||||
14,U18,,VCCO_14,,,,,,,,,,,,,,,,,,,,,,VCCO_14,1.35
|
||||
14,V15,,VCCO_14,,,,,,,,,,,,,,,,,,,,,,VCCO_14,1.35
|
||||
14,L16,,VCCO_14,,,,,,,,,,,,,,,,,,,,,,VCCO_14,3.30
|
||||
14,P17,,VCCO_14,,,,,,,,,,,,,,,,,,,,,,VCCO_14,3.30
|
||||
14,R14,,VCCO_14,,,,,,,,,,,,,,,,,,,,,,VCCO_14,3.30
|
||||
14,T11,,VCCO_14,,,,,,,,,,,,,,,,,,,,,,VCCO_14,3.30
|
||||
14,U8,,VCCO_14,,,,,,,,,,,,,,,,,,,,,,VCCO_14,3.30
|
||||
14,U18,,VCCO_14,,,,,,,,,,,,,,,,,,,,,,VCCO_14,3.30
|
||||
14,V15,,VCCO_14,,,,,,,,,,,,,,,,,,,,,,VCCO_14,3.30
|
||||
15,D10,IOB_X0Y99,IO_0_15,71.275,71.991,,,,,,,,,,,,,,,,,,,,,
|
||||
15,C12,IOB_X0Y87,IO_L6N_T0_VREF_15,125.945,127.211,,,,,,,,,,,,,,,,,,,,VREF_15,0.68
|
||||
15,D8,IOB_X0Y98,IO_L1P_T0_AD0P_15,164.869,166.526,,,,,,,,,,,,,,,,,,,,,
|
||||
15,C8,IOB_X0Y97,IO_L1N_T0_AD0N_15,153.433,154.975,,,,,,,,,,,,,,,,,,,,,
|
||||
15,D9,IOB_X0Y96,IO_L2P_T0_AD8P_15,154.432,155.984,,,,,,,,,,,,,,,,,,,,,
|
||||
15,C9,IOB_X0Y95,IO_L2N_T0_AD8N_15,152.506,154.038,,,,,,,,,,,,,,,,,,,,,
|
||||
15,B9,IOB_X0Y94,IO_L3P_T0_DQS_AD1P_15,128.732,130.026,,,,,,,,,,,,,,,,,,,,,
|
||||
15,A9,IOB_X0Y93,IO_L3N_T0_DQS_AD1N_15,125.068,126.325,,,,,,,,,,,,,,,,,,,,,
|
||||
15,C11,IOB_X0Y92,IO_L4P_T0_15,138.682,140.076,,,,,,,,,,,,,,,,,,,,,
|
||||
15,B11,IOB_X0Y91,IO_L4N_T0_15,135.822,137.187,,,,,,,,,,,,,,,,,,,,,
|
||||
15,B10,IOB_X0Y90,IO_L5P_T0_AD9P_15,124.999,126.256,,,,,,,,,,,,,,,,,,,,,
|
||||
15,A10,IOB_X0Y89,IO_L5N_T0_AD9N_15,129.097,130.394,,,,,,,,,,,,,,,,,,,,,
|
||||
15,D11,IOB_X0Y88,IO_L6P_T0_15,127.012,128.288,,,,,,,,,,,,,,,,,,,,,
|
||||
15,C12,IOB_X0Y87,IO_L6N_T0_VREF_15,125.945,127.211,,,,,,,,,,,,,,,,,,,,,
|
||||
15,B12,IOB_X0Y86,IO_L7P_T1_AD2P_15,144.833,146.288,,,,,,,,,,,,,,,,,,,,,
|
||||
15,A12,IOB_X0Y85,IO_L7N_T1_AD2N_15,147.956,149.443,,,,,,,,,,,,,,,,,,,,,
|
||||
15,A13,IOB_X0Y84,IO_L8P_T1_AD10P_15,146.431,147.902,,,,,,,,,,,,,,,,,,,,,
|
||||
15,A14,IOB_X0Y83,IO_L8N_T1_AD10N_15,150.892,152.408,,,,,,,,,,,,,,,,,,,,,
|
||||
15,C14,IOB_X0Y82,IO_L9P_T1_DQS_AD3P_15,113.213,114.351,,,,,,,,,,,,,,,,,,,,,
|
||||
15,B15,IOB_X0Y81,IO_L9N_T1_DQS_AD3N_15,118.589,119.781,,,,,,,,,,,,,,,,,,,,,
|
||||
15,B14,IOB_X0Y80,IO_L10P_T1_AD11P_15,115.232,116.390,,,,,,,,,,,,,,,,,,,,,
|
||||
15,A15,IOB_X0Y79,IO_L10N_T1_AD11N_15,130.198,131.506,,,,,,,,,,,,,,,,,,,,,
|
||||
15,D13,IOB_X0Y78,IO_L11P_T1_SRCC_15,139.431,140.833,,,,,,,,,,,,,,,,,,,,,
|
||||
15,C13,IOB_X0Y77,IO_L11N_T1_SRCC_15,144.216,145.665,,,,,,,,,,,,,,,,,,,,,
|
||||
15,E13,IOB_X0Y76,IO_L12P_T1_MRCC_15,124.589,125.841,,,,,,,,,,,,,,,,,,,,,
|
||||
15,E15,IOB_X0Y74,IO_L13P_T2_MRCC_15,111.083,112.199,,,,,,,,,,,,,,,,,,,,,
|
||||
15,F18,IOB_X0Y61,IO_L19N_T3_A21_VREF_15,96.334,97.302,,,,,,,,,,,,,,,,,,,,VREF_15,0.68
|
||||
15,D14,IOB_X0Y75,IO_L12N_T1_MRCC_15,130.430,131.741,,,,,,,,,,,,,,,,,,,,,
|
||||
15,G17,IOB_X0Y62,IO_L19P_T3_A22_15,96.655,97.626,,,,,,,,,,,,,,,,,,,,,
|
||||
15,F18,IOB_X0Y61,IO_L19N_T3_A21_VREF_15,96.334,97.302,,,,,,,,,,,,,,,,,,,,,
|
||||
15,G14,IOB_X0Y56,IO_L22P_T3_A17_15,85.587,86.447,,,,,,,,,,,,,,,,,,,,,
|
||||
15,F14,IOB_X0Y55,IO_L22N_T3_A16_15,85.983,86.847,,,,,,,,,,,,,,,,,,,,,
|
||||
15,H14,IOB_X0Y50,IO_25_15,53.356,53.892,,,,,,,,,,,,,,,,,,,,,
|
||||
15,A16,,VCCO_15,,,,,,,,,,,,,,,,,,,,,,VCCO_15,1.35
|
||||
15,B13,,VCCO_15,,,,,,,,,,,,,,,,,,,,,,VCCO_15,1.35
|
||||
15,C10,,VCCO_15,,,,,,,,,,,,,,,,,,,,,,VCCO_15,1.35
|
||||
15,D17,,VCCO_15,,,,,,,,,,,,,,,,,,,,,,VCCO_15,1.35
|
||||
15,E14,,VCCO_15,,,,,,,,,,,,,,,,,,,,,,VCCO_15,1.35
|
||||
15,G18,,VCCO_15,,,,,,,,,,,,,,,,,,,,,,VCCO_15,1.35
|
||||
15,H15,,VCCO_15,,,,,,,,,,,,,,,,,,,,,,VCCO_15,1.35
|
||||
15,A16,,VCCO_15,,,,,,,,,,,,,,,,,,,,,,VCCO_15,2.50
|
||||
15,B13,,VCCO_15,,,,,,,,,,,,,,,,,,,,,,VCCO_15,2.50
|
||||
15,C10,,VCCO_15,,,,,,,,,,,,,,,,,,,,,,VCCO_15,2.50
|
||||
15,D17,,VCCO_15,,,,,,,,,,,,,,,,,,,,,,VCCO_15,2.50
|
||||
15,E14,,VCCO_15,,,,,,,,,,,,,,,,,,,,,,VCCO_15,2.50
|
||||
15,G18,,VCCO_15,,,,,,,,,,,,,,,,,,,,,,VCCO_15,2.50
|
||||
15,H15,,VCCO_15,,,,,,,,,,,,,,,,,,,,,,VCCO_15,2.50
|
||||
34,J6,IOB_X1Y49,IO_0_34,43.682,44.121,,,,,,,,,,,,,,,,,,,,,
|
||||
34,K6,IOB_X1Y48,IO_L1P_T0_34,70.989,71.703,,,,,,,,,,,,,,,,,,,,,
|
||||
34,K5,IOB_X1Y47,IO_L1N_T0_34,58.181,58.766,,,,,,,,,,,,,,,,,,,,,
|
||||
34,J5,IOB_X1Y46,IO_L2P_T0_34,71.434,72.152,,,,,,,,,,,,,,,,,,,,,
|
||||
34,J4,IOB_X1Y45,IO_L2N_T0_34,58.644,59.233,,,,,,,,,,,,,,,,,,,,,
|
||||
34,K2,IOB_X1Y44,IO_L3P_T0_DQS_34,64.117,64.761,,,,,,,,,,,,,,,,,,,,,
|
||||
34,K1,IOB_X1Y43,IO_L3N_T0_DQS_34,61.140,61.754,,,,,,,,,,,,,,,,,,,,,
|
||||
34,K3,IOB_X1Y42,IO_L4P_T0_34,57.141,57.716,,,,,,,,,,,,,,,,,,,,,
|
||||
34,L4,IOB_X1Y40,IO_L5P_T0_34,41.862,42.282,,,,,,,,,,,,,,,,,,,,,
|
||||
34,L3,IOB_X1Y39,IO_L5N_T0_34,50.497,51.005,,,,,,,,,,,,,,,,,,,,,
|
||||
34,L5,IOB_X1Y38,IO_L6P_T0_34,42.404,42.831,,,,,,,,,,,,,,,,,,,,,
|
||||
34,M5,IOB_X1Y37,IO_L6N_T0_VREF_34,29.605,29.903,,,,,,,,,,,,,,,,,,,,,
|
||||
34,M2,IOB_X1Y36,IO_L7P_T1_34,60.545,61.153,,,,,,,,,,,,,,,,,,,,,
|
||||
34,M1,IOB_X1Y35,IO_L7N_T1_34,61.644,62.264,,,,,,,,,,,,,,,,,,,,,
|
||||
34,M6,IOB_X1Y34,IO_L8P_T1_34,49.945,50.447,,,,,,,,,,,,,,,,,,,,,
|
||||
34,N6,IOB_X1Y33,IO_L8N_T1_34,60.767,61.378,,,,,,,,,,,,,,,,,,,,,
|
||||
34,N1,IOB_X1Y32,IO_L9P_T1_DQS_34,66.267,66.933,,,,,,,,,,,,,,,,,,,,,
|
||||
34,P1,IOB_X1Y31,IO_L9N_T1_DQS_34,67.490,68.168,,,,,,,,,,,,,,,,,,,,,
|
||||
34,M4,IOB_X1Y30,IO_L10P_T1_34,49.318,49.814,,,,,,,,,,,,,,,,,,,,,
|
||||
34,N4,IOB_X1Y29,IO_L10N_T1_34,58.189,58.774,,,,,,,,,,,,,,,,,,,,,
|
||||
34,N3,IOB_X1Y28,IO_L11P_T1_SRCC_34,53.012,53.545,,,,,,,,,,,,,,,,,,,,,
|
||||
34,N2,IOB_X1Y27,IO_L11N_T1_SRCC_34,54.556,55.104,,,,,,,,,,,,,,,,,,,,,
|
||||
34,P4,IOB_X1Y26,IO_L12P_T1_MRCC_34,43.456,43.893,,,,,,,,,,,,,,,,,,,,,
|
||||
34,P3,IOB_X1Y25,IO_L12N_T1_MRCC_34,45.567,46.025,,,,,,,,,,,,,,,,,,,,,
|
||||
34,R2,IOB_X1Y24,IO_L13P_T2_MRCC_34,62.355,62.982,,,,,,,,,,,,,,,,,,,,,
|
||||
34,R1,IOB_X1Y23,IO_L13N_T2_MRCC_34,66.761,67.432,,,,,,,,,,,,,,,,,,,,,
|
||||
34,R3,IOB_X1Y22,IO_L14P_T2_SRCC_34,64.924,65.576,,,,,,,,,,,,,,,,,,,,,
|
||||
34,T2,IOB_X1Y21,IO_L14N_T2_SRCC_34,67.811,68.492,,,,,,,,,,,,,,,,,,,,,
|
||||
34,U2,IOB_X1Y20,IO_L15P_T2_DQS_34,77.796,78.578,,,,,,,,,,,,,,,,,,,,,
|
||||
34,U1,IOB_X1Y19,IO_L15N_T2_DQS_34,75.322,76.079,,,,,,,,,,,,,,,,,,,,,
|
||||
34,V3,IOB_X1Y18,IO_L16P_T2_34,78.813,79.605,,,,,,,,,,,,,,,,,,,,,
|
||||
34,V2,IOB_X1Y17,IO_L16N_T2_34,73.837,74.579,,,,,,,,,,,,,,,,,,,,,
|
||||
34,T4,IOB_X1Y16,IO_L17P_T2_34,56.431,56.998,,,,,,,,,,,,,,,,,,,,,
|
||||
34,T3,IOB_X1Y15,IO_L17N_T2_34,47.680,48.159,,,,,,,,,,,,,,,,,,,,,
|
||||
34,U4,IOB_X1Y14,IO_L18P_T2_34,60.807,61.418,,,,,,,,,,,,,,,,,,,,,
|
||||
34,V4,IOB_X1Y13,IO_L18N_T2_34,59.810,60.411,,,,,,,,,,,,,,,,,,,,,
|
||||
34,P6,IOB_X1Y12,IO_L19P_T3_34,42.815,43.245,,,,,,,,,,,,,,,,,,,,,
|
||||
34,P5,IOB_X1Y11,IO_L19N_T3_VREF_34,28.656,28.944,,,,,,,,,,,,,,,,,,,,,
|
||||
34,U6,IOB_X1Y10,IO_L20P_T3_34,65.998,66.661,,,,,,,,,,,,,,,,,,,,,
|
||||
34,U5,IOB_X1Y9,IO_L20N_T3_34,58.073,58.656,,,,,,,,,,,,,,,,,,,,,
|
||||
34,R5,IOB_X1Y8,IO_L21P_T3_DQS_34,49.535,50.033,,,,,,,,,,,,,,,,,,,,,
|
||||
34,T5,IOB_X1Y7,IO_L21N_T3_DQS_34,42.458,42.884,,,,,,,,,,,,,,,,,,,,,
|
||||
34,R7,IOB_X1Y6,IO_L22P_T3_34,48.728,49.218,,,,,,,,,,,,,,,,,,,,,
|
||||
34,T7,IOB_X1Y5,IO_L22N_T3_34,50.189,50.694,,,,,,,,,,,,,,,,,,,,,
|
||||
34,U7,IOB_X1Y4,IO_L23P_T3_34,58.503,59.091,,,,,,,,,,,,,,,,,,,,,
|
||||
34,V6,IOB_X1Y3,IO_L23N_T3_34,59.607,60.206,,,,,,,,,,,,,,,,,,,,,
|
||||
34,V8,IOB_X1Y2,IO_L24P_T3_34,63.908,64.550,,,,,,,,,,,,,,,,,,,,,
|
||||
34,V7,IOB_X1Y1,IO_L24N_T3_34,65.965,66.628,,,,,,,,,,,,,,,,,,,,,
|
||||
34,R6,IOB_X1Y0,IO_25_34,24.967,25.218,,,,,,,,,,,,,,,,,,,,,
|
||||
34,L6,,VCCO_34,,,,,,,,,,,,,,,,,,,,,,VCCO_34,3.30
|
||||
34,M3,,VCCO_34,,,,,,,,,,,,,,,,,,,,,,VCCO_34,3.30
|
||||
34,P7,,VCCO_34,,,,,,,,,,,,,,,,,,,,,,VCCO_34,3.30
|
||||
|
||||
|
@ -7,16 +7,22 @@ from kipy.util.units import to_mm
|
||||
|
||||
er_per_layer = [2.78,-1,3.66,3.66,-1,2.78]
|
||||
via_prop_delay_ps = 23.09 # sqrt(Cvia * Lvia)
|
||||
board_height_mm = 1.6
|
||||
mm_per_m = 1000.0
|
||||
s_per_ps = 1e-12
|
||||
c = 2.998e8
|
||||
|
||||
def main():
|
||||
board_file = "Thunderscope_Rev5.kicad_pcb"
|
||||
rules_file = "Thunderscope_Rev5.kicad_dru"
|
||||
vivado_io_csv_file = "impl_1.csv"
|
||||
|
||||
refresh = False
|
||||
time_modified_old = 0
|
||||
time_modified_new = 0
|
||||
|
||||
equiv_len_max = 0
|
||||
|
||||
try:
|
||||
kicad = KiCad()
|
||||
except BaseException as e:
|
||||
@ -24,19 +30,27 @@ def main():
|
||||
exit()
|
||||
|
||||
pad_delay_dict = get_pad_delays(vivado_io_csv_file)
|
||||
calc_net_delays(kicad,"LVDS_ADC",pad_delay_dict)
|
||||
|
||||
""" if (os.path.isfile(board_file)):
|
||||
try:
|
||||
while True:
|
||||
time_modified_new = os.path.getmtime(board_file)
|
||||
if (time_modified_new > time_modified_old):
|
||||
calc_delays(kicad)
|
||||
time_modified_old = time_modified_new
|
||||
time.sleep(1)
|
||||
|
||||
except KeyboardInterrupt:
|
||||
pass """
|
||||
|
||||
if (refresh == False):
|
||||
equiv_len_max,per_net_delay_dict = calc_net_delays(kicad,"LVDS_ADC",pad_delay_dict)
|
||||
print ("Max Equiv Length: " + str(equiv_len_max))
|
||||
user_write_prompt = input("Write Rules File (y/n): ")
|
||||
if (user_write_prompt == "y"):
|
||||
write_rule_file(per_net_delay_dict,rules_file)
|
||||
else:
|
||||
if (os.path.isfile(board_file)):
|
||||
try:
|
||||
while True:
|
||||
time_modified_new = os.path.getmtime(board_file)
|
||||
if (time_modified_new > time_modified_old):
|
||||
equiv_len_max_new,per_net_delay_dict = calc_net_delays(kicad,"LVDS_ADC",pad_delay_dict)
|
||||
if (equiv_len_max_new <= equiv_len_max_old):
|
||||
write_rule_file(per_net_delay_dict,rules_file)
|
||||
time_modified_old = time_modified_new
|
||||
time.sleep(1)
|
||||
|
||||
except KeyboardInterrupt:
|
||||
pass
|
||||
|
||||
|
||||
def get_pad_delays(vivado_io_csv_file):
|
||||
@ -130,8 +144,8 @@ def calc_net_delays(kicad,netclass,pad_delay_dict):
|
||||
if (pad.net == nets[net_index]):
|
||||
if (pad.number in pad_delay_dict.keys()):
|
||||
per_net_stats[net_index][num_cu_layers + 1] = pad_delay_dict[pad.number]
|
||||
print (pad.number)
|
||||
print (pad_delay_dict[pad.number])
|
||||
#print (pad.number)
|
||||
#print (pad_delay_dict[pad.number])
|
||||
|
||||
# Step 7
|
||||
# Calc the ps_per_mm scaling factor
|
||||
@ -150,18 +164,77 @@ def calc_net_delays(kicad,netclass,pad_delay_dict):
|
||||
|
||||
for net_index in range (num_nets):
|
||||
|
||||
per_net_length_kicad = 0
|
||||
per_net_length_equiv = 0
|
||||
per_net_delay = 0
|
||||
|
||||
# Traces
|
||||
for layer_index in range (num_cu_layers):
|
||||
per_net_length_kicad += per_net_stats[net_index][layer_index]
|
||||
per_net_delay += per_net_stats[net_index][layer_index] * ps_per_mm_by_layer[layer_index]
|
||||
|
||||
# Vias
|
||||
per_net_length_kicad += per_net_stats[net_index][num_cu_layers] * board_height_mm
|
||||
per_net_delay += per_net_stats[net_index][num_cu_layers] * via_prop_delay_ps
|
||||
|
||||
# Pad Delay
|
||||
per_net_delay += per_net_stats[net_index][num_cu_layers + 1]
|
||||
|
||||
# Convert Pad Delay to Length for Equiv
|
||||
per_net_length_equiv = per_net_stats[net_index][num_cu_layers + 1] / ps_per_mm_by_layer[0]
|
||||
per_net_length_equiv += per_net_length_kicad
|
||||
|
||||
per_net_delay_dict[nets[net_index].name] = per_net_delay
|
||||
# Dictionary
|
||||
per_net_delay_dict[nets[net_index].name] = [per_net_length_kicad,per_net_delay,per_net_length_equiv]
|
||||
|
||||
# Step 9
|
||||
# Find net with greatest delay, then make use equivalent length deltas to set Length Rules
|
||||
# For each net: Length Rule = Kicad Length + (Equiv Length of max delay net - Equiv Length)
|
||||
|
||||
equiv_len_max = 0
|
||||
|
||||
for x in per_net_delay_dict.values():
|
||||
if x[2] > equiv_len_max:
|
||||
equiv_len_max = x[2]
|
||||
|
||||
for x in per_net_delay_dict.values():
|
||||
x.append(x[0] + equiv_len_max - x[2])
|
||||
|
||||
print ("-"*113)
|
||||
print ("| Net\t\t| Kicad Length (mm)\t| Total Delay (ps)\t| Equiv. Length (mm)\t| Rule Length (mm)\t|")
|
||||
print ("-"*113)
|
||||
for x, y in per_net_delay_dict.items():
|
||||
print(x, y)
|
||||
print("| " + x + "\t| " + str(y[0]) + "\t| " + str(y[1]) + "\t| " + str(y[2]) + "\t| " + str(y[3]) + "\t|" )
|
||||
print ("-"*113)
|
||||
|
||||
return equiv_len_max,per_net_delay_dict
|
||||
|
||||
|
||||
def write_rule_file(per_net_delay_dict,rules_file):
|
||||
|
||||
with open(rules_file) as f:
|
||||
lines = f.readlines()
|
||||
|
||||
line_num_start = -1
|
||||
|
||||
for x in range(len(lines)):
|
||||
if lines[x].startswith("# DELAY TUNER RULES"):
|
||||
line_num_start = x
|
||||
|
||||
if (line_num_start != -1):
|
||||
with open(rules_file, "w") as f:
|
||||
for x in range(len(lines)):
|
||||
f.write(lines[x])
|
||||
if (x == line_num_start):
|
||||
break
|
||||
f.write("\n")
|
||||
for x,y in per_net_delay_dict.items():
|
||||
f.write('(rule "' + x + ' length"\n')
|
||||
f.write('\t(condition "A.NetName == \'' + x + '\'")\n')
|
||||
f.write("\t(constraint length ")
|
||||
f.write("(min " + str(y[3]) + "mm) ")
|
||||
f.write("(opt " + str(y[3]) + "mm) ")
|
||||
f.write("(max " + str(y[3]) + "mm)))\n")
|
||||
|
||||
if __name__ == '__main__':
|
||||
main()
|
||||
Loading…
Reference in New Issue
Block a user