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Decreased Frequency of Glitching
This commit is contained in:
Aleksa
parent
39c95ff057
commit
2c1c088d07
Firmware/Artix7_PCIe/dso_top
dso_top.bindesign_1_mig_7series_0_0_sim_netlist.vdesign_1_mig_7series_0_0_sim_netlist.vhdldso_top.xpr
dso_top.hw/hw_1
dso_top.ip_user_files
bd/design_1
ip
design_1_auto_cc_0
design_1_auto_us_df_0
design_1_auto_us_df_1
design_1_axi_datamover_0_0/sim
design_1_axi_fifo_mm_s_0_0/sim
design_1_axi_gpio_0_1
design_1_axi_gpio_1_0
design_1_clk_wiz_0_0
design_1_m00_data_fifo_0
design_1_mig_7series_0_0
design_1_mig_7series_0_0/user_design/rtl
axi
mig_7series_v4_2_axi_ctrl_addr_decode.vmig_7series_v4_2_axi_ctrl_read.vmig_7series_v4_2_axi_ctrl_reg.vmig_7series_v4_2_axi_ctrl_reg_bank.vmig_7series_v4_2_axi_ctrl_top.vmig_7series_v4_2_axi_ctrl_write.vmig_7series_v4_2_axi_mc.vmig_7series_v4_2_axi_mc_ar_channel.vmig_7series_v4_2_axi_mc_aw_channel.vmig_7series_v4_2_axi_mc_b_channel.vmig_7series_v4_2_axi_mc_cmd_arbiter.vmig_7series_v4_2_axi_mc_cmd_fsm.vmig_7series_v4_2_axi_mc_cmd_translator.vmig_7series_v4_2_axi_mc_fifo.vmig_7series_v4_2_axi_mc_incr_cmd.vmig_7series_v4_2_axi_mc_r_channel.vmig_7series_v4_2_axi_mc_simple_fifo.vmig_7series_v4_2_axi_mc_w_channel.vmig_7series_v4_2_axi_mc_wr_cmd_fsm.vmig_7series_v4_2_axi_mc_wrap_cmd.vmig_7series_v4_2_ddr_a_upsizer.vmig_7series_v4_2_ddr_axi_register_slice.vmig_7series_v4_2_ddr_axi_upsizer.vmig_7series_v4_2_ddr_axic_register_slice.vmig_7series_v4_2_ddr_carry_and.vmig_7series_v4_2_ddr_carry_latch_and.vmig_7series_v4_2_ddr_carry_latch_or.vmig_7series_v4_2_ddr_carry_or.vmig_7series_v4_2_ddr_command_fifo.vmig_7series_v4_2_ddr_comparator.vmig_7series_v4_2_ddr_comparator_sel.vmig_7series_v4_2_ddr_comparator_sel_static.vmig_7series_v4_2_ddr_r_upsizer.vmig_7series_v4_2_ddr_w_upsizer.v
clocking
mig_7series_v4_2_clk_ibuf.vmig_7series_v4_2_infrastructure.vmig_7series_v4_2_iodelay_ctrl.vmig_7series_v4_2_tempmon.v
controller
mig_7series_v4_2_arb_mux.vmig_7series_v4_2_arb_row_col.vmig_7series_v4_2_arb_select.vmig_7series_v4_2_bank_cntrl.vmig_7series_v4_2_bank_common.vmig_7series_v4_2_bank_compare.vmig_7series_v4_2_bank_mach.vmig_7series_v4_2_bank_queue.vmig_7series_v4_2_bank_state.vmig_7series_v4_2_col_mach.vmig_7series_v4_2_mc.vmig_7series_v4_2_rank_cntrl.vmig_7series_v4_2_rank_common.vmig_7series_v4_2_rank_mach.vmig_7series_v4_2_round_robin_arb.v
design_1_mig_7series_0_0.vdesign_1_mig_7series_0_0_mig_sim.vecc
mig_7series_v4_2_ecc_buf.vmig_7series_v4_2_ecc_dec_fix.vmig_7series_v4_2_ecc_gen.vmig_7series_v4_2_ecc_merge_enc.vmig_7series_v4_2_fi_xor.v
ip_top
phy
mig_7series_v4_2_ddr_byte_group_io.vmig_7series_v4_2_ddr_byte_lane.vmig_7series_v4_2_ddr_calib_top.vmig_7series_v4_2_ddr_if_post_fifo.vmig_7series_v4_2_ddr_mc_phy.vmig_7series_v4_2_ddr_mc_phy_wrapper.vmig_7series_v4_2_ddr_of_pre_fifo.vmig_7series_v4_2_ddr_phy_4lanes.vmig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.vmig_7series_v4_2_ddr_phy_dqs_found_cal.vmig_7series_v4_2_ddr_phy_dqs_found_cal_hr.vmig_7series_v4_2_ddr_phy_init.vmig_7series_v4_2_ddr_phy_ocd_cntlr.vmig_7series_v4_2_ddr_phy_ocd_data.vmig_7series_v4_2_ddr_phy_ocd_edge.vmig_7series_v4_2_ddr_phy_ocd_lim.vmig_7series_v4_2_ddr_phy_ocd_mux.vmig_7series_v4_2_ddr_phy_ocd_po_cntlr.vmig_7series_v4_2_ddr_phy_ocd_samp.vmig_7series_v4_2_ddr_phy_oclkdelay_cal.vmig_7series_v4_2_ddr_phy_prbs_rdlvl.vmig_7series_v4_2_ddr_phy_rdlvl.vmig_7series_v4_2_ddr_phy_tempmon.vmig_7series_v4_2_ddr_phy_top.vmig_7series_v4_2_ddr_phy_wrcal.vmig_7series_v4_2_ddr_phy_wrlvl.vmig_7series_v4_2_ddr_phy_wrlvl_off_delay.vmig_7series_v4_2_ddr_prbs_gen.vmig_7series_v4_2_ddr_skip_calib_tap.vmig_7series_v4_2_poc_cc.vmig_7series_v4_2_poc_edge_store.vmig_7series_v4_2_poc_meta.vmig_7series_v4_2_poc_pd.vmig_7series_v4_2_poc_tap_base.vmig_7series_v4_2_poc_top.v
ui
design_1_smartconnect_0_0
bd_0
bd_48ac.bd
design_1_smartconnect_0_0_sim_netlist.vdesign_1_smartconnect_0_0_sim_netlist.vhdlip
ip_0/sim
ip_1/sim
ip_10/sim
ip_11/sim
ip_12/sim
ip_13/sim
ip_14/sim
ip_15/sim
ip_16/sim
ip_17/sim
ip_18/sim
ip_19/sim
ip_2/sim
ip_20/sim
ip_21/sim
ip_22/sim
ip_23/sim
ip_24/sim
ip_25/sim
ip_26/sim
ip_27/sim
ip_28/sim
ip_29/sim
ip_3/sim
ip_30/sim
ip_31/sim
ip_32/sim
ip_33/sim
ip_34/sim
ip_35/sim
ip_36/sim
ip_37/sim
ip_38/sim
ip_39/sim
ip_4/sim
ip_40/sim
ip_41/sim
ip_42/sim
ip_43/sim
ip_44/sim
ip_45/sim
ip_46/sim
ip_5/sim
ip_6/sim
ip_7/sim
ip_8/sim
ip_9/sim
sim
sim
design_1_util_ds_buf_0_0
design_1_util_vector_logic_0_0/sim
design_1_xbar_0/sim
design_1_xdma_0_0
ip_0
sim
source
design_1_xdma_0_0_pcie2_ip_axi_basic_rx.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_rx_null_gen.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_rx_pipeline.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_top.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_tx.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_tx_pipeline.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_tx_thrtl_ctl.vdesign_1_xdma_0_0_pcie2_ip_core_top.vdesign_1_xdma_0_0_pcie2_ip_gt_common.vdesign_1_xdma_0_0_pcie2_ip_gt_rx_valid_filter_7x.vdesign_1_xdma_0_0_pcie2_ip_gt_top.vdesign_1_xdma_0_0_pcie2_ip_gt_wrapper.vdesign_1_xdma_0_0_pcie2_ip_gtp_cpllpd_ovrd.vdesign_1_xdma_0_0_pcie2_ip_gtp_pipe_drp.vdesign_1_xdma_0_0_pcie2_ip_gtp_pipe_rate.vdesign_1_xdma_0_0_pcie2_ip_gtp_pipe_reset.vdesign_1_xdma_0_0_pcie2_ip_gtx_cpllpd_ovrd.vdesign_1_xdma_0_0_pcie2_ip_pcie2_top.vdesign_1_xdma_0_0_pcie2_ip_pcie_7x.vdesign_1_xdma_0_0_pcie2_ip_pcie_bram_7x.vdesign_1_xdma_0_0_pcie2_ip_pcie_bram_top_7x.vdesign_1_xdma_0_0_pcie2_ip_pcie_brams_7x.vdesign_1_xdma_0_0_pcie2_ip_pcie_pipe_lane.vdesign_1_xdma_0_0_pcie2_ip_pcie_pipe_misc.vdesign_1_xdma_0_0_pcie2_ip_pcie_pipe_pipeline.vdesign_1_xdma_0_0_pcie2_ip_pcie_top.vdesign_1_xdma_0_0_pcie2_ip_pipe_clock.vdesign_1_xdma_0_0_pcie2_ip_pipe_drp.vdesign_1_xdma_0_0_pcie2_ip_pipe_eq.vdesign_1_xdma_0_0_pcie2_ip_pipe_rate.vdesign_1_xdma_0_0_pcie2_ip_pipe_reset.vdesign_1_xdma_0_0_pcie2_ip_pipe_sync.vdesign_1_xdma_0_0_pcie2_ip_pipe_user.vdesign_1_xdma_0_0_pcie2_ip_pipe_wrapper.vdesign_1_xdma_0_0_pcie2_ip_qpll_drp.vdesign_1_xdma_0_0_pcie2_ip_qpll_reset.vdesign_1_xdma_0_0_pcie2_ip_qpll_wrapper.vdesign_1_xdma_0_0_pcie2_ip_rxeq_scan.v
ip_1/sim
ip_2/sim
ip_3/sim
ip_4/sim
sim
xdma_v4_1/hdl/verilog
design_1_xdma_0_0_axi_stream_intf.svdesign_1_xdma_0_0_cfg_sideband.svdesign_1_xdma_0_0_core_top.svdesign_1_xdma_0_0_dma_bram_wrap.svdesign_1_xdma_0_0_dma_bram_wrap_1024.svdesign_1_xdma_0_0_dma_bram_wrap_2048.svdesign_1_xdma_0_0_dma_cpl.svdesign_1_xdma_0_0_dma_req.svdesign_1_xdma_0_0_pcie2_to_pcie3_wrapper.svdesign_1_xdma_0_0_rx_demux.svdesign_1_xdma_0_0_rx_destraddler.svdesign_1_xdma_0_0_tgt_cpl.svdesign_1_xdma_0_0_tgt_req.svdesign_1_xdma_0_0_tx_mux.sv
design_1_xlconstant_0_0/sim
design_1_xlconstant_0_2/sim
design_1_xlconstant_0_3/sim
sim
ip/fifo_generator_0
mem_init_files
axi_data_fifo.haxi_dwidth_converter.hbd_48ac_one_0.hdesign_1_auto_cc_0.hdesign_1_auto_us_df_0.hdesign_1_auto_us_df_0_sc.hdesign_1_auto_us_df_1.hdesign_1_auto_us_df_1_sc.hdesign_1_m00_data_fifo_0.hdesign_1_m00_data_fifo_0_sc.hdesign_1_smartconnect_0_0.hdesign_1_smartconnect_0_0_sc.hdesign_1_xbar_0.hmig_a.prjsc_xtlm_design_1_smartconnect_0_0.memsmartconnect.cxxsmartconnect.hsmartconnect_xtlm.cxxsmartconnect_xtlm.hsmartconnect_xtlm_impl.h
sim_scripts
design_1
README.txt
activehdl
README.txtaxi_clock_converter.haxi_crossbar.haxi_data_fifo.haxi_dwidth_converter.hbd_48ac_one_0.hcompile.dodesign_1.shdesign_1.udodesign_1_auto_cc_0.hdesign_1_auto_cc_0_sc.hdesign_1_auto_us_df_0.hdesign_1_auto_us_df_0_sc.hdesign_1_auto_us_df_1.hdesign_1_auto_us_df_1_sc.hdesign_1_m00_data_fifo_0.hdesign_1_m00_data_fifo_0_sc.hdesign_1_smartconnect_0_0.hdesign_1_smartconnect_0_0_sc.hdesign_1_xbar_0.hdesign_1_xbar_0_sc.hdesign_1_xlconstant_0_0.hdesign_1_xlconstant_0_2.hdesign_1_xlconstant_0_3.hfile_info.txtglbl.vmig_a.prjsc_xtlm_design_1_smartconnect_0_0.memsimulate.dosmartconnect.cxxsmartconnect.hsmartconnect_xtlm.cxxsmartconnect_xtlm.hsmartconnect_xtlm_impl.hsys_clk_gen_ps_v.txtwave.doxlconstant_v1_1_7.h
ies
README.txtaxi_clock_converter.haxi_crossbar.haxi_data_fifo.haxi_dwidth_converter.hbd_48ac_one_0.hdesign_1.shdesign_1_auto_cc_0.hdesign_1_auto_cc_0_sc.hdesign_1_auto_us_df_0.hdesign_1_auto_us_df_0_sc.hdesign_1_auto_us_df_1.hdesign_1_auto_us_df_1_sc.hdesign_1_m00_data_fifo_0.hdesign_1_m00_data_fifo_0_sc.hdesign_1_smartconnect_0_0.hdesign_1_smartconnect_0_0_sc.hdesign_1_xbar_0.hdesign_1_xbar_0_sc.hdesign_1_xlconstant_0_0.hdesign_1_xlconstant_0_2.hdesign_1_xlconstant_0_3.hfile_info.txtglbl.vmig_a.prjrun.fsc_xtlm_design_1_smartconnect_0_0.memsmartconnect.cxxsmartconnect.hsmartconnect_xtlm.cxxsmartconnect_xtlm.hsmartconnect_xtlm_impl.hsys_clk_gen_ps_v.txtxlconstant_v1_1_7.h
modelsim
README.txtaxi_clock_converter.haxi_crossbar.haxi_data_fifo.haxi_dwidth_converter.hbd_48ac_one_0.hcompile.dodesign_1.shdesign_1.udodesign_1_auto_cc_0.hdesign_1_auto_cc_0_sc.hdesign_1_auto_us_df_0.hdesign_1_auto_us_df_0_sc.hdesign_1_auto_us_df_1.hdesign_1_auto_us_df_1_sc.hdesign_1_m00_data_fifo_0.hdesign_1_m00_data_fifo_0_sc.hdesign_1_smartconnect_0_0.hdesign_1_smartconnect_0_0_sc.hdesign_1_xbar_0.hdesign_1_xbar_0_sc.hdesign_1_xlconstant_0_0.hdesign_1_xlconstant_0_2.hdesign_1_xlconstant_0_3.hfile_info.txtglbl.vmig_a.prjsc_xtlm_design_1_smartconnect_0_0.memsimulate.dosmartconnect.cxxsmartconnect.hsmartconnect_xtlm.cxxsmartconnect_xtlm.hsmartconnect_xtlm_impl.hsys_clk_gen_ps_v.txtwave.doxlconstant_v1_1_7.h
questa
README.txtaxi_clock_converter.haxi_crossbar.haxi_data_fifo.haxi_dwidth_converter.hbd_48ac_one_0.hcompile.dodesign_1.shdesign_1.udodesign_1_auto_cc_0.hdesign_1_auto_cc_0_sc.hdesign_1_auto_us_df_0.hdesign_1_auto_us_df_0_sc.hdesign_1_auto_us_df_1.hdesign_1_auto_us_df_1_sc.hdesign_1_m00_data_fifo_0.hdesign_1_m00_data_fifo_0_sc.hdesign_1_smartconnect_0_0.hdesign_1_smartconnect_0_0_sc.hdesign_1_xbar_0.hdesign_1_xbar_0_sc.hdesign_1_xlconstant_0_0.hdesign_1_xlconstant_0_2.hdesign_1_xlconstant_0_3.helaborate.dofile_info.txtglbl.vmig_a.prjsc_xtlm_design_1_smartconnect_0_0.memsimulate.dosmartconnect.cxxsmartconnect.hsmartconnect_xtlm.cxxsmartconnect_xtlm.hsmartconnect_xtlm_impl.hsys_clk_gen_ps_v.txtwave.doxlconstant_v1_1_7.h
riviera
README.txtaxi_clock_converter.haxi_crossbar.haxi_data_fifo.haxi_dwidth_converter.hbd_48ac_one_0.hcompile.dodesign_1.shdesign_1.udodesign_1_auto_cc_0.hdesign_1_auto_cc_0_sc.hdesign_1_auto_us_df_0.hdesign_1_auto_us_df_0_sc.hdesign_1_auto_us_df_1.hdesign_1_auto_us_df_1_sc.hdesign_1_m00_data_fifo_0.hdesign_1_m00_data_fifo_0_sc.hdesign_1_smartconnect_0_0.hdesign_1_smartconnect_0_0_sc.hdesign_1_xbar_0.hdesign_1_xbar_0_sc.hdesign_1_xlconstant_0_0.hdesign_1_xlconstant_0_2.hdesign_1_xlconstant_0_3.hfile_info.txtglbl.vmig_a.prjsc_xtlm_design_1_smartconnect_0_0.memsimulate.dosmartconnect.cxxsmartconnect.hsmartconnect_xtlm.cxxsmartconnect_xtlm.hsmartconnect_xtlm_impl.hsys_clk_gen_ps_v.txtwave.doxlconstant_v1_1_7.h
vcs
README.txtaxi_clock_converter.haxi_crossbar.haxi_data_fifo.haxi_dwidth_converter.hbd_48ac_one_0.hdesign_1.shdesign_1_auto_cc_0.hdesign_1_auto_cc_0_sc.hdesign_1_auto_us_df_0.hdesign_1_auto_us_df_0_sc.hdesign_1_auto_us_df_1.hdesign_1_auto_us_df_1_sc.hdesign_1_m00_data_fifo_0.hdesign_1_m00_data_fifo_0_sc.hdesign_1_smartconnect_0_0.hdesign_1_smartconnect_0_0_sc.hdesign_1_xbar_0.hdesign_1_xbar_0_sc.hdesign_1_xlconstant_0_0.hdesign_1_xlconstant_0_2.hdesign_1_xlconstant_0_3.hfile_info.txtglbl.vmig_a.prjsc_xtlm_design_1_smartconnect_0_0.memsimulate.dosmartconnect.cxxsmartconnect.hsmartconnect_xtlm.cxxsmartconnect_xtlm.hsmartconnect_xtlm_impl.hsys_clk_gen_ps_v.txtxlconstant_v1_1_7.h
xcelium
README.txtaxi_clock_converter.haxi_crossbar.haxi_data_fifo.haxi_dwidth_converter.hbd_48ac_one_0.hdesign_1.shdesign_1_auto_cc_0.hdesign_1_auto_cc_0_sc.hdesign_1_auto_us_df_0.hdesign_1_auto_us_df_0_sc.hdesign_1_auto_us_df_1.hdesign_1_auto_us_df_1_sc.hdesign_1_m00_data_fifo_0.hdesign_1_m00_data_fifo_0_sc.hdesign_1_smartconnect_0_0.hdesign_1_smartconnect_0_0_sc.hdesign_1_xbar_0.hdesign_1_xbar_0_sc.hdesign_1_xlconstant_0_0.hdesign_1_xlconstant_0_2.hdesign_1_xlconstant_0_3.hfile_info.txtglbl.vmig_a.prjrun.fsc_xtlm_design_1_smartconnect_0_0.memsmartconnect.cxxsmartconnect.hsmartconnect_xtlm.cxxsmartconnect_xtlm.hsmartconnect_xtlm_impl.hsys_clk_gen_ps_v.txtxlconstant_v1_1_7.h
xsim
README.txtaxi_clock_converter.haxi_crossbar.haxi_data_fifo.haxi_dwidth_converter.hbd_48ac_one_0.hcmd.tcldesign_1.shdesign_1_auto_cc_0.hdesign_1_auto_cc_0_sc.hdesign_1_auto_us_df_0.hdesign_1_auto_us_df_0_sc.hdesign_1_auto_us_df_1.hdesign_1_auto_us_df_1_sc.hdesign_1_m00_data_fifo_0.hdesign_1_m00_data_fifo_0_sc.hdesign_1_smartconnect_0_0.hdesign_1_smartconnect_0_0_sc.hdesign_1_xbar_0.hdesign_1_xbar_0_sc.hdesign_1_xlconstant_0_0.hdesign_1_xlconstant_0_2.hdesign_1_xlconstant_0_3.helab.optfile_info.txtglbl.vmig_a.prj
protoinst_files
sc_xtlm_design_1_smartconnect_0_0.memsmartconnect.cxxsmartconnect.hsmartconnect_xtlm.cxxsmartconnect_xtlm.hsmartconnect_xtlm_impl.hsys_clk_gen_ps_v.txtvhdl.prjvlog.prjxlconstant_v1_1_7.hxsim.inififo_generator_0
activehdl
ies
modelsim
questa
riviera
vcs
xcelium
xsim
dso_top.srcs/sources_1
bd/design_1
design_1.bddesign_1.bxml
hdl
hw_handoff
ip
design_1_auto_cc_0
design_1_auto_cc_0.dcpdesign_1_auto_cc_0.xmldesign_1_auto_cc_0_sim_netlist.vdesign_1_auto_cc_0_sim_netlist.vhdldesign_1_auto_cc_0_stub.vdesign_1_auto_cc_0_stub.vhdl
design_1_auto_us_df_0
design_1_auto_us_df_0.dcpdesign_1_auto_us_df_0.xmldesign_1_auto_us_df_0_sim_netlist.vdesign_1_auto_us_df_0_sim_netlist.vhdldesign_1_auto_us_df_0_stub.vdesign_1_auto_us_df_0_stub.vhdl
design_1_auto_us_df_1
design_1_auto_us_df_1.dcpdesign_1_auto_us_df_1.xmldesign_1_auto_us_df_1_sim_netlist.vdesign_1_auto_us_df_1_sim_netlist.vhdldesign_1_auto_us_df_1_stub.vdesign_1_auto_us_df_1_stub.vhdl
design_1_axi_datamover_0_0
design_1_axi_datamover_0_0.dcpdesign_1_axi_datamover_0_0.xcidesign_1_axi_datamover_0_0.xmldesign_1_axi_datamover_0_0_sim_netlist.vdesign_1_axi_datamover_0_0_sim_netlist.vhdldesign_1_axi_datamover_0_0_stub.vdesign_1_axi_datamover_0_0_stub.vhdl
design_1_axi_fifo_mm_s_0_0
design_1_axi_fifo_mm_s_0_0.dcpdesign_1_axi_fifo_mm_s_0_0.xmldesign_1_axi_fifo_mm_s_0_0_sim_netlist.vdesign_1_axi_fifo_mm_s_0_0_sim_netlist.vhdldesign_1_axi_fifo_mm_s_0_0_stub.vdesign_1_axi_fifo_mm_s_0_0_stub.vhdl
design_1_axi_gpio_0_1
design_1_axi_gpio_0_1.dcpdesign_1_axi_gpio_0_1.xmldesign_1_axi_gpio_0_1_sim_netlist.vdesign_1_axi_gpio_0_1_sim_netlist.vhdldesign_1_axi_gpio_0_1_stub.vdesign_1_axi_gpio_0_1_stub.vhdl
design_1_axi_gpio_1_0
design_1_axi_gpio_1_0.dcpdesign_1_axi_gpio_1_0.xmldesign_1_axi_gpio_1_0_sim_netlist.vdesign_1_axi_gpio_1_0_sim_netlist.vhdldesign_1_axi_gpio_1_0_stub.vdesign_1_axi_gpio_1_0_stub.vhdl
design_1_clk_wiz_0_0
design_1_clk_wiz_0_0.dcpdesign_1_clk_wiz_0_0.xmldesign_1_clk_wiz_0_0_sim_netlist.vdesign_1_clk_wiz_0_0_sim_netlist.vhdldesign_1_clk_wiz_0_0_stub.vdesign_1_clk_wiz_0_0_stub.vhdl
design_1_m00_data_fifo_0
design_1_m00_data_fifo_0.dcpdesign_1_m00_data_fifo_0.xmldesign_1_m00_data_fifo_0_sim_netlist.vdesign_1_m00_data_fifo_0_sim_netlist.vhdldesign_1_m00_data_fifo_0_stub.vdesign_1_m00_data_fifo_0_stub.vhdl
design_1_mig_7series_0_0
design_1_mig_7series_0_0.dcpdesign_1_mig_7series_0_0.xcidesign_1_mig_7series_0_0.xml
design_1_mig_7series_0_0/user_design/constraints
design_1_mig_7series_0_0_sim_netlist.vdesign_1_mig_7series_0_0_sim_netlist.vhdldesign_1_mig_7series_0_0_stub.vdesign_1_mig_7series_0_0_stub.vhdlmig_b.prjdesign_1_smartconnect_0_0
bd_0
bd_48ac.bdbd_48ac.bxml
design_1_smartconnect_0_0.dcpdesign_1_smartconnect_0_0.xmldesign_1_smartconnect_0_0_sim_netlist.vdesign_1_smartconnect_0_0_sim_netlist.vhdldesign_1_smartconnect_0_0_stub.vdesign_1_smartconnect_0_0_stub.vhdlhw_handoff
ip
ip_0
ip_1
ip_10
ip_11
ip_12
ip_13
ip_14
ip_15
ip_16
ip_17
ip_18
ip_19
ip_2
ip_20
ip_21
ip_22
ip_23
ip_24
ip_25
ip_26
ip_27
ip_28
ip_29
ip_3
ip_30
ip_31
ip_32
ip_33
ip_34
ip_35
ip_36
ip_37
ip_38
ip_39
ip_4
ip_40
ip_41
ip_42
ip_43
ip_44
ip_45
ip_46
ip_5
ip_6
ip_7
ip_8
ip_9
synth
design_1_util_ds_buf_0_0
design_1_util_ds_buf_0_0.dcpdesign_1_util_ds_buf_0_0.xmldesign_1_util_ds_buf_0_0_sim_netlist.vdesign_1_util_ds_buf_0_0_sim_netlist.vhdldesign_1_util_ds_buf_0_0_stub.vdesign_1_util_ds_buf_0_0_stub.vhdl
design_1_util_vector_logic_0_0
design_1_util_vector_logic_0_0.dcpdesign_1_util_vector_logic_0_0.xmldesign_1_util_vector_logic_0_0_sim_netlist.vdesign_1_util_vector_logic_0_0_sim_netlist.vhdldesign_1_util_vector_logic_0_0_stub.vdesign_1_util_vector_logic_0_0_stub.vhdl
design_1_xbar_0
design_1_xbar_0.dcpdesign_1_xbar_0.xmldesign_1_xbar_0_sim_netlist.vdesign_1_xbar_0_sim_netlist.vhdldesign_1_xbar_0_stub.vdesign_1_xbar_0_stub.vhdl
design_1_xdma_0_0
design_1_xdma_0_0.dcpdesign_1_xdma_0_0.xmldesign_1_xdma_0_0_sim_netlist.vdesign_1_xdma_0_0_sim_netlist.vhdldesign_1_xdma_0_0_stub.vdesign_1_xdma_0_0_stub.vhdl
ip_0
ip_1
ip_2
ip_3
ip_4
design_1_xlconstant_0_0
design_1_xlconstant_0_2
design_1_xlconstant_0_3
sim
synth
ui
imports/hdl
ip
.Xil
fifo_generator_0
new
Binary file not shown.
@ -4,7 +4,7 @@
|
||||
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<hwsession version="1" minor="2">
|
||||
<device name="xc7a100t_0" gui_info=""/>
|
||||
<device name="xc7a100t_0" gui_info="dashboard1=hw_ila_1[xc7a100t_0/hw_ila_1/Settings=ILA_SETTINGS_1;xc7a100t_0/hw_ila_1/Trigger Setup=ILA_TRIGGER_1;xc7a100t_0/hw_ila_1/Capture Setup=ILA_CAPTURE_1;xc7a100t_0/hw_ila_1/Status=ILA_STATUS_1;xc7a100t_0/hw_ila_1/Waveform=ILA_WAVE_1;]"/>
|
||||
<ObjectList object_type="hw_cfgmem" gui_info="">
|
||||
<Object name="" gui_info="">
|
||||
<Properties Property="PROGRAM.ADDRESS_RANGE" value="use_file"/>
|
||||
@ -27,5 +27,670 @@
|
||||
<Properties Property="SLR.COUNT" value="1"/>
|
||||
</Object>
|
||||
</ObjectList>
|
||||
<probeset name="hw project" active="false"/>
|
||||
<ObjectList object_type="hw_ila" gui_info="">
|
||||
<Object name="" gui_info="">
|
||||
<Properties Property="CONTROL.TRIGGER_CONDITION" value="AND"/>
|
||||
<Properties Property="CORE_REFRESH_RATE_MS" value="500"/>
|
||||
</Object>
|
||||
<Object name="design_1_i/ila_0" gui_info="">
|
||||
<Properties Property="CONTROL.DATA_DEPTH" value="1024"/>
|
||||
<Properties Property="CONTROL.TRIGGER_CONDITION" value="AND"/>
|
||||
<Properties Property="CONTROL.TRIGGER_POSITION" value="0"/>
|
||||
<Properties Property="CONTROL.WINDOW_COUNT" value="1"/>
|
||||
<Properties Property="CORE_REFRESH_RATE_MS" value="500"/>
|
||||
</Object>
|
||||
</ObjectList>
|
||||
<ObjectList object_type="hw_probe" gui_info="">
|
||||
<Object name="design_1_i/S_AXIS_S2MM_0_1_TDATA[127:0]" gui_info=""/>
|
||||
<Object name="design_1_i/S_AXIS_S2MM_0_1_TLAST" gui_info=""/>
|
||||
<Object name="design_1_i/S_AXIS_S2MM_0_1_TREADY" gui_info="Trigger Setup=0"/>
|
||||
</ObjectList>
|
||||
<probeset name="hw project" active="false">
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe8[0]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const0>"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe5[0]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const0>_1"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe7[0]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const0>_2"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[15]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[0]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_1"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[9]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_10"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[10]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_11"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[11]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_12"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[12]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_13"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[13]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_14"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[14]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_15"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[1]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_2"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[2]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_3"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[3]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_4"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[4]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_5"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[5]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_6"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[6]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_7"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[7]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_8"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[8]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_9"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq128'hXXXX_XXXX_XXXX_XXXX_XXXX_XXXX_XXXX_XXXX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq128'hXXXX_XXXX_XXXX_XXXX_XXXX_XXXX_XXXX_XXXX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe1[127:0]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq128'hXXXX_XXXX_XXXX_XXXX_XXXX_XXXX_XXXX_XXXX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[127]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[126]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[125]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[124]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[123]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[122]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[121]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[120]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[119]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[118]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[117]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[116]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[115]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[114]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[113]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[112]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[111]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[110]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[109]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[108]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[107]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[106]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[105]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[104]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[103]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[102]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[101]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[100]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[99]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[98]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[97]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[96]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[95]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[94]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[93]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[92]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[91]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[90]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[89]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[88]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[87]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[86]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[85]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[84]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[83]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[82]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[81]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[80]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[79]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[78]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[77]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[76]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[75]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[74]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[73]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[72]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[71]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[70]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[69]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[68]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[67]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[66]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[65]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[64]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[63]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[62]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[61]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[60]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[59]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[58]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[57]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[56]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[55]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[54]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[53]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[52]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[51]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[50]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[49]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[48]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[47]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[46]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[45]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[44]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[43]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[42]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[41]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[40]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[39]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[38]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[37]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[36]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[35]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[34]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[33]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[32]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[31]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[30]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[29]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[28]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[27]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[26]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[25]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[24]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[23]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[22]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[21]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[20]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[19]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[18]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[17]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[16]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[15]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[14]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[13]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[12]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[11]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[10]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[9]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[8]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[7]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[6]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[5]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[4]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[3]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[2]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[1]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[0]"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq16'hXXXX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq16'hXXXX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe6[15:0]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq16'hXXXX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[15]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[14]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[13]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[12]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[11]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[10]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[9]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[8]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[7]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[6]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[5]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[4]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[3]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[2]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[1]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[0]"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe4[0]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TLAST"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bR"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe0[0]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bR"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TREADY"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe3[0]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TVALID"/>
|
||||
</nets>
|
||||
</probe>
|
||||
</probeset>
|
||||
</hwsession>
|
||||
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,428 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1
|
||||
// IP Revision: 20
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_auto_cc_0 (
|
||||
s_axi_aclk,
|
||||
s_axi_aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awregion,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arregion,
|
||||
s_axi_arqos,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_aclk,
|
||||
m_axi_aresetn,
|
||||
m_axi_awid,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awsize,
|
||||
m_axi_awburst,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awregion,
|
||||
m_axi_awqos,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bid,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_arid,
|
||||
m_axi_araddr,
|
||||
m_axi_arlen,
|
||||
m_axi_arsize,
|
||||
m_axi_arburst,
|
||||
m_axi_arlock,
|
||||
m_axi_arcache,
|
||||
m_axi_arprot,
|
||||
m_axi_arregion,
|
||||
m_axi_arqos,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rid,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rlast,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
|
||||
input wire s_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
|
||||
input wire s_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [0 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [29 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
|
||||
input wire [3 : 0] s_axi_awregion;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [255 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [31 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [0 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [0 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [29 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [7 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [0 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
|
||||
input wire [3 : 0] s_axi_arregion;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [0 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [255 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 1, ADDR_WIDTH 30, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_T\
|
||||
HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME MI_CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN design_1_mig_7series_0_0_ui_clk, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET M_AXI_ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 MI_CLK CLK" *)
|
||||
input wire m_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME MI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 MI_RST RST" *)
|
||||
input wire m_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
|
||||
output wire [0 : 0] m_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [29 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [7 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||
output wire [2 : 0] m_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||
output wire [1 : 0] m_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [0 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
|
||||
output wire [3 : 0] m_axi_awregion;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [255 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [31 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
|
||||
input wire [0 : 0] m_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
|
||||
output wire [0 : 0] m_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [29 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||
output wire [7 : 0] m_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
|
||||
output wire [2 : 0] m_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
|
||||
output wire [1 : 0] m_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||
output wire [0 : 0] m_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||
output wire [3 : 0] m_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
|
||||
output wire [3 : 0] m_axi_arregion;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||
output wire [3 : 0] m_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
|
||||
input wire [0 : 0] m_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [255 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||
input wire m_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 30, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 128, PHASE 0, CLK_DOMAIN design_1_mig_7series_0_0_ui_clk, NUM_READ_THREADS 1, NUM_WRITE_\
|
||||
THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
axi_clock_converter_v2_1_20_axi_clock_converter #(
|
||||
.C_FAMILY("artix7"),
|
||||
.C_AXI_ID_WIDTH(1),
|
||||
.C_AXI_ADDR_WIDTH(30),
|
||||
.C_AXI_DATA_WIDTH(256),
|
||||
.C_S_AXI_ACLK_RATIO(1),
|
||||
.C_M_AXI_ACLK_RATIO(2),
|
||||
.C_AXI_IS_ACLK_ASYNC(1),
|
||||
.C_AXI_PROTOCOL(0),
|
||||
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_AXI_SUPPORTS_WRITE(1),
|
||||
.C_AXI_SUPPORTS_READ(1),
|
||||
.C_SYNCHRONIZER_STAGE(3)
|
||||
) inst (
|
||||
.s_axi_aclk(s_axi_aclk),
|
||||
.s_axi_aresetn(s_axi_aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(s_axi_awregion),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(1'H0),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(s_axi_arregion),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_aclk(m_axi_aclk),
|
||||
.m_axi_aresetn(m_axi_aresetn),
|
||||
.m_axi_awid(m_axi_awid),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awsize(m_axi_awsize),
|
||||
.m_axi_awburst(m_axi_awburst),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(m_axi_awregion),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(m_axi_bid),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(1'H0),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(m_axi_arid),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(m_axi_arlen),
|
||||
.m_axi_arsize(m_axi_arsize),
|
||||
.m_axi_arburst(m_axi_arburst),
|
||||
.m_axi_arlock(m_axi_arlock),
|
||||
.m_axi_arcache(m_axi_arcache),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(m_axi_arregion),
|
||||
.m_axi_arqos(m_axi_arqos),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(m_axi_rid),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(m_axi_rlast),
|
||||
.m_axi_ruser(1'H0),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,391 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
|
||||
// IP Revision: 21
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_auto_us_df_0 (
|
||||
s_axi_aclk,
|
||||
s_axi_aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awregion,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arregion,
|
||||
s_axi_arqos,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awsize,
|
||||
m_axi_awburst,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awregion,
|
||||
m_axi_awqos,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_araddr,
|
||||
m_axi_arlen,
|
||||
m_axi_arsize,
|
||||
m_axi_arburst,
|
||||
m_axi_arlock,
|
||||
m_axi_arcache,
|
||||
m_axi_arprot,
|
||||
m_axi_arregion,
|
||||
m_axi_arqos,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rlast,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
|
||||
input wire s_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
|
||||
input wire s_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [3 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [63 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
|
||||
input wire [3 : 0] s_axi_awregion;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [127 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [15 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [3 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [3 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [63 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [7 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [0 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
|
||||
input wire [3 : 0] s_axi_arregion;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [3 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [127 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 4, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 32, NUM_WRITE_OUTSTANDING 32, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE\
|
||||
_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [63 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [7 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||
output wire [2 : 0] m_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||
output wire [1 : 0] m_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [0 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
|
||||
output wire [3 : 0] m_axi_awregion;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [255 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [31 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [63 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||
output wire [7 : 0] m_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
|
||||
output wire [2 : 0] m_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
|
||||
output wire [1 : 0] m_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||
output wire [0 : 0] m_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||
output wire [3 : 0] m_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
|
||||
output wire [3 : 0] m_axi_arregion;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||
output wire [3 : 0] m_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [255 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||
input wire m_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 4, NUM_WRITE_OUTSTANDING 4, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_T\
|
||||
HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
axi_dwidth_converter_v2_1_21_top #(
|
||||
.C_FAMILY("artix7"),
|
||||
.C_AXI_PROTOCOL(0),
|
||||
.C_S_AXI_ID_WIDTH(4),
|
||||
.C_SUPPORTS_ID(1),
|
||||
.C_AXI_ADDR_WIDTH(64),
|
||||
.C_S_AXI_DATA_WIDTH(128),
|
||||
.C_M_AXI_DATA_WIDTH(256),
|
||||
.C_AXI_SUPPORTS_WRITE(1),
|
||||
.C_AXI_SUPPORTS_READ(1),
|
||||
.C_FIFO_MODE(1),
|
||||
.C_S_AXI_ACLK_RATIO(1),
|
||||
.C_M_AXI_ACLK_RATIO(2),
|
||||
.C_AXI_IS_ACLK_ASYNC(0),
|
||||
.C_MAX_SPLIT_BEATS(16),
|
||||
.C_PACKING_LEVEL(1),
|
||||
.C_SYNCHRONIZER_STAGE(3)
|
||||
) inst (
|
||||
.s_axi_aclk(s_axi_aclk),
|
||||
.s_axi_aresetn(s_axi_aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(s_axi_awregion),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(s_axi_arregion),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_aclk(1'H0),
|
||||
.m_axi_aresetn(1'H0),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awsize(m_axi_awsize),
|
||||
.m_axi_awburst(m_axi_awburst),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(m_axi_awregion),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(m_axi_arlen),
|
||||
.m_axi_arsize(m_axi_arsize),
|
||||
.m_axi_arburst(m_axi_arburst),
|
||||
.m_axi_arlock(m_axi_arlock),
|
||||
.m_axi_arcache(m_axi_arcache),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(m_axi_arregion),
|
||||
.m_axi_arqos(m_axi_arqos),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(m_axi_rlast),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
|
||||
// IP Revision: 21
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_auto_us_df_1 (
|
||||
s_axi_aclk,
|
||||
s_axi_aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awregion,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awsize,
|
||||
m_axi_awburst,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awregion,
|
||||
m_axi_awqos,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
|
||||
input wire s_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
|
||||
input wire s_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [3 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
|
||||
input wire [3 : 0] s_axi_awregion;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [127 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [15 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [3 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 4, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_T\
|
||||
HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [7 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||
output wire [2 : 0] m_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||
output wire [1 : 0] m_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [0 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
|
||||
output wire [3 : 0] m_axi_awregion;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [255 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [31 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_T\
|
||||
HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
|
||||
axi_dwidth_converter_v2_1_21_top #(
|
||||
.C_FAMILY("artix7"),
|
||||
.C_AXI_PROTOCOL(0),
|
||||
.C_S_AXI_ID_WIDTH(4),
|
||||
.C_SUPPORTS_ID(1),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_S_AXI_DATA_WIDTH(128),
|
||||
.C_M_AXI_DATA_WIDTH(256),
|
||||
.C_AXI_SUPPORTS_WRITE(1),
|
||||
.C_AXI_SUPPORTS_READ(0),
|
||||
.C_FIFO_MODE(1),
|
||||
.C_S_AXI_ACLK_RATIO(1),
|
||||
.C_M_AXI_ACLK_RATIO(2),
|
||||
.C_AXI_IS_ACLK_ASYNC(0),
|
||||
.C_MAX_SPLIT_BEATS(16),
|
||||
.C_PACKING_LEVEL(1),
|
||||
.C_SYNCHRONIZER_STAGE(3)
|
||||
) inst (
|
||||
.s_axi_aclk(s_axi_aclk),
|
||||
.s_axi_aresetn(s_axi_aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(s_axi_awregion),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(4'H0),
|
||||
.s_axi_araddr(32'H00000000),
|
||||
.s_axi_arlen(8'H00),
|
||||
.s_axi_arsize(3'H0),
|
||||
.s_axi_arburst(2'H1),
|
||||
.s_axi_arlock(1'H0),
|
||||
.s_axi_arcache(4'H0),
|
||||
.s_axi_arprot(3'H0),
|
||||
.s_axi_arregion(4'H0),
|
||||
.s_axi_arqos(4'H0),
|
||||
.s_axi_arvalid(1'H0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'H0),
|
||||
.m_axi_aclk(1'H0),
|
||||
.m_axi_aresetn(1'H0),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awsize(m_axi_awsize),
|
||||
.m_axi_awburst(m_axi_awburst),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(m_axi_awregion),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_araddr(),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'H0),
|
||||
.m_axi_rdata(256'H0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.m_axi_rresp(2'H0),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_rvalid(1'H0),
|
||||
.m_axi_rready()
|
||||
);
|
||||
endmodule
|
||||
@ -0,0 +1,390 @@
|
||||
-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_datamover:5.1
|
||||
-- IP Revision: 23
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_datamover_v5_1_23;
|
||||
USE axi_datamover_v5_1_23.axi_datamover;
|
||||
|
||||
ENTITY design_1_axi_datamover_0_0 IS
|
||||
PORT (
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aresetn : IN STD_LOGIC;
|
||||
s2mm_halt : IN STD_LOGIC;
|
||||
s2mm_halt_cmplt : OUT STD_LOGIC;
|
||||
s2mm_err : OUT STD_LOGIC;
|
||||
m_axis_s2mm_cmdsts_awclk : IN STD_LOGIC;
|
||||
m_axis_s2mm_cmdsts_aresetn : IN STD_LOGIC;
|
||||
s_axis_s2mm_cmd_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_cmd_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_cmd_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
|
||||
m_axis_s2mm_sts_tvalid : OUT STD_LOGIC;
|
||||
m_axis_s2mm_sts_tready : IN STD_LOGIC;
|
||||
m_axis_s2mm_sts_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axis_s2mm_sts_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_s2mm_sts_tlast : OUT STD_LOGIC;
|
||||
s2mm_allow_addr_req : IN STD_LOGIC;
|
||||
s2mm_addr_req_posted : OUT STD_LOGIC;
|
||||
s2mm_wr_xfer_cmplt : OUT STD_LOGIC;
|
||||
s2mm_ld_nxt_len : OUT STD_LOGIC;
|
||||
s2mm_wr_len : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s2mm_dbg_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s2mm_dbg_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END design_1_axi_datamover_0_0;
|
||||
|
||||
ARCHITECTURE design_1_axi_datamover_0_0_arch OF design_1_axi_datamover_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_datamover_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_datamover IS
|
||||
GENERIC (
|
||||
C_INCLUDE_MM2S : INTEGER;
|
||||
C_M_AXI_MM2S_ARID : INTEGER;
|
||||
C_M_AXI_MM2S_ID_WIDTH : INTEGER;
|
||||
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_MM2S_STSFIFO : INTEGER;
|
||||
C_MM2S_STSCMD_FIFO_DEPTH : INTEGER;
|
||||
C_MM2S_STSCMD_IS_ASYNC : INTEGER;
|
||||
C_INCLUDE_MM2S_DRE : INTEGER;
|
||||
C_MM2S_BURST_SIZE : INTEGER;
|
||||
C_MM2S_BTT_USED : INTEGER;
|
||||
C_MM2S_ADDR_PIPE_DEPTH : INTEGER;
|
||||
C_INCLUDE_S2MM : INTEGER;
|
||||
C_M_AXI_S2MM_AWID : INTEGER;
|
||||
C_M_AXI_S2MM_ID_WIDTH : INTEGER;
|
||||
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_S2MM_STSFIFO : INTEGER;
|
||||
C_S2MM_STSCMD_FIFO_DEPTH : INTEGER;
|
||||
C_S2MM_STSCMD_IS_ASYNC : INTEGER;
|
||||
C_INCLUDE_S2MM_DRE : INTEGER;
|
||||
C_S2MM_BURST_SIZE : INTEGER;
|
||||
C_S2MM_BTT_USED : INTEGER;
|
||||
C_S2MM_SUPPORT_INDET_BTT : INTEGER;
|
||||
C_S2MM_ADDR_PIPE_DEPTH : INTEGER;
|
||||
C_FAMILY : STRING;
|
||||
C_MM2S_INCLUDE_SF : INTEGER;
|
||||
C_S2MM_INCLUDE_SF : INTEGER;
|
||||
C_ENABLE_CACHE_USER : INTEGER;
|
||||
C_ENABLE_MM2S_TKEEP : INTEGER;
|
||||
C_ENABLE_S2MM_TKEEP : INTEGER;
|
||||
C_ENABLE_SKID_BUF : STRING;
|
||||
C_ENABLE_S2MM_ADV_SIG : INTEGER;
|
||||
C_ENABLE_MM2S_ADV_SIG : INTEGER;
|
||||
C_CMD_WIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
m_axi_mm2s_aclk : IN STD_LOGIC;
|
||||
m_axi_mm2s_aresetn : IN STD_LOGIC;
|
||||
mm2s_halt : IN STD_LOGIC;
|
||||
mm2s_halt_cmplt : OUT STD_LOGIC;
|
||||
mm2s_err : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cmdsts_aclk : IN STD_LOGIC;
|
||||
m_axis_mm2s_cmdsts_aresetn : IN STD_LOGIC;
|
||||
s_axis_mm2s_cmd_tvalid : IN STD_LOGIC;
|
||||
s_axis_mm2s_cmd_tready : OUT STD_LOGIC;
|
||||
s_axis_mm2s_cmd_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
|
||||
m_axis_mm2s_sts_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_sts_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_sts_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axis_mm2s_sts_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_mm2s_sts_tlast : OUT STD_LOGIC;
|
||||
mm2s_allow_addr_req : IN STD_LOGIC;
|
||||
mm2s_addr_req_posted : OUT STD_LOGIC;
|
||||
mm2s_rd_xfer_cmplt : OUT STD_LOGIC;
|
||||
m_axi_mm2s_arid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_arvalid : OUT STD_LOGIC;
|
||||
m_axi_mm2s_arready : IN STD_LOGIC;
|
||||
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_rlast : IN STD_LOGIC;
|
||||
m_axi_mm2s_rvalid : IN STD_LOGIC;
|
||||
m_axi_mm2s_rready : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tlast : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tready : IN STD_LOGIC;
|
||||
mm2s_dbg_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
mm2s_dbg_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aresetn : IN STD_LOGIC;
|
||||
s2mm_halt : IN STD_LOGIC;
|
||||
s2mm_halt_cmplt : OUT STD_LOGIC;
|
||||
s2mm_err : OUT STD_LOGIC;
|
||||
m_axis_s2mm_cmdsts_awclk : IN STD_LOGIC;
|
||||
m_axis_s2mm_cmdsts_aresetn : IN STD_LOGIC;
|
||||
s_axis_s2mm_cmd_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_cmd_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_cmd_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
|
||||
m_axis_s2mm_sts_tvalid : OUT STD_LOGIC;
|
||||
m_axis_s2mm_sts_tready : IN STD_LOGIC;
|
||||
m_axis_s2mm_sts_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axis_s2mm_sts_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_s2mm_sts_tlast : OUT STD_LOGIC;
|
||||
s2mm_allow_addr_req : IN STD_LOGIC;
|
||||
s2mm_addr_req_posted : OUT STD_LOGIC;
|
||||
s2mm_wr_xfer_cmplt : OUT STD_LOGIC;
|
||||
s2mm_ld_nxt_len : OUT STD_LOGIC;
|
||||
s2mm_wr_len : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s2mm_dbg_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s2mm_dbg_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_datamover;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_s2mm_tdata: SIGNAL IS "XIL_INTERFACENAME S_AXIS_S2MM, TDATA_NUM_BYTES 16, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awuser: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWUSER";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_awid: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM, NUM_WRITE_OUTSTANDING 2, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 4, ADDR_WIDTH 32, AWUSER_WIDTH 4, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WR" &
|
||||
"ITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TKEEP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_s2mm_sts_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_S2MM_STS, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_cmd_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_CMD TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_cmd_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_CMD TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_s2mm_cmd_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_S2MM_CMD, TDATA_NUM_BYTES 9, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_cmd_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_CMD TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_s2mm_cmdsts_aresetn: SIGNAL IS "XIL_INTERFACENAME M_AXIS_S2MM_CMDSTS_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_cmdsts_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIS_S2MM_CMDSTS_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_s2mm_cmdsts_awclk: SIGNAL IS "XIL_INTERFACENAME M_AXIS_S2MM_CMDSTS_AWCLK, ASSOCIATED_BUSIF S_AXIS_S2MM_CMD:M_AXIS_S2MM_STS, ASSOCIATED_RESET m_axis_s2mm_cmdsts_aresetn, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_cmdsts_awclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_S2MM_CMDSTS_AWCLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_aresetn: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXI_S2MM_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_aclk: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM_ACLK, ASSOCIATED_BUSIF M_AXI_S2MM:S_AXIS_S2MM, ASSOCIATED_RESET m_axi_s2mm_aresetn, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_ACLK CLK";
|
||||
BEGIN
|
||||
U0 : axi_datamover
|
||||
GENERIC MAP (
|
||||
C_INCLUDE_MM2S => 0,
|
||||
C_M_AXI_MM2S_ARID => 0,
|
||||
C_M_AXI_MM2S_ID_WIDTH => 4,
|
||||
C_M_AXI_MM2S_ADDR_WIDTH => 32,
|
||||
C_M_AXI_MM2S_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
|
||||
C_INCLUDE_MM2S_STSFIFO => 0,
|
||||
C_MM2S_STSCMD_FIFO_DEPTH => 4,
|
||||
C_MM2S_STSCMD_IS_ASYNC => 0,
|
||||
C_INCLUDE_MM2S_DRE => 0,
|
||||
C_MM2S_BURST_SIZE => 16,
|
||||
C_MM2S_BTT_USED => 16,
|
||||
C_MM2S_ADDR_PIPE_DEPTH => 3,
|
||||
C_INCLUDE_S2MM => 1,
|
||||
C_M_AXI_S2MM_AWID => 0,
|
||||
C_M_AXI_S2MM_ID_WIDTH => 4,
|
||||
C_M_AXI_S2MM_ADDR_WIDTH => 32,
|
||||
C_M_AXI_S2MM_DATA_WIDTH => 128,
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH => 128,
|
||||
C_INCLUDE_S2MM_STSFIFO => 1,
|
||||
C_S2MM_STSCMD_FIFO_DEPTH => 4,
|
||||
C_S2MM_STSCMD_IS_ASYNC => 0,
|
||||
C_INCLUDE_S2MM_DRE => 0,
|
||||
C_S2MM_BURST_SIZE => 256,
|
||||
C_S2MM_BTT_USED => 16,
|
||||
C_S2MM_SUPPORT_INDET_BTT => 0,
|
||||
C_S2MM_ADDR_PIPE_DEPTH => 4,
|
||||
C_FAMILY => "artix7",
|
||||
C_MM2S_INCLUDE_SF => 0,
|
||||
C_S2MM_INCLUDE_SF => 1,
|
||||
C_ENABLE_CACHE_USER => 0,
|
||||
C_ENABLE_MM2S_TKEEP => 1,
|
||||
C_ENABLE_S2MM_TKEEP => 1,
|
||||
C_ENABLE_SKID_BUF => "11111",
|
||||
C_ENABLE_S2MM_ADV_SIG => 1,
|
||||
C_ENABLE_MM2S_ADV_SIG => 0,
|
||||
C_CMD_WIDTH => 72
|
||||
)
|
||||
PORT MAP (
|
||||
m_axi_mm2s_aclk => '0',
|
||||
m_axi_mm2s_aresetn => '1',
|
||||
mm2s_halt => '0',
|
||||
m_axis_mm2s_cmdsts_aclk => '0',
|
||||
m_axis_mm2s_cmdsts_aresetn => '1',
|
||||
s_axis_mm2s_cmd_tvalid => '0',
|
||||
s_axis_mm2s_cmd_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 72)),
|
||||
m_axis_mm2s_sts_tready => '0',
|
||||
mm2s_allow_addr_req => '1',
|
||||
m_axi_mm2s_arready => '0',
|
||||
m_axi_mm2s_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
m_axi_mm2s_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_mm2s_rlast => '0',
|
||||
m_axi_mm2s_rvalid => '0',
|
||||
m_axis_mm2s_tready => '0',
|
||||
mm2s_dbg_sel => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
|
||||
m_axi_s2mm_aresetn => m_axi_s2mm_aresetn,
|
||||
s2mm_halt => s2mm_halt,
|
||||
s2mm_halt_cmplt => s2mm_halt_cmplt,
|
||||
s2mm_err => s2mm_err,
|
||||
m_axis_s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk,
|
||||
m_axis_s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn,
|
||||
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid,
|
||||
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready,
|
||||
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata,
|
||||
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid,
|
||||
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready,
|
||||
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata,
|
||||
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep,
|
||||
m_axis_s2mm_sts_tlast => m_axis_s2mm_sts_tlast,
|
||||
s2mm_allow_addr_req => s2mm_allow_addr_req,
|
||||
s2mm_addr_req_posted => s2mm_addr_req_posted,
|
||||
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt,
|
||||
s2mm_ld_nxt_len => s2mm_ld_nxt_len,
|
||||
s2mm_wr_len => s2mm_wr_len,
|
||||
m_axi_s2mm_awid => m_axi_s2mm_awid,
|
||||
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
|
||||
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
|
||||
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
|
||||
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
|
||||
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
|
||||
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
|
||||
m_axi_s2mm_awuser => m_axi_s2mm_awuser,
|
||||
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
|
||||
m_axi_s2mm_awready => m_axi_s2mm_awready,
|
||||
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
|
||||
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
|
||||
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
|
||||
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
|
||||
m_axi_s2mm_wready => m_axi_s2mm_wready,
|
||||
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
|
||||
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
|
||||
m_axi_s2mm_bready => m_axi_s2mm_bready,
|
||||
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
|
||||
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
|
||||
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
|
||||
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
|
||||
s_axis_s2mm_tready => s_axis_s2mm_tready,
|
||||
s2mm_dbg_sel => s2mm_dbg_sel,
|
||||
s2mm_dbg_data => s2mm_dbg_data
|
||||
);
|
||||
END design_1_axi_datamover_0_0_arch;
|
||||
@ -0,0 +1,343 @@
|
||||
-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_fifo_mm_s:4.2
|
||||
-- IP Revision: 3
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_fifo_mm_s_v4_2_3;
|
||||
USE axi_fifo_mm_s_v4_2_3.axi_fifo_mm_s;
|
||||
|
||||
ENTITY design_1_axi_fifo_mm_s_0_0 IS
|
||||
PORT (
|
||||
interrupt : OUT STD_LOGIC;
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
axi_str_txd_tvalid : OUT STD_LOGIC;
|
||||
axi_str_txd_tready : IN STD_LOGIC;
|
||||
axi_str_txd_tlast : OUT STD_LOGIC;
|
||||
axi_str_txd_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END design_1_axi_fifo_mm_s_0_0;
|
||||
|
||||
ARCHITECTURE design_1_axi_fifo_mm_s_0_0_arch OF design_1_axi_fifo_mm_s_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_fifo_mm_s_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_fifo_mm_s IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_S_AXI_ID_WIDTH : INTEGER;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_S_AXI4_DATA_WIDTH : INTEGER;
|
||||
C_TX_FIFO_DEPTH : INTEGER;
|
||||
C_RX_FIFO_DEPTH : INTEGER;
|
||||
C_TX_CASCADE_HEIGHT : INTEGER;
|
||||
C_RX_CASCADE_HEIGHT : INTEGER;
|
||||
C_TX_FIFO_PF_THRESHOLD : INTEGER;
|
||||
C_TX_FIFO_PE_THRESHOLD : INTEGER;
|
||||
C_RX_FIFO_PF_THRESHOLD : INTEGER;
|
||||
C_RX_FIFO_PE_THRESHOLD : INTEGER;
|
||||
C_USE_TX_CUT_THROUGH : INTEGER;
|
||||
C_DATA_INTERFACE_TYPE : INTEGER;
|
||||
C_BASEADDR : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_HIGHADDR : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_AXI4_BASEADDR : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_AXI4_HIGHADDR : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_HAS_AXIS_TID : INTEGER;
|
||||
C_HAS_AXIS_TDEST : INTEGER;
|
||||
C_HAS_AXIS_TUSER : INTEGER;
|
||||
C_HAS_AXIS_TSTRB : INTEGER;
|
||||
C_HAS_AXIS_TKEEP : INTEGER;
|
||||
C_AXIS_TID_WIDTH : INTEGER;
|
||||
C_AXIS_TDEST_WIDTH : INTEGER;
|
||||
C_AXIS_TUSER_WIDTH : INTEGER;
|
||||
C_USE_RX_CUT_THROUGH : INTEGER;
|
||||
C_USE_TX_DATA : INTEGER;
|
||||
C_USE_TX_CTRL : INTEGER;
|
||||
C_USE_RX_DATA : INTEGER
|
||||
);
|
||||
PORT (
|
||||
interrupt : OUT STD_LOGIC;
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
s_axi4_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi4_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi4_awlock : IN STD_LOGIC;
|
||||
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi4_awvalid : IN STD_LOGIC;
|
||||
s_axi4_awready : OUT STD_LOGIC;
|
||||
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi4_wlast : IN STD_LOGIC;
|
||||
s_axi4_wvalid : IN STD_LOGIC;
|
||||
s_axi4_wready : OUT STD_LOGIC;
|
||||
s_axi4_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi4_bvalid : OUT STD_LOGIC;
|
||||
s_axi4_bready : IN STD_LOGIC;
|
||||
s_axi4_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi4_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi4_arlock : IN STD_LOGIC;
|
||||
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi4_arvalid : IN STD_LOGIC;
|
||||
s_axi4_arready : OUT STD_LOGIC;
|
||||
s_axi4_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi4_rlast : OUT STD_LOGIC;
|
||||
s_axi4_rvalid : OUT STD_LOGIC;
|
||||
s_axi4_rready : IN STD_LOGIC;
|
||||
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
axi_str_txd_tvalid : OUT STD_LOGIC;
|
||||
axi_str_txd_tready : IN STD_LOGIC;
|
||||
axi_str_txd_tlast : OUT STD_LOGIC;
|
||||
axi_str_txd_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_str_txd_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
axi_str_txd_tstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_str_txd_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_str_txd_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_str_txd_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
|
||||
axi_str_txc_tvalid : OUT STD_LOGIC;
|
||||
axi_str_txc_tready : IN STD_LOGIC;
|
||||
axi_str_txc_tlast : OUT STD_LOGIC;
|
||||
axi_str_txc_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_str_txc_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
axi_str_txc_tstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_str_txc_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_str_txc_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_str_txc_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
axi_str_rxd_tvalid : IN STD_LOGIC;
|
||||
axi_str_rxd_tready : OUT STD_LOGIC;
|
||||
axi_str_rxd_tlast : IN STD_LOGIC;
|
||||
axi_str_rxd_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_str_rxd_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
axi_str_rxd_tstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_str_rxd_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_str_rxd_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
axi_str_rxd_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_fifo_mm_s;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axi_str_txd_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_STR_TXD TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axi_str_txd_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_STR_TXD TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axi_str_txd_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_STR_TXD TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axi_str_txd_tvalid: SIGNAL IS "XIL_INTERFACENAME AXI_STR_TXD, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axi_str_txd_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_STR_TXD TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mm2s_prmry_reset_out_n: SIGNAL IS "XIL_INTERFACENAME rst_axi_str_txd, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 rst_axi_str_txd RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_" &
|
||||
"THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME rst_s_axi, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 rst_s_axi RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME aclk_s_axi, ASSOCIATED_BUSIF S_AXI:S_AXI_FULL:AXI_STR_TXD:AXI_STR_TXC:AXI_STR_RXD, ASSOCIATED_RESET s_axi_aresetn:mm2s_prmry_reset_out_n:mm2s_cntrl_reset_out_n:s2mm_prmry_reset_out_n, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_s_axi CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF interrupt: SIGNAL IS "XIL_INTERFACENAME interrupt_intf, SENSITIVITY LEVEL_HIGH, PortWidth 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt_intf INTERRUPT";
|
||||
BEGIN
|
||||
U0 : axi_fifo_mm_s
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "artix7",
|
||||
C_S_AXI_ID_WIDTH => 4,
|
||||
C_S_AXI_ADDR_WIDTH => 32,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_S_AXI4_DATA_WIDTH => 32,
|
||||
C_TX_FIFO_DEPTH => 512,
|
||||
C_RX_FIFO_DEPTH => 512,
|
||||
C_TX_CASCADE_HEIGHT => 0,
|
||||
C_RX_CASCADE_HEIGHT => 0,
|
||||
C_TX_FIFO_PF_THRESHOLD => 507,
|
||||
C_TX_FIFO_PE_THRESHOLD => 5,
|
||||
C_RX_FIFO_PF_THRESHOLD => 507,
|
||||
C_RX_FIFO_PE_THRESHOLD => 5,
|
||||
C_USE_TX_CUT_THROUGH => 0,
|
||||
C_DATA_INTERFACE_TYPE => 0,
|
||||
C_BASEADDR => X"40020000",
|
||||
C_HIGHADDR => X"4002FFFF",
|
||||
C_AXI4_BASEADDR => X"80001000",
|
||||
C_AXI4_HIGHADDR => X"80002FFF",
|
||||
C_HAS_AXIS_TID => 0,
|
||||
C_HAS_AXIS_TDEST => 0,
|
||||
C_HAS_AXIS_TUSER => 0,
|
||||
C_HAS_AXIS_TSTRB => 0,
|
||||
C_HAS_AXIS_TKEEP => 0,
|
||||
C_AXIS_TID_WIDTH => 4,
|
||||
C_AXIS_TDEST_WIDTH => 4,
|
||||
C_AXIS_TUSER_WIDTH => 4,
|
||||
C_USE_RX_CUT_THROUGH => 0,
|
||||
C_USE_TX_DATA => 1,
|
||||
C_USE_TX_CTRL => 0,
|
||||
C_USE_RX_DATA => 0
|
||||
)
|
||||
PORT MAP (
|
||||
interrupt => interrupt,
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
s_axi4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
s_axi4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
s_axi4_awlock => '0',
|
||||
s_axi4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi4_awvalid => '0',
|
||||
s_axi4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi4_wlast => '0',
|
||||
s_axi4_wvalid => '0',
|
||||
s_axi4_bready => '0',
|
||||
s_axi4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
s_axi4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
s_axi4_arlock => '0',
|
||||
s_axi4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi4_arvalid => '0',
|
||||
s_axi4_rready => '0',
|
||||
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
|
||||
axi_str_txd_tvalid => axi_str_txd_tvalid,
|
||||
axi_str_txd_tready => axi_str_txd_tready,
|
||||
axi_str_txd_tlast => axi_str_txd_tlast,
|
||||
axi_str_txd_tdata => axi_str_txd_tdata,
|
||||
axi_str_txc_tready => '0',
|
||||
axi_str_rxd_tvalid => '0',
|
||||
axi_str_rxd_tlast => '0',
|
||||
axi_str_rxd_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
axi_str_rxd_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
axi_str_rxd_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
axi_str_rxd_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
axi_str_rxd_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
axi_str_rxd_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4))
|
||||
);
|
||||
END design_1_axi_fifo_mm_s_0_0_arch;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,207 @@
|
||||
-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
|
||||
-- IP Revision: 23
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_gpio_v2_0_23;
|
||||
USE axi_gpio_v2_0_23.axi_gpio;
|
||||
|
||||
ENTITY design_1_axi_gpio_0_1 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END design_1_axi_gpio_0_1;
|
||||
|
||||
ARCHITECTURE design_1_axi_gpio_0_1_arch OF design_1_axi_gpio_0_1 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_gpio_0_1_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_gpio IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_GPIO_WIDTH : INTEGER;
|
||||
C_GPIO2_WIDTH : INTEGER;
|
||||
C_ALL_INPUTS : INTEGER;
|
||||
C_ALL_INPUTS_2 : INTEGER;
|
||||
C_ALL_OUTPUTS : INTEGER;
|
||||
C_ALL_OUTPUTS_2 : INTEGER;
|
||||
C_INTERRUPT_PRESENT : INTEGER;
|
||||
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_IS_DUAL : INTEGER;
|
||||
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_gpio;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio2_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_o: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_T" &
|
||||
"HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
|
||||
BEGIN
|
||||
U0 : axi_gpio
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "artix7",
|
||||
C_S_AXI_ADDR_WIDTH => 9,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_GPIO_WIDTH => 32,
|
||||
C_GPIO2_WIDTH => 32,
|
||||
C_ALL_INPUTS => 0,
|
||||
C_ALL_INPUTS_2 => 1,
|
||||
C_ALL_OUTPUTS => 1,
|
||||
C_ALL_OUTPUTS_2 => 0,
|
||||
C_INTERRUPT_PRESENT => 0,
|
||||
C_DOUT_DEFAULT => X"00000000",
|
||||
C_TRI_DEFAULT => X"FFFFFFFF",
|
||||
C_IS_DUAL => 1,
|
||||
C_DOUT_DEFAULT_2 => X"00000000",
|
||||
C_TRI_DEFAULT_2 => X"FFFFFFFF"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
gpio_io_o => gpio_io_o,
|
||||
gpio2_io_i => gpio2_io_i
|
||||
);
|
||||
END design_1_axi_gpio_0_1_arch;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,207 @@
|
||||
-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
|
||||
-- IP Revision: 23
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_gpio_v2_0_23;
|
||||
USE axi_gpio_v2_0_23.axi_gpio;
|
||||
|
||||
ENTITY design_1_axi_gpio_1_0 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END design_1_axi_gpio_1_0;
|
||||
|
||||
ARCHITECTURE design_1_axi_gpio_1_0_arch OF design_1_axi_gpio_1_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_gpio_1_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_gpio IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_GPIO_WIDTH : INTEGER;
|
||||
C_GPIO2_WIDTH : INTEGER;
|
||||
C_ALL_INPUTS : INTEGER;
|
||||
C_ALL_INPUTS_2 : INTEGER;
|
||||
C_ALL_OUTPUTS : INTEGER;
|
||||
C_ALL_OUTPUTS_2 : INTEGER;
|
||||
C_INTERRUPT_PRESENT : INTEGER;
|
||||
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_IS_DUAL : INTEGER;
|
||||
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_gpio;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio2_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_o: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_T" &
|
||||
"HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
|
||||
BEGIN
|
||||
U0 : axi_gpio
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "artix7",
|
||||
C_S_AXI_ADDR_WIDTH => 9,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_GPIO_WIDTH => 32,
|
||||
C_GPIO2_WIDTH => 32,
|
||||
C_ALL_INPUTS => 0,
|
||||
C_ALL_INPUTS_2 => 1,
|
||||
C_ALL_OUTPUTS => 1,
|
||||
C_ALL_OUTPUTS_2 => 0,
|
||||
C_INTERRUPT_PRESENT => 0,
|
||||
C_DOUT_DEFAULT => X"00000000",
|
||||
C_TRI_DEFAULT => X"FFFFFFFF",
|
||||
C_IS_DUAL => 1,
|
||||
C_DOUT_DEFAULT_2 => X"00000000",
|
||||
C_TRI_DEFAULT_2 => X"FFFFFFFF"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
gpio_io_o => gpio_io_o,
|
||||
gpio2_io_i => gpio2_io_i
|
||||
);
|
||||
END design_1_axi_gpio_1_0_arch;
|
||||
@ -0,0 +1,92 @@
|
||||
|
||||
// file: design_1_clk_wiz_0_0.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1__200.00000______0.000______50.0______109.241_____96.948
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary_________125.000____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "design_1_clk_wiz_0_0,clk_wiz_v6_0_5_0_0,{component_name=design_1_clk_wiz_0_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=1,clkin1_period=8.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
|
||||
|
||||
module design_1_clk_wiz_0_0
|
||||
(
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
// Status and control signals
|
||||
input resetn,
|
||||
output locked,
|
||||
// Clock in ports
|
||||
input clk_in1
|
||||
);
|
||||
|
||||
design_1_clk_wiz_0_0_clk_wiz inst
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1(clk_out1),
|
||||
// Status and control signals
|
||||
.resetn(resetn),
|
||||
.locked(locked),
|
||||
// Clock in ports
|
||||
.clk_in1(clk_in1)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@ -0,0 +1,182 @@
|
||||
|
||||
// file: design_1_clk_wiz_0_0.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1__200.00000______0.000______50.0______109.241_____96.948
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary_________125.000____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module design_1_clk_wiz_0_0_clk_wiz
|
||||
|
||||
(// Clock in ports
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
// Status and control signals
|
||||
input resetn,
|
||||
output locked,
|
||||
input clk_in1
|
||||
);
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
wire clk_in1_design_1_clk_wiz_0_0;
|
||||
wire clk_in2_design_1_clk_wiz_0_0;
|
||||
assign clk_in1_design_1_clk_wiz_0_0 = clk_in1;
|
||||
|
||||
|
||||
|
||||
|
||||
// Clocking PRIMITIVE
|
||||
//------------------------------------
|
||||
|
||||
// Instantiation of the MMCM PRIMITIVE
|
||||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
|
||||
wire clk_out1_design_1_clk_wiz_0_0;
|
||||
wire clk_out2_design_1_clk_wiz_0_0;
|
||||
wire clk_out3_design_1_clk_wiz_0_0;
|
||||
wire clk_out4_design_1_clk_wiz_0_0;
|
||||
wire clk_out5_design_1_clk_wiz_0_0;
|
||||
wire clk_out6_design_1_clk_wiz_0_0;
|
||||
wire clk_out7_design_1_clk_wiz_0_0;
|
||||
|
||||
wire [15:0] do_unused;
|
||||
wire drdy_unused;
|
||||
wire psdone_unused;
|
||||
wire locked_int;
|
||||
wire clkfbout_design_1_clk_wiz_0_0;
|
||||
wire clkfbout_buf_design_1_clk_wiz_0_0;
|
||||
wire clkfboutb_unused;
|
||||
wire clkout1_unused;
|
||||
wire clkout2_unused;
|
||||
wire clkout3_unused;
|
||||
wire clkout4_unused;
|
||||
wire clkout5_unused;
|
||||
wire clkout6_unused;
|
||||
wire clkfbstopped_unused;
|
||||
wire clkinstopped_unused;
|
||||
wire reset_high;
|
||||
|
||||
PLLE2_ADV
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
.COMPENSATION ("ZHOLD"),
|
||||
.STARTUP_WAIT ("FALSE"),
|
||||
.DIVCLK_DIVIDE (1),
|
||||
.CLKFBOUT_MULT (8),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKOUT0_DIVIDE (5),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKIN1_PERIOD (8.000))
|
||||
plle2_adv_inst
|
||||
// Output clocks
|
||||
(
|
||||
.CLKFBOUT (clkfbout_design_1_clk_wiz_0_0),
|
||||
.CLKOUT0 (clk_out1_design_1_clk_wiz_0_0),
|
||||
.CLKOUT1 (clkout1_unused),
|
||||
.CLKOUT2 (clkout2_unused),
|
||||
.CLKOUT3 (clkout3_unused),
|
||||
.CLKOUT4 (clkout4_unused),
|
||||
.CLKOUT5 (clkout5_unused),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfbout_buf_design_1_clk_wiz_0_0),
|
||||
.CLKIN1 (clk_in1_design_1_clk_wiz_0_0),
|
||||
.CLKIN2 (1'b0),
|
||||
// Tied to always select the primary input clock
|
||||
.CLKINSEL (1'b1),
|
||||
// Ports for dynamic reconfiguration
|
||||
.DADDR (7'h0),
|
||||
.DCLK (1'b0),
|
||||
.DEN (1'b0),
|
||||
.DI (16'h0),
|
||||
.DO (do_unused),
|
||||
.DRDY (drdy_unused),
|
||||
.DWE (1'b0),
|
||||
// Other control and status signals
|
||||
.LOCKED (locked_int),
|
||||
.PWRDWN (1'b0),
|
||||
.RST (reset_high));
|
||||
assign reset_high = ~resetn;
|
||||
|
||||
assign locked = locked_int;
|
||||
// Clock Monitor clock assigning
|
||||
//--------------------------------------
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
|
||||
BUFG clkf_buf
|
||||
(.O (clkfbout_buf_design_1_clk_wiz_0_0),
|
||||
.I (clkfbout_design_1_clk_wiz_0_0));
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
BUFG clkout1_buf
|
||||
(.O (clk_out1),
|
||||
.I (clk_out1_design_1_clk_wiz_0_0));
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,418 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_data_fifo:2.1
|
||||
// IP Revision: 20
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_m00_data_fifo_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awregion,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arregion,
|
||||
s_axi_arqos,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awid,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awsize,
|
||||
m_axi_awburst,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awregion,
|
||||
m_axi_awqos,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bid,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_arid,
|
||||
m_axi_araddr,
|
||||
m_axi_arlen,
|
||||
m_axi_arsize,
|
||||
m_axi_arburst,
|
||||
m_axi_arlock,
|
||||
m_axi_arcache,
|
||||
m_axi_arprot,
|
||||
m_axi_arregion,
|
||||
m_axi_arqos,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rid,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rlast,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [0 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [29 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
|
||||
input wire [3 : 0] s_axi_awregion;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [255 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [31 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [0 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [0 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [29 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [7 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [0 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
|
||||
input wire [3 : 0] s_axi_arregion;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [0 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [255 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 1, ADDR_WIDTH 30, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_T\
|
||||
HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
|
||||
output wire [0 : 0] m_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [29 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [7 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||
output wire [2 : 0] m_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||
output wire [1 : 0] m_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [0 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
|
||||
output wire [3 : 0] m_axi_awregion;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [255 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [31 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
|
||||
input wire [0 : 0] m_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
|
||||
output wire [0 : 0] m_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [29 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||
output wire [7 : 0] m_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
|
||||
output wire [2 : 0] m_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
|
||||
output wire [1 : 0] m_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||
output wire [0 : 0] m_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||
output wire [3 : 0] m_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
|
||||
output wire [3 : 0] m_axi_arregion;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||
output wire [3 : 0] m_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
|
||||
input wire [0 : 0] m_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [255 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||
input wire m_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 1, ADDR_WIDTH 30, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_T\
|
||||
HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
axi_data_fifo_v2_1_20_axi_data_fifo #(
|
||||
.C_FAMILY("artix7"),
|
||||
.C_AXI_PROTOCOL(0),
|
||||
.C_AXI_ID_WIDTH(1),
|
||||
.C_AXI_ADDR_WIDTH(30),
|
||||
.C_AXI_DATA_WIDTH(256),
|
||||
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_AXI_WRITE_FIFO_DEPTH(512),
|
||||
.C_AXI_WRITE_FIFO_TYPE("bram"),
|
||||
.C_AXI_WRITE_FIFO_DELAY(1),
|
||||
.C_AXI_READ_FIFO_DEPTH(512),
|
||||
.C_AXI_READ_FIFO_TYPE("bram"),
|
||||
.C_AXI_READ_FIFO_DELAY(1)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(s_axi_awregion),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(1'H0),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(s_axi_arregion),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(m_axi_awid),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awsize(m_axi_awsize),
|
||||
.m_axi_awburst(m_axi_awburst),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(m_axi_awregion),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(m_axi_bid),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(1'H0),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(m_axi_arid),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(m_axi_arlen),
|
||||
.m_axi_arsize(m_axi_arsize),
|
||||
.m_axi_arburst(m_axi_arburst),
|
||||
.m_axi_arlock(m_axi_arlock),
|
||||
.m_axi_arcache(m_axi_arcache),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(m_axi_arregion),
|
||||
.m_axi_arqos(m_axi_arqos),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(m_axi_rid),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(m_axi_rlast),
|
||||
.m_axi_ruser(1'H0),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
@ -0,0 +1,164 @@
|
||||
// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
|
||||
// --
|
||||
// -- This file contains confidential and proprietary information
|
||||
// -- of Xilinx, Inc. and is protected under U.S. and
|
||||
// -- international copyright and other intellectual property
|
||||
// -- laws.
|
||||
// --
|
||||
// -- DISCLAIMER
|
||||
// -- This disclaimer is not a license and does not grant any
|
||||
// -- rights to the materials distributed herewith. Except as
|
||||
// -- otherwise provided in a valid license issued to you by
|
||||
// -- Xilinx, and to the maximum extent permitted by applicable
|
||||
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// -- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// -- including negligence, or under any other theory of
|
||||
// -- liability) for any loss or damage of any kind or nature
|
||||
// -- related to, arising under or in connection with these
|
||||
// -- materials, including for any direct, or any indirect,
|
||||
// -- special, incidental, or consequential loss or damage
|
||||
// -- (including loss of data, profits, goodwill, or any type of
|
||||
// -- loss or damage suffered as a result of any action brought
|
||||
// -- by a third party) even if such damage or loss was
|
||||
// -- reasonably foreseeable or Xilinx had been advised of the
|
||||
// -- possibility of the same.
|
||||
// --
|
||||
// -- CRITICAL APPLICATIONS
|
||||
// -- Xilinx products are not designed or intended to be fail-
|
||||
// -- safe, or for use in any application requiring fail-safe
|
||||
// -- performance, such as life-support or safety devices or
|
||||
// -- systems, Class III medical devices, nuclear facilities,
|
||||
// -- applications related to the deployment of airbags, or any
|
||||
// -- other applications that could lead to death, personal
|
||||
// -- injury, or severe property or environmental damage
|
||||
// -- (individually and collectively, "Critical
|
||||
// -- Applications"). Customer assumes the sole risk and
|
||||
// -- liability of any use of Xilinx products in Critical
|
||||
// -- Applications, subject only to applicable laws and
|
||||
// -- regulations governing limitations on product liability.
|
||||
// --
|
||||
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// -- PART OF THIS FILE AT ALL TIMES.
|
||||
// --
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// File name: axi_ctrl_ecc_top.v
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// Specifications:
|
||||
//
|
||||
// Structure:
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
module mig_7series_v4_2_axi_ctrl_addr_decode #
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Parameter Definitions
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Width of AXI-4-Lite address bus
|
||||
parameter integer C_ADDR_WIDTH = 32,
|
||||
// Number of Registers
|
||||
parameter integer C_NUM_REG = 5,
|
||||
parameter integer C_NUM_REG_WIDTH = 3,
|
||||
// Number of Registers
|
||||
parameter C_REG_ADDR_ARRAY = 160'h0000_f00C_0000_f008_0000_f004_0000_f000_FFFF_FFFF,
|
||||
parameter C_REG_RDWR_ARRAY = 5'b00101
|
||||
|
||||
)
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Port Declarations
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// AXI4-Lite Slave Interface
|
||||
// Slave Interface System Signals
|
||||
input wire [C_ADDR_WIDTH-1:0] axaddr ,
|
||||
// Slave Interface Write Data Ports
|
||||
output wire [C_NUM_REG_WIDTH-1:0] reg_decode_num
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
function [C_ADDR_WIDTH-1:0] calc_bit_mask (
|
||||
input [C_NUM_REG*C_ADDR_WIDTH-1:0] addr_decode_array
|
||||
);
|
||||
begin : func_calc_bit_mask
|
||||
integer i;
|
||||
reg [C_ADDR_WIDTH-1:0] first_addr;
|
||||
reg [C_ADDR_WIDTH-1:0] bit_mask;
|
||||
|
||||
calc_bit_mask = {C_ADDR_WIDTH{1'b0}};
|
||||
first_addr = addr_decode_array[C_ADDR_WIDTH+:C_ADDR_WIDTH];
|
||||
|
||||
for (i = 2; i < C_NUM_REG; i = i + 1) begin
|
||||
bit_mask = first_addr ^ addr_decode_array[C_ADDR_WIDTH*i +: C_ADDR_WIDTH];
|
||||
calc_bit_mask = calc_bit_mask | bit_mask;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer lsb_mask_index (
|
||||
input [C_ADDR_WIDTH-1:0] mask
|
||||
);
|
||||
begin : my_lsb_mask_index
|
||||
lsb_mask_index = 0;
|
||||
while ((lsb_mask_index < C_ADDR_WIDTH-1) && ~mask[lsb_mask_index]) begin
|
||||
lsb_mask_index = lsb_mask_index + 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer msb_mask_index (
|
||||
input [C_ADDR_WIDTH-1:0] mask
|
||||
);
|
||||
begin : my_msb_mask_index
|
||||
msb_mask_index = C_ADDR_WIDTH-1;
|
||||
while ((msb_mask_index > 0) && ~mask[msb_mask_index]) begin
|
||||
msb_mask_index = msb_mask_index - 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Local parameters
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
localparam P_ADDR_BIT_MASK = calc_bit_mask(C_REG_ADDR_ARRAY);
|
||||
localparam P_MASK_LSB = lsb_mask_index(P_ADDR_BIT_MASK);
|
||||
localparam P_MASK_MSB = msb_mask_index(P_ADDR_BIT_MASK);
|
||||
localparam P_MASK_WIDTH = P_MASK_MSB - P_MASK_LSB + 1;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Wires/Reg declarations
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
integer i;
|
||||
(* rom_extract = "no" *)
|
||||
reg [C_NUM_REG_WIDTH-1:0] reg_decode_num_i;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN RTL
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
always @(*) begin
|
||||
reg_decode_num_i = {C_NUM_REG_WIDTH{1'b0}};
|
||||
for (i = 1; i < C_NUM_REG; i = i + 1) begin : decode_addr
|
||||
if ((axaddr[P_MASK_MSB:P_MASK_LSB] == C_REG_ADDR_ARRAY[i*C_ADDR_WIDTH+P_MASK_LSB+:P_MASK_WIDTH])
|
||||
&& C_REG_RDWR_ARRAY[i] ) begin
|
||||
reg_decode_num_i = i[C_NUM_REG_WIDTH-1:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign reg_decode_num = reg_decode_num_i;
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user