Added wraparounds and halt_cmplt signal to 50t

Firmware/XDMA/hdl/100t_200t/dso_top.v

@@ -216,7 +216,6 @@ module dso_top
     ddr_ready_cdc <= { ddr_ready_cdc[1:0], init_calib_complete_0};
   assign ddr_ready = ddr_ready_cdc[2];
   
-
   serdes serdes (
 	.rst            (serdes_rst),
 	.adc_lclk_p		(adc_lclk_p),

Firmware/XDMA/hdl/35t_50t/dso_top.v

@@ -77,6 +77,7 @@ module dso_top
 
   wire s2mm_err;
   wire s2mm_halt;
+  wire s2mm_halt_cmplt;
   wire s2mm_wr_xfer_cmplt;
   
   wire fe_sda_buf;
@@ -239,9 +240,11 @@ module dso_top
     .adc_divclk(divclk),
     .s2mm_err(s2mm_err),
     .s2mm_halt(s2mm_halt),
+    .s2mm_halt_cmplt(s2mm_halt_cmplt),
     .s2mm_wr_xfer_cmplt(s2mm_wr_xfer_cmplt),
     .gpio_io_o_0(gpio_io_o_0),
     .gpio2_io_i(gpio2_io_i),
+    .gpio2_io_o_0(gpio2_io_o_0),
     .serdes_ready (serdes_ready),
     .ddr_ready(ddr_ready)
   );
@@ -293,6 +296,7 @@ module dso_top
     .axi_aclk(axi_aclk),
     .axi_aresetn(axi_aresetn),
     .gpio2_io_i(gpio2_io_i),
+    .gpio2_io_o_0(gpio2_io_o_0),
     .gpio_io_o_0(gpio_io_o_0),
     .pcie_clk_n(pcie_clk_n),
     .pcie_clk_p(pcie_clk_p),
@@ -303,6 +307,7 @@ module dso_top
     .pcie_perstn(pcie_perstn),
     .s2mm_err(s2mm_err),
     .s2mm_halt(s2mm_halt),
+    .s2mm_halt_cmplt(s2mm_halt_cmplt),
     .s2mm_wr_xfer_cmplt(s2mm_wr_xfer_cmplt),
     .Vp_Vn_0_v_n(Vp_Vn_0_v_n),
     .Vp_Vn_0_v_p(Vp_Vn_0_v_p),

Firmware/XDMA/output/xdma_prj_50t_full.prm

@@ -8,7 +8,7 @@ Start Address      0x00000000
 End Address        0x007FFFFF
 
 Addr1         Addr2         Date                    File(s)
-0x00000000    0x001854AB    May 11 13:08:37 2024    ./output/xdma_prj_50t_gold.bit
+0x00000000    0x001833CF    Sep 11 21:21:08 2024    ./output/xdma_prj_50t_gold.bit
 0x0023FC00    0x0023FFFF    May 11 13:02:37 2024    ./cfg/timer1_50t.bin
-0x00240000    0x003C54AB    May 11 13:07:58 2024    ./output/xdma_prj_50t.bit
+0x00240000    0x003C33CF    Sep 11 21:20:51 2024    ./output/xdma_prj_50t.bit
 0x00480000    0x0048003B    May 11 13:02:37 2024    ./cfg/timer2_50t.bin

Firmware/XDMA/output/xdma_prj_50t_update.prm

@@ -8,4 +8,4 @@ Start Address      0x00000000
 End Address        0x007FFFFF
 
 Addr1         Addr2         Date                    File(s)
-0x00240000    0x003C54AB    May 11 13:07:58 2024    ./output/xdma_prj_50t.bit
+0x00240000    0x003C33CF    Sep 11 21:20:51 2024    ./output/xdma_prj_50t.bit