Merge pull request #260 from EEVengers/rev5-hw

Rev5 HW WIP

Hardware/Altium/Thunderscope_Rev5/ADC.Harness

@@ -0,0 +1 @@
+ADC LVDS=D4B_N,D4B_P,D4A_N,D4A_P,D3B_N,D3B_P,D3A_N,D3A_P,FCLK_N,FCLK_P,LCLK_N,LCLK_P,D2B_N,D2B_P,D2A_N,D2A_P,D1B_N,D1B_P,D1A_N,D1A_P

Hardware/Altium/Thunderscope_Rev5/FPGA.Harness

@@ -0,0 +1,5 @@
+ADC LVDS=D4B_N,D4B_P,D4A_N,D4A_P,D3B_N,D3B_P,D3A_N,D3A_P,FCLK_N,FCLK_P,LCLK_N,LCLK_P,D2B_N,D2B_P,D2A_N,D2A_P,D1B_N,D1B_P,D1A_N,D1A_P
+M2_X4_RX=PER0_N,PER0_P,PER1_N,PER1_P,PER2_N,PER2_P,PER3_N,PER3_P
+M2_X4_TX=PET0_N,PET0_P,PET1_N,PET1_P,PET2_N,PET2_P,PET3_N,PET3_P
+PCIe_X4_RX=PER0_N,PER0_P,PER1_N,PER1_P,PER2_N,PER2_P,PER3_N,PER3_P
+PCIe_X4_TX=PET0_N,PET0_P,PET1_N,PET1_P,PET2_N,PET2_P,PET3_N,PET3_P

Hardware/Altium/Thunderscope_Rev5/M2_KEY_M.Harness

@@ -0,0 +1,2 @@
+M2_X4_RX=PER0_N,PER0_P,PER1_N,PER1_P,PER2_N,PER2_P,PER3_N,PER3_P
+M2_X4_TX=PET0_N,PET0_P,PET1_N,PET1_P,PET2_N,PET2_P,PET3_N,PET3_P

Hardware/Altium/Thunderscope_Rev5/Managed/Sheets/FC1D1A13-1D8D-4C53-8666-9A4B6D32A5EC/CON_PCIe_X4.Harness

@@ -0,0 +1,2 @@
+PCIe_X4_RX=PER0_N,PER0_P,PER1_N,PER1_P,PER2_N,PER2_P,PER3_N,PER3_P
+PCIe_X4_TX=PET0_N,PET0_P,PET1_N,PET1_P,PET2_N,PET2_P,PET3_N,PET3_P

Hardware/Altium/Thunderscope_Rev5/Thunderscope_Rev5.PrjPCBStructure

@@ -0,0 +1,17 @@
+Record=TopLevelDocument|FileName=Main.SchDoc|SheetNumber=1
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=ADC|SchDesignator=ADC|FileName=ADC.SchDoc|SheetNumber=5|SymbolType=Normal|RawFileName=ADC.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=CH1|SchDesignator=CH1|FileName=FE_Channel.SchDoc|SheetNumber=2|SymbolType=Normal|RawFileName=FE_Channel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=CH2|SchDesignator=CH2|FileName=FE_Channel.SchDoc|SheetNumber=2|SymbolType=Normal|RawFileName=FE_Channel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=CH3|SchDesignator=CH3|FileName=FE_Channel.SchDoc|SheetNumber=2|SymbolType=Normal|RawFileName=FE_Channel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=CH4|SchDesignator=CH4|FileName=FE_Channel.SchDoc|SheetNumber=2|SymbolType=Normal|RawFileName=FE_Channel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=Clock Generator|SchDesignator=Clock Generator|FileName=PLL.SchDoc|SheetNumber=4|SymbolType=Normal|RawFileName=PLL.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=FPGA|SchDesignator=FPGA|FileName=FPGA.SchDoc|SheetNumber=7|SymbolType=Normal|RawFileName=FPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=Front End Trim and Bias|SchDesignator=Front End Trim and Bias|FileName=FE.SchDoc|SheetNumber=3|SymbolType=Normal|RawFileName=FE.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=M.2_Key_M|SchDesignator=M.2_Key_M|FileName=M2_KEY_M.SchDoc|SheetNumber=14|SymbolType=Normal|RawFileName=M2_KEY_M.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=PCIe_X4|SchDesignator=PCIe_X4|FileName=CON_PCIe_X4.SchDoc|SheetNumber=13|SymbolType=Normal|RawFileName=CON_PCIe_X4.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=POWER|SchDesignator=POWER|FileName=PWR.SchDoc|SheetNumber=6|SymbolType=Normal|RawFileName=PWR.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FPGA Configuration|SchDesignator=FPGA Configuration|FileName=FPGA_CFG.SchDoc|SheetNumber=9|SymbolType=Normal|RawFileName=FPGA_CFG.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FPGA IO Banks|SchDesignator=FPGA IO Banks|FileName=FPGA_Bank_IO.SchDoc|SheetNumber=8|SymbolType=Normal|RawFileName=FPGA_Bank_IO.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FPGA Power|SchDesignator=FPGA Power|FileName=FPGA_PWR.SchDoc|SheetNumber=11|SymbolType=Normal|RawFileName=FPGA_PWR.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FPGA Transceivers|SchDesignator=FPGA Transceivers|FileName=FPGA_MGT.SchDoc|SheetNumber=10|SymbolType=Normal|RawFileName=FPGA_MGT.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Voltage Regulation|SchDesignator=Voltage Regulation|FileName=FPGA_REG.SchDoc|SheetNumber=12|SymbolType=Normal|RawFileName=FPGA_REG.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=