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Added M.2 Interposer and PCB End Caps

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Aleksa Bjelogrlic 2024-02-21 20:51:58 -05:00
parent 05e250b223
commit 34fdd7ebb2
74 changed files with 92220 additions and 0 deletions

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Hardware/Altium/End_Caps/End_Caps.PrjPcb Normal file
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Hardware/Altium/End_Caps/Front.PcbDoc
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Hardware/Altium/End_Caps/Project Outputs for End_Caps/Design Rule Check - Back.drc Normal file
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Protel Design System Design Rule Check
PCB File : C:\Users\Aleksa\Documents\Altium\End_Caps\Back.PcbDoc
Date : 2022-10-30
Time : 10:50:45 PM
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<body onload=""><img ALT="Altium" src="
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<td class="front_matter_column1">Date:</td>
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<td class="front_matter_column3">2022-10-30</td>
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<td class="front_matter_column3">10:50:45 PM</td>
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<td class="front_matter_column3"><a href="file:///C:\Users\Aleksa\Documents\Altium\End_Caps\Back.PcbDoc" class="file"><acronym title="C:\Users\Aleksa\Documents\Altium\End_Caps\Back.PcbDoc">C:\Users\Aleksa\Documents\Altium\End_Caps\Back.PcbDoc</acronym></a></td>
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51
Hardware/Altium/End_Caps/Project Outputs for End_Caps/Design Rule Check - Front.drc Normal file
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@ -0,0 +1,51 @@
Protel Design System Design Rule Check
PCB File : C:\Users\Aleksa\Documents\Altium\End_Caps\Front.PcbDoc
Date : 2022-10-30
Time : 10:50:18 PM
Processing Rule : Clearance Constraint (Gap=0.254mm) (All),(All)
Rule Violations :0
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Rule Violations :0
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Rule Violations :0
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Rule Violations :0
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Rule Violations :0
Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=15mm) (All)
Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=0mm) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.2mm) (All),(All)
Rule Violations :0
Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Rule Violations :0
Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All)
Rule Violations :0
Processing Rule : Net Antennae (Tolerance=0mm) (All)
Rule Violations :0
Processing Rule : Board Clearance Constraint (Gap=0mm) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Violations Detected : 0
Waived Violations : 0
Time Elapsed : 00:00:01

328
Hardware/Altium/End_Caps/Project Outputs for End_Caps/Design Rule Check - Front.html Normal file
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<body onload=""><img ALT="Altium" src="
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<td class="column1">
<table class="front_matter">
<tr class="front_matter">
<td class="front_matter_column1">Date:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">2022-10-30</td>
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<td class="front_matter_column1">Time:</td>
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<td class="front_matter_column3">10:50:18 PM</td>
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<tr class="front_matter">
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<td class="front_matter_column3"><a href="file:///C:\Users\Aleksa\Documents\Altium\End_Caps\Front.PcbDoc" class="file"><acronym title="C:\Users\Aleksa\Documents\Altium\End_Caps\Front.PcbDoc">C:\Users\Aleksa\Documents\Altium\End_Caps\Front.PcbDoc</acronym></a></td>
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<td class="DRC_summary_header_col3">0</td></tr>
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<th class="column1">Warnings</th>
<th class="column2">Count</th>
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<td style="font-weight : bold; text-align : right" class="column1">Total</td>
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<th class="column1">Rule Violations</th>
<th class="column2">Count</th>
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<td class="column2">0</td>
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<td class="column2">0</td>
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<td class="column1"><a href="#IDRUKOIRFKF4NJCBFHWJCSIHOUEDIGELLKLB5MRHCTASERB1NPUD5F">Width Constraint (Min=0.254mm) (Max=0.254mm) (Preferred=0.254mm) (All)</a></td>
<td class="column2">0</td>
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<td class="column2">0</td>
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<td class="column2">0</td>
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<td class="column2">0</td>
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<td style="font-weight : bold; text-align : right" class="column1">Total</td>
<td style="font-weight : bold" class="column2">0</td>
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54
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M02*

16
Hardware/Altium/End_Caps/Project Outputs for End_Caps/Gerber/Back.GBO Normal file
View File

@ -0,0 +1,16 @@
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G04 #@! TF.GenerationSoftware,Altium Limited,Altium Designer,22.4.2 (48)*
G04*
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G70*
G04*
G04 #@! TF.SameCoordinates,D0525307-FA06-41FD-84B0-9E93535F59E6*
G04*
G04*
G04 #@! TF.FilePolarity,Positive*
G04*
G01*
G75*
M02*

34
Hardware/Altium/End_Caps/Project Outputs for End_Caps/Gerber/Back.GBS Normal file
View File

@ -0,0 +1,34 @@
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G04*
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G70*
G04*
G04 #@! TF.SameCoordinates,D0525307-FA06-41FD-84B0-9E93535F59E6*
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G04*
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G01*
G75*
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D10*
X201772Y21949D02*
D03*
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D03*
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X15748Y104331D02*
D03*
Y15748D02*
D03*
X389764D02*
D03*
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D03*
M02*

87
Hardware/Altium/End_Caps/Project Outputs for End_Caps/Gerber/Back.GKO Normal file
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G04*
G04 Layer_Color=16711935*
%FSLAX25Y25*%
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G70*
G04*
G04 #@! TF.SameCoordinates,D0525307-FA06-41FD-84B0-9E93535F59E6*
G04*
G04*
G04 #@! TF.FilePolarity,Positive*
G04*
G01*
G75*
%ADD11C,0.00050*%
D11*
X15709Y120079D02*
G03*
X-0Y104370I-0J-15709D01*
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M02*

410
Hardware/Altium/End_Caps/Project Outputs for End_Caps/Gerber/Back.GTL Normal file
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G04*
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G04 Layer_Color=255*
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G70*
G04*
G04 #@! TF.SameCoordinates,D0525307-FA06-41FD-84B0-9E93535F59E6*
G04*
G04*
G04 #@! TF.FilePolarity,Positive*
G04*
G01*
G75*
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16
Hardware/Altium/End_Caps/Project Outputs for End_Caps/Gerber/Front.GTO Normal file
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2478
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