AllSpiceMirrors/ThunderScope
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LVDS Routing WIP

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Also placed PCIe stuffing options
This commit is contained in:
Aleksa Bjelogrlic 2025-03-25 00:40:45 -04:00
parent bac0f98dd9
commit 4e97e82a2f
9 changed files with 22259 additions and 17148 deletions

Hardware/KiCad/Thunderscope_Rev5/FPGA_Bank_IO.kicad_sch
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Hardware/KiCad/Thunderscope_Rev5/FPGA_CFG_MGT.kicad_sch
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Hardware/KiCad/Thunderscope_Rev5/FPGA_PWR.kicad_sch
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LOADING design file

Hardware/KiCad/Thunderscope_Rev5/FPGA_VREG.kicad_sch
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LOADING design file

Hardware/KiCad/Thunderscope_Rev5/PLL.kicad_sch
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2
Hardware/KiCad/Thunderscope_Rev5/Thunderscope_Rev5.kicad_dru
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@ -51,7 +51,7 @@
(rule LVDS_ADC_Outer
(layer outer)
(condition "A.hasNetclass('LVDS_ADC')")
(constraint diff_pair_gap (min 0.13022mm)(opt 0.13022mm)(max 0.13022mm))
(constraint diff_pair_gap (opt 0.13022mm))
(constraint track_width (min 0.127mm)(opt 0.127mm)(max 0.127mm)))
(rule "LVDS_ADC_Skew"
(condition "A.hasNetclass('LVDS_ADC')")

Hardware/KiCad/Thunderscope_Rev5/Thunderscope_Rev5.kicad_pcb
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LOADING design file

50
Hardware/KiCad/Thunderscope_Rev5/Thunderscope_Rev5.kicad_prl
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@ -7,9 +7,7 @@
"FE_100Z_Diff",
"FE_50Z",
"LVDS",
"LVDS_ADC",
"LVDS_SYNC",
"LVDS_USRIO",
"PCIe",
"PWR"
],
@ -23,8 +21,6 @@
"/FPGA/MGT_TX2_P",
"/FPGA/MGT_TX3_N",
"/FPGA/MGT_TX3_P",
"/ADC/ADC_CLK_P",
"/ADC/ADC_CLK_N",
"Net-(U18H-VCCADC_0)",
"/CH1/ATTEN_50X_R",
"/CH2/ATTEN_50X_R",
@ -123,26 +119,6 @@
"Net-(U18D-DONE_0)",
"GND",
"+5V",
"/ADC/D3B_P",
"/ADC/D2A_P",
"/ADC/D1B_N",
"/ADC/LCLK_N",
"/ADC/D2B_N",
"/ADC/D1A_N",
"/ADC/D3A_N",
"/ADC/D3A_P",
"/ADC/FCLK_N",
"/ADC/D2B_P",
"/ADC/D1A_P",
"/ADC/D2A_N",
"/ADC/D4B_P",
"/ADC/D3B_N",
"/ADC/D1B_P",
"/ADC/D4A_N",
"/ADC/FCLK_P",
"/ADC/LCLK_P",
"/ADC/D4A_P",
"/ADC/D4B_N",
"/FPGA/FPGA IO Banks/FE_PG",
"/FPGA/FPGA IO Banks/QSPI_DQ2",
"/FPGA/FPGA IO Banks/QSPI_DQ0",
@ -189,30 +165,6 @@
"/TS-USB4 Components/M2_PET3_P",
"/TS-USB4 Components/M2_PET3_N",
"/TS-USB4 Components/M2_PET2_N",
"/FPGA/USRIO_9_N",
"/FPGA/USRIO_3_P",
"/FPGA/USRIO_4_N",
"/FPGA/USRIO_5_P",
"/FPGA/USRIO_10_N",
"/FPGA/USRIO_10_P",
"/FPGA/USRIO_3_N",
"/FPGA/USRIO_8_N",
"/FPGA/USRIO_7_N",
"/FPGA/USRIO_5_N",
"/FPGA/USRIO_8_P",
"/FPGA/USRIO_12_N",
"/FPGA/USRIO_9_P",
"/FPGA/USRIO_11_N",
"/FPGA/USRIO_2_P",
"/FPGA/USRIO_1_P",
"/FPGA/USRIO_12_P",
"/FPGA/USRIO_6_N",
"/FPGA/USRIO_4_P",
"/FPGA/USRIO_11_P",
"/FPGA/USRIO_2_N",
"/FPGA/USRIO_7_P",
"/FPGA/USRIO_6_P",
"/FPGA/USRIO_1_N",
"/SPRING",
"/TS-PCIe Components/PCIe_PET3_N",
"/TS-PCIe Components/PCIe_PET1_P",
@ -290,7 +242,7 @@
"lockedItems": false,
"otherItems": true,
"pads": true,
"text": true,
"text": false,
"tracks": true,
"vias": true,
"zones": true

9
Hardware/KiCad/Thunderscope_Rev5/Thunderscope_Rev5.kicad_pro
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@ -789,13 +789,14 @@
"wire_width": 6
},
{
"clearance": 0.127,
"name": "FE_100Z_Diff",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 4,
"schematic_color": "rgba(0, 0, 0, 0.000)"
},
{
"clearance": 0.15,
"clearance": 0.127,
"name": "FE_50Z",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 6,
@ -805,31 +806,35 @@
"via_drill": 1.0
},
{
"clearance": 0.127,
"name": "LVDS_ADC",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 1,
"schematic_color": "rgba(0, 0, 0, 0.000)"
},
{
"clearance": 0.127,
"name": "LVDS_SYNC",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 3,
"schematic_color": "rgba(0, 0, 0, 0.000)"
},
{
"clearance": 0.127,
"name": "LVDS_USRIO",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 2,
"schematic_color": "rgba(0, 0, 0, 0.000)"
},
{
"clearance": 0.127,
"name": "PCIe",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 0,
"schematic_color": "rgba(0, 0, 0, 0.000)"
},
{
"clearance": 0.15,
"clearance": 0.127,
"name": "PWR",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 5,