AllSpiceMirrors/ThunderScope
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Removed old custom module gateware

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This commit is contained in:
Aleksa Bjelogrlic 2024-05-11 16:06:48 -04:00
parent fa3d4bb0d8
commit 5401d8af3a
555 changed files with 0 additions and 3095968 deletions
Firmware/XDMA/FPGA_Module_Rev2_50T
FPGA_Module_Rev2_50T.bin
FPGA_Module_Rev2_50T.ip_user_files
README.txt
ip
clk_wiz_0
clk_wiz_0.veoclk_wiz_0_sim_netlist.vclk_wiz_0_sim_netlist.vhdlclk_wiz_0_stub.vclk_wiz_0_stub.vhdl
fifo_generator_0
fifo_generator_0.veofifo_generator_0.vhofifo_generator_0_stub.vfifo_generator_0_stub.vhdl
ipstatic
hdl
fifo_generator_v13_2_rfs.vfifo_generator_v13_2_rfs.vhd
simulation
fifo_generator_vlog_beh.v
mem_init_files
axi_clock_converter.haxi_crossbar.haxi_data_fifo.haxi_dwidth_converter.hbd_48ac_one_0.hdesign_1_auto_cc_0.hdesign_1_auto_cc_0_sc.hdesign_1_auto_us_df_0.hdesign_1_auto_us_df_0_sc.hdesign_1_auto_us_df_1.hdesign_1_auto_us_df_1_sc.hdesign_1_m00_data_fifo_0.hdesign_1_m00_data_fifo_0_sc.hdesign_1_smartconnect_0_0.hdesign_1_smartconnect_0_0_sc.hdesign_1_xbar_0.hdesign_1_xbar_0_sc.hdesign_1_xbar_1.hdesign_1_xbar_1_sc.hdesign_1_xlconstant_0_0.hdesign_1_xlconstant_0_2.hdesign_1_xlconstant_0_3.hmig_a.prjmig_b.prjsc_xtlm_design_1_smartconnect_0_0.memsmartconnect.cxxsmartconnect.hsmartconnect_xtlm.cxxsmartconnect_xtlm.hsmartconnect_xtlm_impl.hsys_clk_gen_ps_v.txtxlconstant_v1_1_7.h
FPGA_Module_Rev2_50T.srcs
constrs_1
imports/new
module_bitgen.xdcmodule_io.xdc
new
timing.xdc
sources_1
bd/design_1
design_1.bddesign_1.bxmldesign_1_ooc.xdc
hdl
design_1_wrapper.v
hw_handoff
design_1.hwhdesign_1_bd.tcl
ip
design_1_axi_clock_converter_0_0
design_1_axi_clock_converter_0_0.dcpdesign_1_axi_clock_converter_0_0.xcidesign_1_axi_clock_converter_0_0.xmldesign_1_axi_clock_converter_0_0_clocks.xdcdesign_1_axi_clock_converter_0_0_ooc.xdcdesign_1_axi_clock_converter_0_0_sim_netlist.vdesign_1_axi_clock_converter_0_0_sim_netlist.vhdldesign_1_axi_clock_converter_0_0_stub.vdesign_1_axi_clock_converter_0_0_stub.vhdl
sim
design_1_axi_clock_converter_0_0.cppdesign_1_axi_clock_converter_0_0.hdesign_1_axi_clock_converter_0_0.vdesign_1_axi_clock_converter_0_0_sc.cppdesign_1_axi_clock_converter_0_0_sc.hdesign_1_axi_clock_converter_0_0_stub.sv
synth
design_1_axi_clock_converter_0_0.v
sysc
axi_clock_converter.cppaxi_clock_converter.h
design_1_axi_crossbar_0_0
design_1_axi_crossbar_0_0.dcpdesign_1_axi_crossbar_0_0.xcidesign_1_axi_crossbar_0_0.xmldesign_1_axi_crossbar_0_0_ooc.xdcdesign_1_axi_crossbar_0_0_sim_netlist.vdesign_1_axi_crossbar_0_0_sim_netlist.vhdldesign_1_axi_crossbar_0_0_stub.vdesign_1_axi_crossbar_0_0_stub.vhdl
sim
design_1_axi_crossbar_0_0.cppdesign_1_axi_crossbar_0_0.hdesign_1_axi_crossbar_0_0.vdesign_1_axi_crossbar_0_0_sc.cppdesign_1_axi_crossbar_0_0_sc.hdesign_1_axi_crossbar_0_0_stub.sv
src
axi_crossbar.cppaxi_crossbar.h
synth
design_1_axi_crossbar_0_0.v
design_1_axi_crossbar_0_1
design_1_axi_crossbar_0_1.dcpdesign_1_axi_crossbar_0_1.xcidesign_1_axi_crossbar_0_1.xmldesign_1_axi_crossbar_0_1_ooc.xdcdesign_1_axi_crossbar_0_1_sim_netlist.vdesign_1_axi_crossbar_0_1_sim_netlist.vhdldesign_1_axi_crossbar_0_1_stub.vdesign_1_axi_crossbar_0_1_stub.vhdl
sim
design_1_axi_crossbar_0_1.cppdesign_1_axi_crossbar_0_1.hdesign_1_axi_crossbar_0_1.vdesign_1_axi_crossbar_0_1_sc.cppdesign_1_axi_crossbar_0_1_sc.hdesign_1_axi_crossbar_0_1_stub.sv
src
axi_crossbar.cppaxi_crossbar.h
synth
design_1_axi_crossbar_0_1.v
design_1_axi_datamover_0_0
design_1_axi_datamover_0_0.dcpdesign_1_axi_datamover_0_0.xcidesign_1_axi_datamover_0_0.xdcdesign_1_axi_datamover_0_0.xmldesign_1_axi_datamover_0_0_clocks.xdcdesign_1_axi_datamover_0_0_ooc.xdcdesign_1_axi_datamover_0_0_sim_netlist.vdesign_1_axi_datamover_0_0_sim_netlist.vhdldesign_1_axi_datamover_0_0_stub.vdesign_1_axi_datamover_0_0_stub.vhdl
sim
design_1_axi_datamover_0_0.vhd
synth
design_1_axi_datamover_0_0.vhd
design_1_axi_dwidth_converter_0_0
design_1_axi_dwidth_converter_0_0.dcpdesign_1_axi_dwidth_converter_0_0.xcidesign_1_axi_dwidth_converter_0_0.xmldesign_1_axi_dwidth_converter_0_0_clocks.xdcdesign_1_axi_dwidth_converter_0_0_ooc.xdcdesign_1_axi_dwidth_converter_0_0_sim_netlist.vdesign_1_axi_dwidth_converter_0_0_sim_netlist.vhdldesign_1_axi_dwidth_converter_0_0_stub.vdesign_1_axi_dwidth_converter_0_0_stub.vhdl
sim
design_1_axi_dwidth_converter_0_0.cppdesign_1_axi_dwidth_converter_0_0.hdesign_1_axi_dwidth_converter_0_0.vdesign_1_axi_dwidth_converter_0_0_sc.cppdesign_1_axi_dwidth_converter_0_0_sc.hdesign_1_axi_dwidth_converter_0_0_stub.sv
src
axi_dwidth_converter.cppaxi_dwidth_converter.h
synth
design_1_axi_dwidth_converter_0_0.v
design_1_axi_fifo_mm_s_0_0
design_1_axi_fifo_mm_s_0_0.dcpdesign_1_axi_fifo_mm_s_0_0.xcidesign_1_axi_fifo_mm_s_0_0.xmldesign_1_axi_fifo_mm_s_0_0_ooc.xdcdesign_1_axi_fifo_mm_s_0_0_sim_netlist.vdesign_1_axi_fifo_mm_s_0_0_sim_netlist.vhdldesign_1_axi_fifo_mm_s_0_0_stub.vdesign_1_axi_fifo_mm_s_0_0_stub.vhdl
sim
design_1_axi_fifo_mm_s_0_0.vhd
synth
design_1_axi_fifo_mm_s_0_0.vhd
design_1_axi_gpio_0_1
design_1_axi_gpio_0_1.dcpdesign_1_axi_gpio_0_1.xcidesign_1_axi_gpio_0_1.xdcdesign_1_axi_gpio_0_1.xmldesign_1_axi_gpio_0_1_board.xdcdesign_1_axi_gpio_0_1_ooc.xdcdesign_1_axi_gpio_0_1_sim_netlist.vdesign_1_axi_gpio_0_1_sim_netlist.vhdldesign_1_axi_gpio_0_1_stub.vdesign_1_axi_gpio_0_1_stub.vhdl
sim
design_1_axi_gpio_0_1.vhd
synth
design_1_axi_gpio_0_1.vhd
design_1_clk_wiz_0_0
design_1_clk_wiz_0_0.dcpdesign_1_clk_wiz_0_0.vdesign_1_clk_wiz_0_0.xcidesign_1_clk_wiz_0_0.xdcdesign_1_clk_wiz_0_0.xmldesign_1_clk_wiz_0_0_board.xdcdesign_1_clk_wiz_0_0_clk_wiz.vdesign_1_clk_wiz_0_0_late.xdcdesign_1_clk_wiz_0_0_ooc.xdcdesign_1_clk_wiz_0_0_sim_netlist.vdesign_1_clk_wiz_0_0_sim_netlist.vhdldesign_1_clk_wiz_0_0_stub.vdesign_1_clk_wiz_0_0_stub.vhdl
design_1_mig_7series_0_0
design_1_mig_7series_0_0.dcpdesign_1_mig_7series_0_0.veodesign_1_mig_7series_0_0.xcidesign_1_mig_7series_0_0.xml
design_1_mig_7series_0_0
datasheet.txt
docs
phy_only_support_readme.txt
example_design
par
example_top.xdcreadme.txt
rtl
example_top.v
traffic_gen
mig_7series_v4_2_axi4_tg.vmig_7series_v4_2_axi4_wrapper.vmig_7series_v4_2_cmd_prbs_gen_axi.vmig_7series_v4_2_data_gen_chk.vmig_7series_v4_2_tg.v
sim
ddr3_model.svddr3_model_parameters.vhies_run.shreadme.txtsim.dosim_tb_top.vvcs_run.shwiredly.vxsim_files.prjxsim_options.tclxsim_run.bat
mig.prj
user_design
constraints
design_1_mig_7series_0_0.xdcdesign_1_mig_7series_0_0_ooc.xdc
rtl
axi
mig_7series_v4_2_axi_ctrl_addr_decode.vmig_7series_v4_2_axi_ctrl_read.vmig_7series_v4_2_axi_ctrl_reg.vmig_7series_v4_2_axi_ctrl_reg_bank.vmig_7series_v4_2_axi_ctrl_top.vmig_7series_v4_2_axi_ctrl_write.vmig_7series_v4_2_axi_mc.vmig_7series_v4_2_axi_mc_ar_channel.vmig_7series_v4_2_axi_mc_aw_channel.vmig_7series_v4_2_axi_mc_b_channel.vmig_7series_v4_2_axi_mc_cmd_arbiter.vmig_7series_v4_2_axi_mc_cmd_fsm.vmig_7series_v4_2_axi_mc_cmd_translator.vmig_7series_v4_2_axi_mc_fifo.vmig_7series_v4_2_axi_mc_incr_cmd.vmig_7series_v4_2_axi_mc_r_channel.vmig_7series_v4_2_axi_mc_simple_fifo.vmig_7series_v4_2_axi_mc_w_channel.vmig_7series_v4_2_axi_mc_wr_cmd_fsm.vmig_7series_v4_2_axi_mc_wrap_cmd.vmig_7series_v4_2_ddr_a_upsizer.vmig_7series_v4_2_ddr_axi_register_slice.vmig_7series_v4_2_ddr_axi_upsizer.vmig_7series_v4_2_ddr_axic_register_slice.vmig_7series_v4_2_ddr_carry_and.vmig_7series_v4_2_ddr_carry_latch_and.vmig_7series_v4_2_ddr_carry_latch_or.vmig_7series_v4_2_ddr_carry_or.vmig_7series_v4_2_ddr_command_fifo.vmig_7series_v4_2_ddr_comparator.vmig_7series_v4_2_ddr_comparator_sel.vmig_7series_v4_2_ddr_comparator_sel_static.vmig_7series_v4_2_ddr_r_upsizer.vmig_7series_v4_2_ddr_w_upsizer.v
clocking
mig_7series_v4_2_clk_ibuf.vmig_7series_v4_2_infrastructure.vmig_7series_v4_2_iodelay_ctrl.vmig_7series_v4_2_tempmon.v
controller
mig_7series_v4_2_arb_mux.vmig_7series_v4_2_arb_row_col.vmig_7series_v4_2_arb_select.vmig_7series_v4_2_bank_cntrl.vmig_7series_v4_2_bank_common.vmig_7series_v4_2_bank_compare.vmig_7series_v4_2_bank_mach.vmig_7series_v4_2_bank_queue.vmig_7series_v4_2_bank_state.vmig_7series_v4_2_col_mach.vmig_7series_v4_2_mc.vmig_7series_v4_2_rank_cntrl.vmig_7series_v4_2_rank_common.vmig_7series_v4_2_rank_mach.vmig_7series_v4_2_round_robin_arb.v
design_1_mig_7series_0_0.vdesign_1_mig_7series_0_0_mig.vdesign_1_mig_7series_0_0_mig_sim.v
ecc
mig_7series_v4_2_ecc_buf.vmig_7series_v4_2_ecc_dec_fix.vmig_7series_v4_2_ecc_gen.vmig_7series_v4_2_ecc_merge_enc.vmig_7series_v4_2_fi_xor.v
ip_top
mig_7series_v4_2_mem_intfc.vmig_7series_v4_2_memc_ui_top_axi.v
phy
mig_7series_v4_2_ddr_byte_group_io.vmig_7series_v4_2_ddr_byte_lane.vmig_7series_v4_2_ddr_calib_top.vmig_7series_v4_2_ddr_if_post_fifo.vmig_7series_v4_2_ddr_mc_phy.vmig_7series_v4_2_ddr_mc_phy_wrapper.vmig_7series_v4_2_ddr_of_pre_fifo.vmig_7series_v4_2_ddr_phy_4lanes.vmig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.vmig_7series_v4_2_ddr_phy_dqs_found_cal.vmig_7series_v4_2_ddr_phy_dqs_found_cal_hr.vmig_7series_v4_2_ddr_phy_init.vmig_7series_v4_2_ddr_phy_ocd_cntlr.vmig_7series_v4_2_ddr_phy_ocd_data.vmig_7series_v4_2_ddr_phy_ocd_edge.vmig_7series_v4_2_ddr_phy_ocd_lim.vmig_7series_v4_2_ddr_phy_ocd_mux.vmig_7series_v4_2_ddr_phy_ocd_po_cntlr.vmig_7series_v4_2_ddr_phy_ocd_samp.vmig_7series_v4_2_ddr_phy_oclkdelay_cal.vmig_7series_v4_2_ddr_phy_prbs_rdlvl.vmig_7series_v4_2_ddr_phy_rdlvl.vmig_7series_v4_2_ddr_phy_tempmon.vmig_7series_v4_2_ddr_phy_top.vmig_7series_v4_2_ddr_phy_wrcal.vmig_7series_v4_2_ddr_phy_wrlvl.vmig_7series_v4_2_ddr_phy_wrlvl_off_delay.vmig_7series_v4_2_ddr_prbs_gen.vmig_7series_v4_2_ddr_skip_calib_tap.vmig_7series_v4_2_poc_cc.vmig_7series_v4_2_poc_edge_store.vmig_7series_v4_2_poc_meta.vmig_7series_v4_2_poc_pd.vmig_7series_v4_2_poc_tap_base.vmig_7series_v4_2_poc_top.v
ui
mig_7series_v4_2_ui_cmd.vmig_7series_v4_2_ui_rd_data.vmig_7series_v4_2_ui_top.vmig_7series_v4_2_ui_wr_data.v
design_1_mig_7series_0_0_sim_netlist.vdesign_1_mig_7series_0_0_sim_netlist.vhdldesign_1_mig_7series_0_0_stub.vdesign_1_mig_7series_0_0_stub.vhdldesign_1_mig_7series_0_0_xmdf.tclmig_a.prjmig_b.prjxil_txt.inxil_txt.out
design_1_util_ds_buf_0_0
design_1_util_ds_buf_0_0.dcpdesign_1_util_ds_buf_0_0.xcidesign_1_util_ds_buf_0_0.xmldesign_1_util_ds_buf_0_0_board.xdcdesign_1_util_ds_buf_0_0_ooc.xdcdesign_1_util_ds_buf_0_0_sim_netlist.vdesign_1_util_ds_buf_0_0_sim_netlist.vhdldesign_1_util_ds_buf_0_0_stub.vdesign_1_util_ds_buf_0_0_stub.vhdl
sim
design_1_util_ds_buf_0_0.vhd
synth
design_1_util_ds_buf_0_0.vhd
util_ds_buf.vhd
design_1_util_vector_logic_0_0
design_1_util_vector_logic_0_0.dcpdesign_1_util_vector_logic_0_0.xcidesign_1_util_vector_logic_0_0.xmldesign_1_util_vector_logic_0_0_sim_netlist.vdesign_1_util_vector_logic_0_0_sim_netlist.vhdldesign_1_util_vector_logic_0_0_stub.vdesign_1_util_vector_logic_0_0_stub.vhdl
sim
design_1_util_vector_logic_0_0.v
synth
design_1_util_vector_logic_0_0.v
design_1_xdma_0_0
design_1_xdma_0_0.dcpdesign_1_xdma_0_0.xcidesign_1_xdma_0_0.xmldesign_1_xdma_0_0_board.xdcdesign_1_xdma_0_0_sim_netlist.vdesign_1_xdma_0_0_sim_netlist.vhdldesign_1_xdma_0_0_stub.vdesign_1_xdma_0_0_stub.vhdl
ip_0
design_1_xdma_0_0_pcie2_ip.xcidesign_1_xdma_0_0_pcie2_ip.xml
sim
design_1_xdma_0_0_pcie2_ip.v
source
design_1_xdma_0_0_pcie2_ip-PCIE_X0Y0.xdcdesign_1_xdma_0_0_pcie2_ip_axi_basic_rx.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_rx_null_gen.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_rx_pipeline.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_top.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_tx.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_tx_pipeline.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_tx_thrtl_ctl.vdesign_1_xdma_0_0_pcie2_ip_core_top.vdesign_1_xdma_0_0_pcie2_ip_gt_common.vdesign_1_xdma_0_0_pcie2_ip_gt_rx_valid_filter_7x.vdesign_1_xdma_0_0_pcie2_ip_gt_top.vdesign_1_xdma_0_0_pcie2_ip_gt_wrapper.vdesign_1_xdma_0_0_pcie2_ip_gtp_cpllpd_ovrd.vdesign_1_xdma_0_0_pcie2_ip_gtp_pipe_drp.vdesign_1_xdma_0_0_pcie2_ip_gtp_pipe_rate.vdesign_1_xdma_0_0_pcie2_ip_gtp_pipe_reset.vdesign_1_xdma_0_0_pcie2_ip_gtx_cpllpd_ovrd.vdesign_1_xdma_0_0_pcie2_ip_pcie2_top.vdesign_1_xdma_0_0_pcie2_ip_pcie_7x.vdesign_1_xdma_0_0_pcie2_ip_pcie_bram_7x.vdesign_1_xdma_0_0_pcie2_ip_pcie_bram_top_7x.vdesign_1_xdma_0_0_pcie2_ip_pcie_brams_7x.vdesign_1_xdma_0_0_pcie2_ip_pcie_pipe_lane.vdesign_1_xdma_0_0_pcie2_ip_pcie_pipe_misc.vdesign_1_xdma_0_0_pcie2_ip_pcie_pipe_pipeline.vdesign_1_xdma_0_0_pcie2_ip_pcie_top.vdesign_1_xdma_0_0_pcie2_ip_pipe_clock.vdesign_1_xdma_0_0_pcie2_ip_pipe_drp.vdesign_1_xdma_0_0_pcie2_ip_pipe_eq.vdesign_1_xdma_0_0_pcie2_ip_pipe_rate.vdesign_1_xdma_0_0_pcie2_ip_pipe_reset.vdesign_1_xdma_0_0_pcie2_ip_pipe_sync.vdesign_1_xdma_0_0_pcie2_ip_pipe_user.vdesign_1_xdma_0_0_pcie2_ip_pipe_wrapper.vdesign_1_xdma_0_0_pcie2_ip_qpll_drp.vdesign_1_xdma_0_0_pcie2_ip_qpll_reset.vdesign_1_xdma_0_0_pcie2_ip_qpll_wrapper.vdesign_1_xdma_0_0_pcie2_ip_rxeq_scan.v
synth
design_1_xdma_0_0_pcie2_ip.vdesign_1_xdma_0_0_pcie2_ip_ooc.xdc
sys_clk_gen_ps_v.txt
ip_1
sim
xdma_v4_1_6_blk_mem_64_reg_be.v
synth
xdma_v4_1_6_blk_mem_64_reg_be.vhd
xdma_v4_1_6_blk_mem_64_reg_be.xcixdma_v4_1_6_blk_mem_64_reg_be.xmlxdma_v4_1_6_blk_mem_64_reg_be_ooc.xdc
ip_2
sim
xdma_v4_1_6_blk_mem_64_noreg_be.v
synth
xdma_v4_1_6_blk_mem_64_noreg_be.vhd
xdma_v4_1_6_blk_mem_64_noreg_be.xcixdma_v4_1_6_blk_mem_64_noreg_be.xmlxdma_v4_1_6_blk_mem_64_noreg_be_ooc.xdc
ip_3
pcie2_fifo_generator_dma_cpl.xcipcie2_fifo_generator_dma_cpl.xdcpcie2_fifo_generator_dma_cpl.xml
sim
pcie2_fifo_generator_dma_cpl.v
synth
pcie2_fifo_generator_dma_cpl.vhd
ip_4
pcie2_fifo_generator_tgt_brdg.xcipcie2_fifo_generator_tgt_brdg.xdcpcie2_fifo_generator_tgt_brdg.xml
sim
pcie2_fifo_generator_tgt_brdg.v
synth
pcie2_fifo_generator_tgt_brdg.vhd
sim
design_1_xdma_0_0.sv
source
design_1_xdma_0_0_pcie3_7vx_ip.xdc
synth
design_1_xdma_0_0.svdesign_1_xdma_0_0_ooc.xdc
xdma_v4_1/hdl/verilog
design_1_xdma_0_0_axi_stream_intf.svdesign_1_xdma_0_0_cfg_sideband.svdesign_1_xdma_0_0_core_top.svdesign_1_xdma_0_0_dma_bram_wrap.svdesign_1_xdma_0_0_dma_bram_wrap_1024.svdesign_1_xdma_0_0_dma_bram_wrap_2048.svdesign_1_xdma_0_0_dma_cpl.svdesign_1_xdma_0_0_dma_req.svdesign_1_xdma_0_0_pcie2_to_pcie3_wrapper.svdesign_1_xdma_0_0_rx_demux.svdesign_1_xdma_0_0_rx_destraddler.svdesign_1_xdma_0_0_tgt_cpl.svdesign_1_xdma_0_0_tgt_req.svdesign_1_xdma_0_0_tx_mux.sv
design_1_xlconstant_0_0
design_1_xlconstant_0_0.xcidesign_1_xlconstant_0_0.xml
sim
design_1_xlconstant_0_0.cppdesign_1_xlconstant_0_0.hdesign_1_xlconstant_0_0.vdesign_1_xlconstant_0_0_stub.svxlconstant_v1_1_7.h
synth
design_1_xlconstant_0_0.v
design_1_xlconstant_0_2
design_1_xlconstant_0_2.xcidesign_1_xlconstant_0_2.xml
sim
design_1_xlconstant_0_2.cppdesign_1_xlconstant_0_2.hdesign_1_xlconstant_0_2.vdesign_1_xlconstant_0_2_stub.svxlconstant_v1_1_7.h
synth
design_1_xlconstant_0_2.v
design_1_xlconstant_0_3
design_1_xlconstant_0_3.xcidesign_1_xlconstant_0_3.xml
sim
design_1_xlconstant_0_3.cppdesign_1_xlconstant_0_3.hdesign_1_xlconstant_0_3.vdesign_1_xlconstant_0_3_stub.svxlconstant_v1_1_7.h
synth
design_1_xlconstant_0_3.v
ipshared
0513/hdl
lib_pkg_v1_0_rfs.vhd
07be/hdl
axi_dwidth_converter_v2_1_vl_rfs.vaxi_dwidth_converter_v2_1_vlsyn_rfs.v
2137/hdl
util_vector_logic_v2_0_vl_rfs.v
2751/hdl
blk_mem_gen_v8_3_vhsyn_rfs.vhd
276e
hdl
fifo_generator_v13_2_rfs.vfifo_generator_v13_2_rfs.vhdfifo_generator_v13_2_vhsyn_rfs.vhd
simulation
fifo_generator_vlog_beh.v
2985
hdl
blk_mem_gen_v8_4_vhsyn_rfs.vhd
simulation
blk_mem_gen_v8_4.v
2ef9/hdl
axi_register_slice_v2_1_vl_rfs.v
47c9/hdl
axi_data_fifo_v2_1_vl_rfs.v
51ce/hdl
lib_srl_fifo_v1_0_rfs.vhd
5bfc/hdl
axi_fifo_mm_s_v4_2_rfs.vhd
66ea/hdl
axi_lite_ipif_v3_0_vh_rfs.vhd
7589/hdl
axi_clock_converter_v2_1_vl_rfs.v
8b3d
mmcm_pll_drp_func_7s_mmcm.vhmmcm_pll_drp_func_7s_pll.vhmmcm_pll_drp_func_us_mmcm.vhmmcm_pll_drp_func_us_pll.vhmmcm_pll_drp_func_us_plus_mmcm.vhmmcm_pll_drp_func_us_plus_pll.vh
8dfa/hdl
axi_protocol_converter_v2_1_vl_rfs.v
a040/hdl
interrupt_control_v3_1_vh_rfs.vhd
a5cb/hdl
lib_fifo_v1_0_rfs.vhd
af86/hdl
axi_datamover_v5_1_vh_rfs.vhd
b68e/hdl
axi_crossbar_v2_1_vl_rfs.v
b752/hdl
generic_baseblocks_v2_1_vl_rfs.v
b8f8/hdl
verilog
axi_infrastructure_header.vhaxidma_fifo.vhdma_defines.svhdma_defines.vhdma_pcie_axis_cc_if.svhdma_pcie_axis_cq_if.svhdma_pcie_axis_rc_if.svhdma_pcie_axis_rq_if.svhdma_pcie_c2h_crdt_if.svhdma_pcie_dsc_in_if.svhdma_pcie_dsc_out_if.svhdma_pcie_fabric_input_if.svhdma_pcie_fabric_output_if.svhdma_pcie_gic_if.svhdma_pcie_h2c_crdt_if.svhdma_pcie_mi_16Bx2048_4Bwe_ram_if.svhdma_pcie_mi_2Bx2048_ram_if.svhdma_pcie_mi_4Bx2048_4Bwe_ram_if.svhdma_pcie_mi_64Bx1024_32Bwe_ram_if.svhdma_pcie_mi_64Bx128_32Bwe_ram_if.svhdma_pcie_mi_64Bx2048_32Bwe_ram_if.svhdma_pcie_mi_64Bx256_32Bwe_ram_if.svhdma_pcie_mi_64Bx512_32Bwe_ram_if.svhdma_pcie_mi_8Bx2048_4Bwe_ram_if.svhdma_pcie_mi_dsc_cpld_if.svhdma_pcie_mi_dsc_cpli_if.svhdma_pcie_misc_input_if.svhdma_pcie_misc_output_if.svhdma_soft_defines.vhpcie_dma_attr_defines.svhpciedmacoredefines.vhxdma_axi4mm_axi_bridge.vh
xdma_v4_1_vl_rfs.sv
bb35/hdl
axi_gpio_v2_0_vh_rfs.vhd
e6d5
hdl
fifo_generator_v13_1_rfs.vfifo_generator_v13_1_rfs.vhdfifo_generator_v13_1_vhsyn_rfs.vhd
simulation
fifo_generator_vlog_beh.v
ec67/hdl
axi_infrastructure_v1_1_0.vhaxi_infrastructure_v1_1_vl_rfs.v
ef1e/hdl
lib_cdc_v1_0_rfs.vhd
fcfc/hdl
xlconstant_v1_1_vl_rfs.v
sim
design_1.protoinstdesign_1.v
synth
design_1.hwdefdesign_1.v
ui
bd_1c0056ca.uibd_1f5defd0.uibd_2a847c9f.uibd_77ae6ffa.uibd_d985a9f1.uibd_e9229627.uibd_f8730b82.ui
imports
Verilog_macros
delay_controller_wrap.vserdes_1_to_468_idelay_ddr.v
dso_top
I2C_Transmit.vSPI_Transmit.v
hdl
dso_top.v
ip
.Xil
.clk_wiz_0.xcix.lock
clk_wiz_0.xcix
fifo_generator_0
fifo_generator_0.dcpfifo_generator_0.veofifo_generator_0.vhofifo_generator_0.xcififo_generator_0.xdcfifo_generator_0.xmlfifo_generator_0_clocks.xdcfifo_generator_0_ooc.xdcfifo_generator_0_sim_netlist.vfifo_generator_0_sim_netlist.vhdlfifo_generator_0_stub.vfifo_generator_0_stub.vhdl
hdl
blk_mem_gen_v8_4_vhsyn_rfs.vhdfifo_generator_v13_2_vhsyn_rfs.vhd
synth
fifo_generator_0.vhd
new
adc_to_datamover.vserdes.vserial_controller.v
FPGA_Module_Rev2_50T.xpr

BIN
Firmware/XDMA/FPGA_Module_Rev2_50T/FPGA_Module_Rev2_50T.bin
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This file was deleted.

1
Firmware/XDMA/FPGA_Module_Rev2_50T/FPGA_Module_Rev2_50T.ip_user_files/README.txt
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The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

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Firmware/XDMA/FPGA_Module_Rev2_50T/FPGA_Module_Rev2_50T.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo
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//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1__300.00000______0.000______50.0______175.656____648.245
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_____________125_______________10
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
clk_wiz_0 instance_name
(
// Clock out ports
.clk_out1(clk_out1), // output clk_out1
// Clock in ports
.clk_in1(clk_in1)); // input clk_in1
// INST_TAG_END ------ End INSTANTIATION Template ---------

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Firmware/XDMA/FPGA_Module_Rev2_50T/FPGA_Module_Rev2_50T.ip_user_files/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
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// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
// Date : Mon Apr 22 20:26:10 2024
// Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/Aleksa/Documents/FPGA_Dev/FPGA_Module_Rev2_50T/FPGA_Module_Rev2_50T.runs/clk_wiz_0_synth_1/clk_wiz_0_sim_netlist.v
// Design : clk_wiz_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a50tcsg325-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module clk_wiz_0
(clk_out1,
clk_in1);
output clk_out1;
input clk_in1;
wire clk_in1;
wire clk_out1;
clk_wiz_0_clk_wiz_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1));
endmodule
(* ORIG_REF_NAME = "clk_wiz_0_clk_wiz" *)
module clk_wiz_0_clk_wiz_0_clk_wiz
(clk_out1,
clk_in1);
output clk_out1;
input clk_in1;
wire clk_in1;
wire clk_in1_clk_wiz_0;
wire clk_out1;
wire clk_out1_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfbout_clk_wiz_0;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_wiz_0),
.O(clkfbout_buf_clk_wiz_0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkin1_bufg
(.I(clk_in1),
.O(clk_in1_clk_wiz_0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_clk_wiz_0),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("LOW"),
.CLKFBOUT_MULT_F(40.500000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(8.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(3.375000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("BUF_IN"),
.DIVCLK_DIVIDE(5),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_wiz_0),
.CLKFBOUT(clkfbout_clk_wiz_0),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_clk_wiz_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_clk_wiz_0),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif

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Firmware/XDMA/FPGA_Module_Rev2_50T/FPGA_Module_Rev2_50T.ip_user_files/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
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-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
-- Date : Mon Apr 22 20:26:10 2024
-- Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/Aleksa/Documents/FPGA_Dev/FPGA_Module_Rev2_50T/FPGA_Module_Rev2_50T.runs/clk_wiz_0_synth_1/clk_wiz_0_sim_netlist.vhdl
-- Design : clk_wiz_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a50tcsg325-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_wiz_0_clk_wiz_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of clk_wiz_0_clk_wiz_0_clk_wiz : entity is "clk_wiz_0_clk_wiz";
end clk_wiz_0_clk_wiz_0_clk_wiz;
architecture STRUCTURE of clk_wiz_0_clk_wiz_0_clk_wiz is
signal clk_in1_clk_wiz_0 : STD_LOGIC;
signal clk_out1_clk_wiz_0 : STD_LOGIC;
signal clkfbout_buf_clk_wiz_0 : STD_LOGIC;
signal clkfbout_clk_wiz_0 : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_bufg : label is "PRIMITIVE";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_wiz_0,
O => clkfbout_buf_clk_wiz_0
);
clkin1_bufg: unisim.vcomponents.BUFG
port map (
I => clk_in1,
O => clk_in1_clk_wiz_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_clk_wiz_0,
O => clk_out1
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "LOW",
CLKFBOUT_MULT_F => 40.500000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 8.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 3.375000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "BUF_IN",
DIVCLK_DIVIDE => 5,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_clk_wiz_0,
CLKFBOUT => clkfbout_clk_wiz_0,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_clk_wiz_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_clk_wiz_0,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => NLW_mmcm_adv_inst_LOCKED_UNCONNECTED,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_wiz_0 is
port (
clk_out1 : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_wiz_0 : entity is true;
end clk_wiz_0;
architecture STRUCTURE of clk_wiz_0 is
begin
inst: entity work.clk_wiz_0_clk_wiz_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1
);
end STRUCTURE;

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// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
// Date : Mon Apr 22 20:26:10 2024
// Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/Aleksa/Documents/FPGA_Dev/FPGA_Module_Rev2_50T/FPGA_Module_Rev2_50T.runs/clk_wiz_0_synth_1/clk_wiz_0_stub.v
// Design : clk_wiz_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a50tcsg325-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_wiz_0(clk_out1, clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_in1" */;
output clk_out1;
input clk_in1;
endmodule

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-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
-- Date : Mon Apr 22 20:26:10 2024
-- Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/Aleksa/Documents/FPGA_Dev/FPGA_Module_Rev2_50T/FPGA_Module_Rev2_50T.runs/clk_wiz_0_synth_1/clk_wiz_0_stub.vhdl
-- Design : clk_wiz_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a50tcsg325-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_wiz_0 is
Port (
clk_out1 : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end clk_wiz_0;
architecture stub of clk_wiz_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_in1";
begin
end;

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// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:13.2
// IP Revision: 5
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
fifo_generator_0 your_instance_name (
.rst(rst), // input wire rst
.wr_clk(wr_clk), // input wire wr_clk
.rd_clk(rd_clk), // input wire rd_clk
.din(din), // input wire [63 : 0] din
.wr_en(wr_en), // input wire wr_en
.rd_en(rd_en), // input wire rd_en
.dout(dout), // output wire [127 : 0] dout
.full(full), // output wire full
.empty(empty), // output wire empty
.valid(valid), // output wire valid
.wr_rst_busy(wr_rst_busy), // output wire wr_rst_busy
.rd_rst_busy(rd_rst_busy) // output wire rd_rst_busy
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file fifo_generator_0.v when simulating
// the core, fifo_generator_0. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

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-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
-- IP Revision: 5
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT fifo_generator_0
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : fifo_generator_0
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
valid => valid,
wr_rst_busy => wr_rst_busy,
rd_rst_busy => rd_rst_busy
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file fifo_generator_0.vhd when simulating
-- the core, fifo_generator_0. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.

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// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
// Date : Mon Apr 22 20:26:29 2024
// Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/Aleksa/Documents/FPGA_Dev/FPGA_Module_Rev2_50T/FPGA_Module_Rev2_50T.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0_stub.v
// Design : fifo_generator_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a50tcsg325-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_2_5,Vivado 2020.1" *)
module fifo_generator_0(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
empty, valid, wr_rst_busy, rd_rst_busy)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[63:0],wr_en,rd_en,dout[127:0],full,empty,valid,wr_rst_busy,rd_rst_busy" */;
input rst;
input wr_clk;
input rd_clk;
input [63:0]din;
input wr_en;
input rd_en;
output [127:0]dout;
output full;
output empty;
output valid;
output wr_rst_busy;
output rd_rst_busy;
endmodule

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-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
-- Date : Mon Apr 22 20:26:29 2024
-- Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/Aleksa/Documents/FPGA_Dev/FPGA_Module_Rev2_50T/FPGA_Module_Rev2_50T.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0_stub.vhdl
-- Design : fifo_generator_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a50tcsg325-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fifo_generator_0 is
Port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 127 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
valid : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC
);
end fifo_generator_0;
architecture stub of fifo_generator_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[63:0],wr_en,rd_en,dout[127:0],full,empty,valid,wr_rst_busy,rd_rst_busy";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.1";
begin
end;

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#ifndef _axi_clock_converter_
#define _axi_clock_converter_
#include <xtlm.h>
#include <utils/xtlm_aximm_passthru_module.h>
#include <systemc>
class axi_clock_converter:public sc_module{
public:
axi_clock_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&);
virtual ~axi_clock_converter();
SC_HAS_PROCESS(axi_clock_converter);
xtlm::xtlm_aximm_target_socket* S_TARGET_rd_socket;
xtlm::xtlm_aximm_target_socket* S_TARGET_wr_socket;
xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_rd_socket;
xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_wr_socket;
sc_in<bool> s_axi_aclk;
sc_in<bool> s_axi_aresetn;
sc_in<bool> m_axi_aclk;
sc_in<bool> m_axi_aresetn;
private:
xtlm::xtlm_aximm_passthru_module *P1;
xtlm::xtlm_aximm_passthru_module *P2;
};
#endif

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// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
#ifndef XTLM_SIMPLE_INTERCONNECT_H_
#define XTLM_SIMPLE_INTERCONNECT_H_
#include "xtlm.h"
class xtlm_simple_interconnect_model;
class axi_crossbar: public sc_core::sc_module {
public:
axi_crossbar(sc_module_name name, xsc::common_cpp::properties& properties);
virtual ~axi_crossbar();
xsc::common_cpp::report_handler* m_report_handler;
//Socket_declaration
xtlm::xtlm_aximm_initiator_socket* initiator_0_rd_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_0_wr_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_1_rd_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_1_wr_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_2_rd_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_2_wr_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_3_rd_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_3_wr_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_4_rd_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_4_wr_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_5_rd_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_5_wr_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_6_rd_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_6_wr_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_7_rd_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_7_wr_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_8_rd_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_8_wr_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_9_rd_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_9_wr_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_10_rd_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_10_wr_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_11_rd_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_11_wr_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_12_rd_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_12_wr_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_13_rd_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_13_wr_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_14_rd_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_14_wr_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_15_rd_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_15_wr_socket;
xtlm::xtlm_aximm_target_socket* target_0_rd_socket;
xtlm::xtlm_aximm_target_socket* target_0_wr_socket;
xtlm::xtlm_aximm_target_socket* target_1_rd_socket;
xtlm::xtlm_aximm_target_socket* target_1_wr_socket;
xtlm::xtlm_aximm_target_socket* target_2_rd_socket;
xtlm::xtlm_aximm_target_socket* target_2_wr_socket;
xtlm::xtlm_aximm_target_socket* target_3_rd_socket;
xtlm::xtlm_aximm_target_socket* target_3_wr_socket;
xtlm::xtlm_aximm_target_socket* target_4_rd_socket;
xtlm::xtlm_aximm_target_socket* target_4_wr_socket;
xtlm::xtlm_aximm_target_socket* target_5_rd_socket;
xtlm::xtlm_aximm_target_socket* target_5_wr_socket;
xtlm::xtlm_aximm_target_socket* target_6_rd_socket;
xtlm::xtlm_aximm_target_socket* target_6_wr_socket;
xtlm::xtlm_aximm_target_socket* target_7_rd_socket;
xtlm::xtlm_aximm_target_socket* target_7_wr_socket;
xtlm::xtlm_aximm_target_socket* target_8_rd_socket;
xtlm::xtlm_aximm_target_socket* target_8_wr_socket;
xtlm::xtlm_aximm_target_socket* target_9_rd_socket;
xtlm::xtlm_aximm_target_socket* target_9_wr_socket;
xtlm::xtlm_aximm_target_socket* target_10_rd_socket;
xtlm::xtlm_aximm_target_socket* target_10_wr_socket;
xtlm::xtlm_aximm_target_socket* target_11_rd_socket;
xtlm::xtlm_aximm_target_socket* target_11_wr_socket;
xtlm::xtlm_aximm_target_socket* target_12_rd_socket;
xtlm::xtlm_aximm_target_socket* target_12_wr_socket;
xtlm::xtlm_aximm_target_socket* target_13_rd_socket;
xtlm::xtlm_aximm_target_socket* target_13_wr_socket;
xtlm::xtlm_aximm_target_socket* target_14_rd_socket;
xtlm::xtlm_aximm_target_socket* target_14_wr_socket;
xtlm::xtlm_aximm_target_socket* target_15_rd_socket;
xtlm::xtlm_aximm_target_socket* target_15_wr_socket;
sc_in<bool> aclk;
sc_in<bool> aresetn;
private :
xtlm_simple_interconnect_model* m_model;
};
#endif /* XTLM_SIMPLE_INTERCONNECT_H_ */

24
Firmware/XDMA/FPGA_Module_Rev2_50T/FPGA_Module_Rev2_50T.ip_user_files/mem_init_files/axi_data_fifo.h
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#ifndef _axi_data_fifo_
#define _axi_data_fifo_
#include <xtlm.h>
#include <utils/xtlm_aximm_passthru_module.h>
#include <systemc>
class axi_data_fifo:public sc_module{
public:
axi_data_fifo(sc_core::sc_module_name module_name,xsc::common_cpp::properties&);
virtual ~axi_data_fifo();
SC_HAS_PROCESS(axi_data_fifo);
xtlm::xtlm_aximm_target_socket* S_TARGET_rd_socket;
xtlm::xtlm_aximm_target_socket* S_TARGET_wr_socket;
xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_rd_socket;
xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_wr_socket;
sc_in<bool> aclk;
sc_in<bool> aresetn;
private:
xtlm::xtlm_aximm_passthru_module *P1;
xtlm::xtlm_aximm_passthru_module *P2;
};
#endif

116
Firmware/XDMA/FPGA_Module_Rev2_50T/FPGA_Module_Rev2_50T.ip_user_files/mem_init_files/axi_dwidth_converter.h
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@ -1,116 +0,0 @@
// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
// (c) Copyright 2013 - 2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
#ifndef _AXI_DWIDTH_CONVERTER_H_
#define _AXI_DWIDTH_CONVERTER_H_
#include "xtlm.h"
#include "report_handler.h"
class axi_dwidth_converter: public sc_core::sc_module {
public:
SC_HAS_PROCESS(axi_dwidth_converter);
xtlm::xtlm_aximm_target_socket* target_rd_socket;
xtlm::xtlm_aximm_target_socket* target_wr_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
sc_core::sc_in<bool> s_axi_aclk;
sc_core::sc_in<bool> s_axi_aresetn;
sc_core::sc_in<bool> m_axi_aclk;
sc_core::sc_in<bool> m_axi_aresetn;
sc_core::sc_signal<bool> clk;
sc_core::sc_signal<bool> resetn;
axi_dwidth_converter(sc_core::sc_module_name p_name,
xsc::common_cpp::properties& m_properties);
xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
xtlm::xtlm_aximm_initiator_rd_socket_util* rd_initiator_util;
xtlm::xtlm_aximm_initiator_wr_socket_util* wr_initiator_util;
xtlm::xtlm_aximm_mem_manager* mem_manager;
~axi_dwidth_converter();
unsigned int SI_DATA_WIDTH;
unsigned int MI_DATA_WIDTH;
unsigned int FIFO_MODE;
unsigned int ratio;
void wr_handler();
void rd_handler();
void wr_upsizing();
void wr_downsizing();
void rd_upsizing();
void rd_downsizing();
/**
* @brief Method to send transaction on master interface
*/
void m_downsize_interface_txn_sender();
void m_upsize_interface_txn_sender();
void m_downsize_interface_response_sender();
void m_upsize_interface_response_sender();
private:
xtlm::aximm_payload* m_rd_trans;
xtlm::aximm_payload* m_wr_trans;
std::queue<xtlm::aximm_payload*> m_upsize_rd_payld_queue;
std::queue<xtlm::aximm_payload*> m_upsize_wr_payld_queue;
std::queue<xtlm::aximm_payload*> m_interface_wr_payload_queue;
std::queue<xtlm::aximm_payload*> m_interface_rd_payload_queue;
sc_core::sc_event event_downsize_trig_txn_sender; //!< Event to trigger Txn Sender Method
sc_core::sc_event event_upsize_trig_txn_sender; //!< Event to trigger Txn Sender Method
sc_core::sc_event event_trig_rd_handler;
sc_core::sc_event event_trig_wr_handler;
std::list<xtlm::aximm_payload* > *m_response_list;
std::map<xtlm::aximm_payload*,std::list<xtlm::aximm_payload*>*> m_response_mapper_downsize;
std::map<xtlm::aximm_payload*,xtlm::aximm_payload*> m_response_mapper_upsize;
xsc::common_cpp::report_handler m_logger;
std::string m_log_msg;
};
#endif /* _AXI_DWIDTH_CONVERTER_H_ */

65
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// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _bd_48ac_one_0_H_
#define _bd_48ac_one_0_H_
#include "xlconstant_v1_1_7.h"
#include "systemc.h"
class bd_48ac_one_0 : public sc_module {
public:
xlconstant_v1_1_7<1,1> mod;
sc_out< sc_bv<1> > dout;
bd_48ac_one_0 (sc_core::sc_module_name name);
};
#endif

683
Firmware/XDMA/FPGA_Module_Rev2_50T/FPGA_Module_Rev2_50T.ip_user_files/mem_init_files/design_1_auto_cc_0.h
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#ifndef IP_DESIGN_1_AUTO_CC_0_H_
#define IP_DESIGN_1_AUTO_CC_0_H_
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef XTLM
#include "xtlm.h"
#endif
#ifndef SYSTEMC_INCLUDED
#include <systemc>
#endif
#if defined(_MSC_VER)
#define DllExport __declspec(dllexport)
#elif defined(__GNUC__)
#define DllExport __attribute__ ((visibility("default")))
#else
#define DllExport
#endif
#include "design_1_auto_cc_0_sc.h"
#ifdef XILINX_SIMULATOR
class DllExport design_1_auto_cc_0 : public design_1_auto_cc_0_sc
{
public:
design_1_auto_cc_0(const sc_core::sc_module_name& nm);
virtual ~design_1_auto_cc_0();
// module pin-to-pin RTL interface
sc_core::sc_in< bool > s_axi_aclk;
sc_core::sc_in< bool > s_axi_aresetn;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awid;
sc_core::sc_in< sc_dt::sc_bv<30> > s_axi_awaddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
sc_core::sc_in< bool > s_axi_awvalid;
sc_core::sc_out< bool > s_axi_awready;
sc_core::sc_in< sc_dt::sc_bv<256> > s_axi_wdata;
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wstrb;
sc_core::sc_in< bool > s_axi_wlast;
sc_core::sc_in< bool > s_axi_wvalid;
sc_core::sc_out< bool > s_axi_wready;
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_bid;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
sc_core::sc_out< bool > s_axi_bvalid;
sc_core::sc_in< bool > s_axi_bready;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arid;
sc_core::sc_in< sc_dt::sc_bv<30> > s_axi_araddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
sc_core::sc_in< bool > s_axi_arvalid;
sc_core::sc_out< bool > s_axi_arready;
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rid;
sc_core::sc_out< sc_dt::sc_bv<256> > s_axi_rdata;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
sc_core::sc_out< bool > s_axi_rlast;
sc_core::sc_out< bool > s_axi_rvalid;
sc_core::sc_in< bool > s_axi_rready;
sc_core::sc_in< bool > m_axi_aclk;
sc_core::sc_in< bool > m_axi_aresetn;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awid;
sc_core::sc_out< sc_dt::sc_bv<30> > m_axi_awaddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
sc_core::sc_out< bool > m_axi_awvalid;
sc_core::sc_in< bool > m_axi_awready;
sc_core::sc_out< sc_dt::sc_bv<256> > m_axi_wdata;
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wstrb;
sc_core::sc_out< bool > m_axi_wlast;
sc_core::sc_out< bool > m_axi_wvalid;
sc_core::sc_in< bool > m_axi_wready;
sc_core::sc_in< sc_dt::sc_bv<1> > m_axi_bid;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
sc_core::sc_in< bool > m_axi_bvalid;
sc_core::sc_out< bool > m_axi_bready;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arid;
sc_core::sc_out< sc_dt::sc_bv<30> > m_axi_araddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
sc_core::sc_out< bool > m_axi_arvalid;
sc_core::sc_in< bool > m_axi_arready;
sc_core::sc_in< sc_dt::sc_bv<1> > m_axi_rid;
sc_core::sc_in< sc_dt::sc_bv<256> > m_axi_rdata;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
sc_core::sc_in< bool > m_axi_rlast;
sc_core::sc_in< bool > m_axi_rvalid;
sc_core::sc_out< bool > m_axi_rready;
protected:
virtual void before_end_of_elaboration();
private:
xtlm::xaximm_pin2xtlm_t<256,30,1,1,1,1,1,1>* mp_S_AXI_transactor;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
sc_signal< bool > m_s_axi_awlock_converter_signal;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
sc_signal< bool > m_s_axi_arlock_converter_signal;
sc_signal< bool > m_S_AXI_transactor_rst_signal;
xtlm::xaximm_xtlm2pin_t<256,30,1,1,1,1,1,1>* mp_M_AXI_transactor;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
sc_signal< bool > m_m_axi_awlock_converter_signal;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
sc_signal< bool > m_m_axi_arlock_converter_signal;
sc_signal< bool > m_M_AXI_transactor_rst_signal;
};
#endif // XILINX_SIMULATOR
#ifdef XM_SYSTEMC
class DllExport design_1_auto_cc_0 : public design_1_auto_cc_0_sc
{
public:
design_1_auto_cc_0(const sc_core::sc_module_name& nm);
virtual ~design_1_auto_cc_0();
// module pin-to-pin RTL interface
sc_core::sc_in< bool > s_axi_aclk;
sc_core::sc_in< bool > s_axi_aresetn;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awid;
sc_core::sc_in< sc_dt::sc_bv<30> > s_axi_awaddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
sc_core::sc_in< bool > s_axi_awvalid;
sc_core::sc_out< bool > s_axi_awready;
sc_core::sc_in< sc_dt::sc_bv<256> > s_axi_wdata;
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wstrb;
sc_core::sc_in< bool > s_axi_wlast;
sc_core::sc_in< bool > s_axi_wvalid;
sc_core::sc_out< bool > s_axi_wready;
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_bid;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
sc_core::sc_out< bool > s_axi_bvalid;
sc_core::sc_in< bool > s_axi_bready;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arid;
sc_core::sc_in< sc_dt::sc_bv<30> > s_axi_araddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
sc_core::sc_in< bool > s_axi_arvalid;
sc_core::sc_out< bool > s_axi_arready;
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rid;
sc_core::sc_out< sc_dt::sc_bv<256> > s_axi_rdata;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
sc_core::sc_out< bool > s_axi_rlast;
sc_core::sc_out< bool > s_axi_rvalid;
sc_core::sc_in< bool > s_axi_rready;
sc_core::sc_in< bool > m_axi_aclk;
sc_core::sc_in< bool > m_axi_aresetn;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awid;
sc_core::sc_out< sc_dt::sc_bv<30> > m_axi_awaddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
sc_core::sc_out< bool > m_axi_awvalid;
sc_core::sc_in< bool > m_axi_awready;
sc_core::sc_out< sc_dt::sc_bv<256> > m_axi_wdata;
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wstrb;
sc_core::sc_out< bool > m_axi_wlast;
sc_core::sc_out< bool > m_axi_wvalid;
sc_core::sc_in< bool > m_axi_wready;
sc_core::sc_in< sc_dt::sc_bv<1> > m_axi_bid;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
sc_core::sc_in< bool > m_axi_bvalid;
sc_core::sc_out< bool > m_axi_bready;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arid;
sc_core::sc_out< sc_dt::sc_bv<30> > m_axi_araddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
sc_core::sc_out< bool > m_axi_arvalid;
sc_core::sc_in< bool > m_axi_arready;
sc_core::sc_in< sc_dt::sc_bv<1> > m_axi_rid;
sc_core::sc_in< sc_dt::sc_bv<256> > m_axi_rdata;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
sc_core::sc_in< bool > m_axi_rlast;
sc_core::sc_in< bool > m_axi_rvalid;
sc_core::sc_out< bool > m_axi_rready;
protected:
virtual void before_end_of_elaboration();
private:
xtlm::xaximm_pin2xtlm_t<256,30,1,1,1,1,1,1>* mp_S_AXI_transactor;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
sc_signal< bool > m_s_axi_awlock_converter_signal;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
sc_signal< bool > m_s_axi_arlock_converter_signal;
sc_signal< bool > m_S_AXI_transactor_rst_signal;
xtlm::xaximm_xtlm2pin_t<256,30,1,1,1,1,1,1>* mp_M_AXI_transactor;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
sc_signal< bool > m_m_axi_awlock_converter_signal;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
sc_signal< bool > m_m_axi_arlock_converter_signal;
sc_signal< bool > m_M_AXI_transactor_rst_signal;
};
#endif // XM_SYSTEMC
#ifdef RIVIERA
class DllExport design_1_auto_cc_0 : public design_1_auto_cc_0_sc
{
public:
design_1_auto_cc_0(const sc_core::sc_module_name& nm);
virtual ~design_1_auto_cc_0();
// module pin-to-pin RTL interface
sc_core::sc_in< bool > s_axi_aclk;
sc_core::sc_in< bool > s_axi_aresetn;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awid;
sc_core::sc_in< sc_dt::sc_bv<30> > s_axi_awaddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
sc_core::sc_in< bool > s_axi_awvalid;
sc_core::sc_out< bool > s_axi_awready;
sc_core::sc_in< sc_dt::sc_bv<256> > s_axi_wdata;
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wstrb;
sc_core::sc_in< bool > s_axi_wlast;
sc_core::sc_in< bool > s_axi_wvalid;
sc_core::sc_out< bool > s_axi_wready;
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_bid;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
sc_core::sc_out< bool > s_axi_bvalid;
sc_core::sc_in< bool > s_axi_bready;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arid;
sc_core::sc_in< sc_dt::sc_bv<30> > s_axi_araddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
sc_core::sc_in< bool > s_axi_arvalid;
sc_core::sc_out< bool > s_axi_arready;
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rid;
sc_core::sc_out< sc_dt::sc_bv<256> > s_axi_rdata;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
sc_core::sc_out< bool > s_axi_rlast;
sc_core::sc_out< bool > s_axi_rvalid;
sc_core::sc_in< bool > s_axi_rready;
sc_core::sc_in< bool > m_axi_aclk;
sc_core::sc_in< bool > m_axi_aresetn;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awid;
sc_core::sc_out< sc_dt::sc_bv<30> > m_axi_awaddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
sc_core::sc_out< bool > m_axi_awvalid;
sc_core::sc_in< bool > m_axi_awready;
sc_core::sc_out< sc_dt::sc_bv<256> > m_axi_wdata;
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wstrb;
sc_core::sc_out< bool > m_axi_wlast;
sc_core::sc_out< bool > m_axi_wvalid;
sc_core::sc_in< bool > m_axi_wready;
sc_core::sc_in< sc_dt::sc_bv<1> > m_axi_bid;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
sc_core::sc_in< bool > m_axi_bvalid;
sc_core::sc_out< bool > m_axi_bready;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arid;
sc_core::sc_out< sc_dt::sc_bv<30> > m_axi_araddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
sc_core::sc_out< bool > m_axi_arvalid;
sc_core::sc_in< bool > m_axi_arready;
sc_core::sc_in< sc_dt::sc_bv<1> > m_axi_rid;
sc_core::sc_in< sc_dt::sc_bv<256> > m_axi_rdata;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
sc_core::sc_in< bool > m_axi_rlast;
sc_core::sc_in< bool > m_axi_rvalid;
sc_core::sc_out< bool > m_axi_rready;
protected:
virtual void before_end_of_elaboration();
private:
xtlm::xaximm_pin2xtlm_t<256,30,1,1,1,1,1,1>* mp_S_AXI_transactor;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
sc_signal< bool > m_s_axi_awlock_converter_signal;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
sc_signal< bool > m_s_axi_arlock_converter_signal;
sc_signal< bool > m_S_AXI_transactor_rst_signal;
xtlm::xaximm_xtlm2pin_t<256,30,1,1,1,1,1,1>* mp_M_AXI_transactor;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
sc_signal< bool > m_m_axi_awlock_converter_signal;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
sc_signal< bool > m_m_axi_arlock_converter_signal;
sc_signal< bool > m_M_AXI_transactor_rst_signal;
};
#endif // RIVIERA
#ifdef VCSSYSTEMC
#include "utils/xtlm_aximm_initiator_stub.h"
#include "utils/xtlm_aximm_target_stub.h"
class DllExport design_1_auto_cc_0 : public design_1_auto_cc_0_sc
{
public:
design_1_auto_cc_0(const sc_core::sc_module_name& nm);
virtual ~design_1_auto_cc_0();
// module pin-to-pin RTL interface
sc_core::sc_in< bool > s_axi_aclk;
sc_core::sc_in< bool > s_axi_aresetn;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awid;
sc_core::sc_in< sc_dt::sc_bv<30> > s_axi_awaddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
sc_core::sc_in< bool > s_axi_awvalid;
sc_core::sc_out< bool > s_axi_awready;
sc_core::sc_in< sc_dt::sc_bv<256> > s_axi_wdata;
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wstrb;
sc_core::sc_in< bool > s_axi_wlast;
sc_core::sc_in< bool > s_axi_wvalid;
sc_core::sc_out< bool > s_axi_wready;
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_bid;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
sc_core::sc_out< bool > s_axi_bvalid;
sc_core::sc_in< bool > s_axi_bready;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arid;
sc_core::sc_in< sc_dt::sc_bv<30> > s_axi_araddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
sc_core::sc_in< bool > s_axi_arvalid;
sc_core::sc_out< bool > s_axi_arready;
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rid;
sc_core::sc_out< sc_dt::sc_bv<256> > s_axi_rdata;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
sc_core::sc_out< bool > s_axi_rlast;
sc_core::sc_out< bool > s_axi_rvalid;
sc_core::sc_in< bool > s_axi_rready;
sc_core::sc_in< bool > m_axi_aclk;
sc_core::sc_in< bool > m_axi_aresetn;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awid;
sc_core::sc_out< sc_dt::sc_bv<30> > m_axi_awaddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
sc_core::sc_out< bool > m_axi_awvalid;
sc_core::sc_in< bool > m_axi_awready;
sc_core::sc_out< sc_dt::sc_bv<256> > m_axi_wdata;
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wstrb;
sc_core::sc_out< bool > m_axi_wlast;
sc_core::sc_out< bool > m_axi_wvalid;
sc_core::sc_in< bool > m_axi_wready;
sc_core::sc_in< sc_dt::sc_bv<1> > m_axi_bid;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
sc_core::sc_in< bool > m_axi_bvalid;
sc_core::sc_out< bool > m_axi_bready;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arid;
sc_core::sc_out< sc_dt::sc_bv<30> > m_axi_araddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
sc_core::sc_out< bool > m_axi_arvalid;
sc_core::sc_in< bool > m_axi_arready;
sc_core::sc_in< sc_dt::sc_bv<1> > m_axi_rid;
sc_core::sc_in< sc_dt::sc_bv<256> > m_axi_rdata;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
sc_core::sc_in< bool > m_axi_rlast;
sc_core::sc_in< bool > m_axi_rvalid;
sc_core::sc_out< bool > m_axi_rready;
protected:
virtual void before_end_of_elaboration();
private:
xtlm::xaximm_pin2xtlm_t<256,30,1,1,1,1,1,1>* mp_S_AXI_transactor;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
sc_signal< bool > m_s_axi_awlock_converter_signal;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
sc_signal< bool > m_s_axi_arlock_converter_signal;
sc_signal< bool > m_S_AXI_transactor_rst_signal;
xtlm::xaximm_xtlm2pin_t<256,30,1,1,1,1,1,1>* mp_M_AXI_transactor;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
sc_signal< bool > m_m_axi_awlock_converter_signal;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
sc_signal< bool > m_m_axi_arlock_converter_signal;
sc_signal< bool > m_M_AXI_transactor_rst_signal;
// Transactor stubs
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
// Socket stubs
};
#endif // VCSSYSTEMC
#ifdef MTI_SYSTEMC
#include "utils/xtlm_aximm_initiator_stub.h"
#include "utils/xtlm_aximm_target_stub.h"
class DllExport design_1_auto_cc_0 : public design_1_auto_cc_0_sc
{
public:
design_1_auto_cc_0(const sc_core::sc_module_name& nm);
virtual ~design_1_auto_cc_0();
// module pin-to-pin RTL interface
sc_core::sc_in< bool > s_axi_aclk;
sc_core::sc_in< bool > s_axi_aresetn;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awid;
sc_core::sc_in< sc_dt::sc_bv<30> > s_axi_awaddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
sc_core::sc_in< bool > s_axi_awvalid;
sc_core::sc_out< bool > s_axi_awready;
sc_core::sc_in< sc_dt::sc_bv<256> > s_axi_wdata;
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wstrb;
sc_core::sc_in< bool > s_axi_wlast;
sc_core::sc_in< bool > s_axi_wvalid;
sc_core::sc_out< bool > s_axi_wready;
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_bid;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
sc_core::sc_out< bool > s_axi_bvalid;
sc_core::sc_in< bool > s_axi_bready;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arid;
sc_core::sc_in< sc_dt::sc_bv<30> > s_axi_araddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
sc_core::sc_in< bool > s_axi_arvalid;
sc_core::sc_out< bool > s_axi_arready;
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rid;
sc_core::sc_out< sc_dt::sc_bv<256> > s_axi_rdata;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
sc_core::sc_out< bool > s_axi_rlast;
sc_core::sc_out< bool > s_axi_rvalid;
sc_core::sc_in< bool > s_axi_rready;
sc_core::sc_in< bool > m_axi_aclk;
sc_core::sc_in< bool > m_axi_aresetn;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awid;
sc_core::sc_out< sc_dt::sc_bv<30> > m_axi_awaddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
sc_core::sc_out< bool > m_axi_awvalid;
sc_core::sc_in< bool > m_axi_awready;
sc_core::sc_out< sc_dt::sc_bv<256> > m_axi_wdata;
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wstrb;
sc_core::sc_out< bool > m_axi_wlast;
sc_core::sc_out< bool > m_axi_wvalid;
sc_core::sc_in< bool > m_axi_wready;
sc_core::sc_in< sc_dt::sc_bv<1> > m_axi_bid;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
sc_core::sc_in< bool > m_axi_bvalid;
sc_core::sc_out< bool > m_axi_bready;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arid;
sc_core::sc_out< sc_dt::sc_bv<30> > m_axi_araddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
sc_core::sc_out< bool > m_axi_arvalid;
sc_core::sc_in< bool > m_axi_arready;
sc_core::sc_in< sc_dt::sc_bv<1> > m_axi_rid;
sc_core::sc_in< sc_dt::sc_bv<256> > m_axi_rdata;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
sc_core::sc_in< bool > m_axi_rlast;
sc_core::sc_in< bool > m_axi_rvalid;
sc_core::sc_out< bool > m_axi_rready;
protected:
virtual void before_end_of_elaboration();
private:
xtlm::xaximm_pin2xtlm_t<256,30,1,1,1,1,1,1>* mp_S_AXI_transactor;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
sc_signal< bool > m_s_axi_awlock_converter_signal;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
sc_signal< bool > m_s_axi_arlock_converter_signal;
sc_signal< bool > m_S_AXI_transactor_rst_signal;
xtlm::xaximm_xtlm2pin_t<256,30,1,1,1,1,1,1>* mp_M_AXI_transactor;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
sc_signal< bool > m_m_axi_awlock_converter_signal;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
sc_signal< bool > m_m_axi_arlock_converter_signal;
sc_signal< bool > m_M_AXI_transactor_rst_signal;
// Transactor stubs
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
// Socket stubs
};
#endif // MTI_SYSTEMC
#endif // IP_DESIGN_1_AUTO_CC_0_H_

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#ifndef IP_DESIGN_1_AUTO_CC_0_SC_H_
#define IP_DESIGN_1_AUTO_CC_0_SC_H_
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef XTLM
#include "xtlm.h"
#endif
#ifndef SYSTEMC_INCLUDED
#include <systemc>
#endif
#if defined(_MSC_VER)
#define DllExport __declspec(dllexport)
#elif defined(__GNUC__)
#define DllExport __attribute__ ((visibility("default")))
#else
#define DllExport
#endif
class axi_clock_converter;
class DllExport design_1_auto_cc_0_sc : public sc_core::sc_module
{
public:
design_1_auto_cc_0_sc(const sc_core::sc_module_name& nm);
virtual ~design_1_auto_cc_0_sc();
public: // module socket-to-socket TLM interface
xtlm::xtlm_aximm_target_socket* S_TARGET_rd_socket;
xtlm::xtlm_aximm_target_socket* S_TARGET_wr_socket;
xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_rd_socket;
xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_wr_socket;
protected:
axi_clock_converter* mp_impl;
private:
design_1_auto_cc_0_sc(const design_1_auto_cc_0_sc&);
const design_1_auto_cc_0_sc& operator=(const design_1_auto_cc_0_sc&);
};
#endif // IP_DESIGN_1_AUTO_CC_0_SC_H_

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#ifndef IP_DESIGN_1_AUTO_US_DF_0_H_
#define IP_DESIGN_1_AUTO_US_DF_0_H_
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef XTLM
#include "xtlm.h"
#endif
#ifndef SYSTEMC_INCLUDED
#include <systemc>
#endif
#if defined(_MSC_VER)
#define DllExport __declspec(dllexport)
#elif defined(__GNUC__)
#define DllExport __attribute__ ((visibility("default")))
#else
#define DllExport
#endif
#include "design_1_auto_us_df_0_sc.h"
#ifdef XILINX_SIMULATOR
class DllExport design_1_auto_us_df_0 : public design_1_auto_us_df_0_sc
{
public:
design_1_auto_us_df_0(const sc_core::sc_module_name& nm);
virtual ~design_1_auto_us_df_0();
// module pin-to-pin RTL interface
sc_core::sc_in< bool > s_axi_aclk;
sc_core::sc_in< bool > s_axi_aresetn;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awid;
sc_core::sc_in< sc_dt::sc_bv<64> > s_axi_awaddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
sc_core::sc_in< bool > s_axi_awvalid;
sc_core::sc_out< bool > s_axi_awready;
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
sc_core::sc_in< bool > s_axi_wlast;
sc_core::sc_in< bool > s_axi_wvalid;
sc_core::sc_out< bool > s_axi_wready;
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_bid;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
sc_core::sc_out< bool > s_axi_bvalid;
sc_core::sc_in< bool > s_axi_bready;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arid;
sc_core::sc_in< sc_dt::sc_bv<64> > s_axi_araddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
sc_core::sc_in< bool > s_axi_arvalid;
sc_core::sc_out< bool > s_axi_arready;
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_rid;
sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
sc_core::sc_out< bool > s_axi_rlast;
sc_core::sc_out< bool > s_axi_rvalid;
sc_core::sc_in< bool > s_axi_rready;
sc_core::sc_out< sc_dt::sc_bv<64> > m_axi_awaddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
sc_core::sc_out< bool > m_axi_awvalid;
sc_core::sc_in< bool > m_axi_awready;
sc_core::sc_out< sc_dt::sc_bv<256> > m_axi_wdata;
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wstrb;
sc_core::sc_out< bool > m_axi_wlast;
sc_core::sc_out< bool > m_axi_wvalid;
sc_core::sc_in< bool > m_axi_wready;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
sc_core::sc_in< bool > m_axi_bvalid;
sc_core::sc_out< bool > m_axi_bready;
sc_core::sc_out< sc_dt::sc_bv<64> > m_axi_araddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
sc_core::sc_out< bool > m_axi_arvalid;
sc_core::sc_in< bool > m_axi_arready;
sc_core::sc_in< sc_dt::sc_bv<256> > m_axi_rdata;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
sc_core::sc_in< bool > m_axi_rlast;
sc_core::sc_in< bool > m_axi_rvalid;
sc_core::sc_out< bool > m_axi_rready;
protected:
virtual void before_end_of_elaboration();
private:
xtlm::xaximm_pin2xtlm_t<128,64,4,1,1,1,1,1>* mp_S_AXI_transactor;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
sc_signal< bool > m_s_axi_awlock_converter_signal;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
sc_signal< bool > m_s_axi_arlock_converter_signal;
sc_signal< bool > m_S_AXI_transactor_rst_signal;
xtlm::xaximm_xtlm2pin_t<256,64,1,1,1,1,1,1>* mp_M_AXI_transactor;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
sc_signal< bool > m_m_axi_awlock_converter_signal;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
sc_signal< bool > m_m_axi_arlock_converter_signal;
sc_signal< bool > m_M_AXI_transactor_rst_signal;
};
#endif // XILINX_SIMULATOR
#ifdef XM_SYSTEMC
class DllExport design_1_auto_us_df_0 : public design_1_auto_us_df_0_sc
{
public:
design_1_auto_us_df_0(const sc_core::sc_module_name& nm);
virtual ~design_1_auto_us_df_0();
// module pin-to-pin RTL interface
sc_core::sc_in< bool > s_axi_aclk;
sc_core::sc_in< bool > s_axi_aresetn;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awid;
sc_core::sc_in< sc_dt::sc_bv<64> > s_axi_awaddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
sc_core::sc_in< bool > s_axi_awvalid;
sc_core::sc_out< bool > s_axi_awready;
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
sc_core::sc_in< bool > s_axi_wlast;
sc_core::sc_in< bool > s_axi_wvalid;
sc_core::sc_out< bool > s_axi_wready;
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_bid;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
sc_core::sc_out< bool > s_axi_bvalid;
sc_core::sc_in< bool > s_axi_bready;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arid;
sc_core::sc_in< sc_dt::sc_bv<64> > s_axi_araddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
sc_core::sc_in< bool > s_axi_arvalid;
sc_core::sc_out< bool > s_axi_arready;
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_rid;
sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
sc_core::sc_out< bool > s_axi_rlast;
sc_core::sc_out< bool > s_axi_rvalid;
sc_core::sc_in< bool > s_axi_rready;
sc_core::sc_out< sc_dt::sc_bv<64> > m_axi_awaddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
sc_core::sc_out< bool > m_axi_awvalid;
sc_core::sc_in< bool > m_axi_awready;
sc_core::sc_out< sc_dt::sc_bv<256> > m_axi_wdata;
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wstrb;
sc_core::sc_out< bool > m_axi_wlast;
sc_core::sc_out< bool > m_axi_wvalid;
sc_core::sc_in< bool > m_axi_wready;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
sc_core::sc_in< bool > m_axi_bvalid;
sc_core::sc_out< bool > m_axi_bready;
sc_core::sc_out< sc_dt::sc_bv<64> > m_axi_araddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
sc_core::sc_out< bool > m_axi_arvalid;
sc_core::sc_in< bool > m_axi_arready;
sc_core::sc_in< sc_dt::sc_bv<256> > m_axi_rdata;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
sc_core::sc_in< bool > m_axi_rlast;
sc_core::sc_in< bool > m_axi_rvalid;
sc_core::sc_out< bool > m_axi_rready;
protected:
virtual void before_end_of_elaboration();
private:
xtlm::xaximm_pin2xtlm_t<128,64,4,1,1,1,1,1>* mp_S_AXI_transactor;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
sc_signal< bool > m_s_axi_awlock_converter_signal;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
sc_signal< bool > m_s_axi_arlock_converter_signal;
sc_signal< bool > m_S_AXI_transactor_rst_signal;
xtlm::xaximm_xtlm2pin_t<256,64,1,1,1,1,1,1>* mp_M_AXI_transactor;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
sc_signal< bool > m_m_axi_awlock_converter_signal;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
sc_signal< bool > m_m_axi_arlock_converter_signal;
sc_signal< bool > m_M_AXI_transactor_rst_signal;
};
#endif // XM_SYSTEMC
#ifdef RIVIERA
class DllExport design_1_auto_us_df_0 : public design_1_auto_us_df_0_sc
{
public:
design_1_auto_us_df_0(const sc_core::sc_module_name& nm);
virtual ~design_1_auto_us_df_0();
// module pin-to-pin RTL interface
sc_core::sc_in< bool > s_axi_aclk;
sc_core::sc_in< bool > s_axi_aresetn;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awid;
sc_core::sc_in< sc_dt::sc_bv<64> > s_axi_awaddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
sc_core::sc_in< bool > s_axi_awvalid;
sc_core::sc_out< bool > s_axi_awready;
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
sc_core::sc_in< bool > s_axi_wlast;
sc_core::sc_in< bool > s_axi_wvalid;
sc_core::sc_out< bool > s_axi_wready;
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_bid;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
sc_core::sc_out< bool > s_axi_bvalid;
sc_core::sc_in< bool > s_axi_bready;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arid;
sc_core::sc_in< sc_dt::sc_bv<64> > s_axi_araddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
sc_core::sc_in< bool > s_axi_arvalid;
sc_core::sc_out< bool > s_axi_arready;
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_rid;
sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
sc_core::sc_out< bool > s_axi_rlast;
sc_core::sc_out< bool > s_axi_rvalid;
sc_core::sc_in< bool > s_axi_rready;
sc_core::sc_out< sc_dt::sc_bv<64> > m_axi_awaddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
sc_core::sc_out< bool > m_axi_awvalid;
sc_core::sc_in< bool > m_axi_awready;
sc_core::sc_out< sc_dt::sc_bv<256> > m_axi_wdata;
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wstrb;
sc_core::sc_out< bool > m_axi_wlast;
sc_core::sc_out< bool > m_axi_wvalid;
sc_core::sc_in< bool > m_axi_wready;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
sc_core::sc_in< bool > m_axi_bvalid;
sc_core::sc_out< bool > m_axi_bready;
sc_core::sc_out< sc_dt::sc_bv<64> > m_axi_araddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
sc_core::sc_out< bool > m_axi_arvalid;
sc_core::sc_in< bool > m_axi_arready;
sc_core::sc_in< sc_dt::sc_bv<256> > m_axi_rdata;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
sc_core::sc_in< bool > m_axi_rlast;
sc_core::sc_in< bool > m_axi_rvalid;
sc_core::sc_out< bool > m_axi_rready;
protected:
virtual void before_end_of_elaboration();
private:
xtlm::xaximm_pin2xtlm_t<128,64,4,1,1,1,1,1>* mp_S_AXI_transactor;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
sc_signal< bool > m_s_axi_awlock_converter_signal;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
sc_signal< bool > m_s_axi_arlock_converter_signal;
sc_signal< bool > m_S_AXI_transactor_rst_signal;
xtlm::xaximm_xtlm2pin_t<256,64,1,1,1,1,1,1>* mp_M_AXI_transactor;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
sc_signal< bool > m_m_axi_awlock_converter_signal;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
sc_signal< bool > m_m_axi_arlock_converter_signal;
sc_signal< bool > m_M_AXI_transactor_rst_signal;
};
#endif // RIVIERA
#ifdef VCSSYSTEMC
#include "utils/xtlm_aximm_initiator_stub.h"
#include "utils/xtlm_aximm_target_stub.h"
class DllExport design_1_auto_us_df_0 : public design_1_auto_us_df_0_sc
{
public:
design_1_auto_us_df_0(const sc_core::sc_module_name& nm);
virtual ~design_1_auto_us_df_0();
// module pin-to-pin RTL interface
sc_core::sc_in< bool > s_axi_aclk;
sc_core::sc_in< bool > s_axi_aresetn;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awid;
sc_core::sc_in< sc_dt::sc_bv<64> > s_axi_awaddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
sc_core::sc_in< bool > s_axi_awvalid;
sc_core::sc_out< bool > s_axi_awready;
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
sc_core::sc_in< bool > s_axi_wlast;
sc_core::sc_in< bool > s_axi_wvalid;
sc_core::sc_out< bool > s_axi_wready;
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_bid;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
sc_core::sc_out< bool > s_axi_bvalid;
sc_core::sc_in< bool > s_axi_bready;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arid;
sc_core::sc_in< sc_dt::sc_bv<64> > s_axi_araddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
sc_core::sc_in< bool > s_axi_arvalid;
sc_core::sc_out< bool > s_axi_arready;
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_rid;
sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
sc_core::sc_out< bool > s_axi_rlast;
sc_core::sc_out< bool > s_axi_rvalid;
sc_core::sc_in< bool > s_axi_rready;
sc_core::sc_out< sc_dt::sc_bv<64> > m_axi_awaddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
sc_core::sc_out< bool > m_axi_awvalid;
sc_core::sc_in< bool > m_axi_awready;
sc_core::sc_out< sc_dt::sc_bv<256> > m_axi_wdata;
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wstrb;
sc_core::sc_out< bool > m_axi_wlast;
sc_core::sc_out< bool > m_axi_wvalid;
sc_core::sc_in< bool > m_axi_wready;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
sc_core::sc_in< bool > m_axi_bvalid;
sc_core::sc_out< bool > m_axi_bready;
sc_core::sc_out< sc_dt::sc_bv<64> > m_axi_araddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
sc_core::sc_out< bool > m_axi_arvalid;
sc_core::sc_in< bool > m_axi_arready;
sc_core::sc_in< sc_dt::sc_bv<256> > m_axi_rdata;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
sc_core::sc_in< bool > m_axi_rlast;
sc_core::sc_in< bool > m_axi_rvalid;
sc_core::sc_out< bool > m_axi_rready;
protected:
virtual void before_end_of_elaboration();
private:
xtlm::xaximm_pin2xtlm_t<128,64,4,1,1,1,1,1>* mp_S_AXI_transactor;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
sc_signal< bool > m_s_axi_awlock_converter_signal;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
sc_signal< bool > m_s_axi_arlock_converter_signal;
sc_signal< bool > m_S_AXI_transactor_rst_signal;
xtlm::xaximm_xtlm2pin_t<256,64,1,1,1,1,1,1>* mp_M_AXI_transactor;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
sc_signal< bool > m_m_axi_awlock_converter_signal;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
sc_signal< bool > m_m_axi_arlock_converter_signal;
sc_signal< bool > m_M_AXI_transactor_rst_signal;
// Transactor stubs
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
// Socket stubs
};
#endif // VCSSYSTEMC
#ifdef MTI_SYSTEMC
#include "utils/xtlm_aximm_initiator_stub.h"
#include "utils/xtlm_aximm_target_stub.h"
class DllExport design_1_auto_us_df_0 : public design_1_auto_us_df_0_sc
{
public:
design_1_auto_us_df_0(const sc_core::sc_module_name& nm);
virtual ~design_1_auto_us_df_0();
// module pin-to-pin RTL interface
sc_core::sc_in< bool > s_axi_aclk;
sc_core::sc_in< bool > s_axi_aresetn;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awid;
sc_core::sc_in< sc_dt::sc_bv<64> > s_axi_awaddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
sc_core::sc_in< bool > s_axi_awvalid;
sc_core::sc_out< bool > s_axi_awready;
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
sc_core::sc_in< bool > s_axi_wlast;
sc_core::sc_in< bool > s_axi_wvalid;
sc_core::sc_out< bool > s_axi_wready;
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_bid;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
sc_core::sc_out< bool > s_axi_bvalid;
sc_core::sc_in< bool > s_axi_bready;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arid;
sc_core::sc_in< sc_dt::sc_bv<64> > s_axi_araddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
sc_core::sc_in< bool > s_axi_arvalid;
sc_core::sc_out< bool > s_axi_arready;
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_rid;
sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
sc_core::sc_out< bool > s_axi_rlast;
sc_core::sc_out< bool > s_axi_rvalid;
sc_core::sc_in< bool > s_axi_rready;
sc_core::sc_out< sc_dt::sc_bv<64> > m_axi_awaddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
sc_core::sc_out< bool > m_axi_awvalid;
sc_core::sc_in< bool > m_axi_awready;
sc_core::sc_out< sc_dt::sc_bv<256> > m_axi_wdata;
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wstrb;
sc_core::sc_out< bool > m_axi_wlast;
sc_core::sc_out< bool > m_axi_wvalid;
sc_core::sc_in< bool > m_axi_wready;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
sc_core::sc_in< bool > m_axi_bvalid;
sc_core::sc_out< bool > m_axi_bready;
sc_core::sc_out< sc_dt::sc_bv<64> > m_axi_araddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
sc_core::sc_out< bool > m_axi_arvalid;
sc_core::sc_in< bool > m_axi_arready;
sc_core::sc_in< sc_dt::sc_bv<256> > m_axi_rdata;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
sc_core::sc_in< bool > m_axi_rlast;
sc_core::sc_in< bool > m_axi_rvalid;
sc_core::sc_out< bool > m_axi_rready;
protected:
virtual void before_end_of_elaboration();
private:
xtlm::xaximm_pin2xtlm_t<128,64,4,1,1,1,1,1>* mp_S_AXI_transactor;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
sc_signal< bool > m_s_axi_awlock_converter_signal;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
sc_signal< bool > m_s_axi_arlock_converter_signal;
sc_signal< bool > m_S_AXI_transactor_rst_signal;
xtlm::xaximm_xtlm2pin_t<256,64,1,1,1,1,1,1>* mp_M_AXI_transactor;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
sc_signal< bool > m_m_axi_awlock_converter_signal;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
sc_signal< bool > m_m_axi_arlock_converter_signal;
sc_signal< bool > m_M_AXI_transactor_rst_signal;
// Transactor stubs
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
// Socket stubs
};
#endif // MTI_SYSTEMC
#endif // IP_DESIGN_1_AUTO_US_DF_0_H_

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Firmware/XDMA/FPGA_Module_Rev2_50T/FPGA_Module_Rev2_50T.ip_user_files/mem_init_files/design_1_auto_us_df_0_sc.h
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#ifndef IP_DESIGN_1_AUTO_US_DF_0_SC_H_
#define IP_DESIGN_1_AUTO_US_DF_0_SC_H_
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef XTLM
#include "xtlm.h"
#endif
#ifndef SYSTEMC_INCLUDED
#include <systemc>
#endif
#if defined(_MSC_VER)
#define DllExport __declspec(dllexport)
#elif defined(__GNUC__)
#define DllExport __attribute__ ((visibility("default")))
#else
#define DllExport
#endif
class axi_dwidth_converter;
class DllExport design_1_auto_us_df_0_sc : public sc_core::sc_module
{
public:
design_1_auto_us_df_0_sc(const sc_core::sc_module_name& nm);
virtual ~design_1_auto_us_df_0_sc();
public: // module socket-to-socket TLM interface
xtlm::xtlm_aximm_target_socket* target_rd_socket;
xtlm::xtlm_aximm_target_socket* target_wr_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
protected:
axi_dwidth_converter* mp_impl;
private:
design_1_auto_us_df_0_sc(const design_1_auto_us_df_0_sc&);
const design_1_auto_us_df_0_sc& operator=(const design_1_auto_us_df_0_sc&);
};
#endif // IP_DESIGN_1_AUTO_US_DF_0_SC_H_

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Firmware/XDMA/FPGA_Module_Rev2_50T/FPGA_Module_Rev2_50T.ip_user_files/mem_init_files/design_1_auto_us_df_1.h
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@ -1,475 +0,0 @@
#ifndef IP_DESIGN_1_AUTO_US_DF_1_H_
#define IP_DESIGN_1_AUTO_US_DF_1_H_
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef XTLM
#include "xtlm.h"
#endif
#ifndef SYSTEMC_INCLUDED
#include <systemc>
#endif
#if defined(_MSC_VER)
#define DllExport __declspec(dllexport)
#elif defined(__GNUC__)
#define DllExport __attribute__ ((visibility("default")))
#else
#define DllExport
#endif
#include "design_1_auto_us_df_1_sc.h"
#ifdef XILINX_SIMULATOR
#include "utils/xtlm_aximm_initiator_stub.h"
#include "utils/xtlm_aximm_target_stub.h"
class DllExport design_1_auto_us_df_1 : public design_1_auto_us_df_1_sc
{
public:
design_1_auto_us_df_1(const sc_core::sc_module_name& nm);
virtual ~design_1_auto_us_df_1();
// module pin-to-pin RTL interface
sc_core::sc_in< bool > s_axi_aclk;
sc_core::sc_in< bool > s_axi_aresetn;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awid;
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
sc_core::sc_in< bool > s_axi_awvalid;
sc_core::sc_out< bool > s_axi_awready;
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
sc_core::sc_in< bool > s_axi_wlast;
sc_core::sc_in< bool > s_axi_wvalid;
sc_core::sc_out< bool > s_axi_wready;
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_bid;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
sc_core::sc_out< bool > s_axi_bvalid;
sc_core::sc_in< bool > s_axi_bready;
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
sc_core::sc_out< bool > m_axi_awvalid;
sc_core::sc_in< bool > m_axi_awready;
sc_core::sc_out< sc_dt::sc_bv<256> > m_axi_wdata;
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wstrb;
sc_core::sc_out< bool > m_axi_wlast;
sc_core::sc_out< bool > m_axi_wvalid;
sc_core::sc_in< bool > m_axi_wready;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
sc_core::sc_in< bool > m_axi_bvalid;
sc_core::sc_out< bool > m_axi_bready;
protected:
virtual void before_end_of_elaboration();
private:
xtlm::xaximm_pin2xtlm_t<128,32,4,1,1,1,1,1>* mp_S_AXI_transactor;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
sc_signal< bool > m_s_axi_awlock_converter_signal;
sc_signal< bool > m_S_AXI_transactor_rst_signal;
xtlm::xaximm_xtlm2pin_t<256,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
sc_signal< bool > m_m_axi_awlock_converter_signal;
sc_signal< bool > m_M_AXI_transactor_rst_signal;
xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_rd_socket_stub;
xtlm::xtlm_aximm_target_stub* mp_M_AXI_rd_socket_stub;
};
#endif // XILINX_SIMULATOR
#ifdef XM_SYSTEMC
#include "utils/xtlm_aximm_initiator_stub.h"
#include "utils/xtlm_aximm_target_stub.h"
class DllExport design_1_auto_us_df_1 : public design_1_auto_us_df_1_sc
{
public:
design_1_auto_us_df_1(const sc_core::sc_module_name& nm);
virtual ~design_1_auto_us_df_1();
// module pin-to-pin RTL interface
sc_core::sc_in< bool > s_axi_aclk;
sc_core::sc_in< bool > s_axi_aresetn;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awid;
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
sc_core::sc_in< bool > s_axi_awvalid;
sc_core::sc_out< bool > s_axi_awready;
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
sc_core::sc_in< bool > s_axi_wlast;
sc_core::sc_in< bool > s_axi_wvalid;
sc_core::sc_out< bool > s_axi_wready;
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_bid;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
sc_core::sc_out< bool > s_axi_bvalid;
sc_core::sc_in< bool > s_axi_bready;
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
sc_core::sc_out< bool > m_axi_awvalid;
sc_core::sc_in< bool > m_axi_awready;
sc_core::sc_out< sc_dt::sc_bv<256> > m_axi_wdata;
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wstrb;
sc_core::sc_out< bool > m_axi_wlast;
sc_core::sc_out< bool > m_axi_wvalid;
sc_core::sc_in< bool > m_axi_wready;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
sc_core::sc_in< bool > m_axi_bvalid;
sc_core::sc_out< bool > m_axi_bready;
protected:
virtual void before_end_of_elaboration();
private:
xtlm::xaximm_pin2xtlm_t<128,32,4,1,1,1,1,1>* mp_S_AXI_transactor;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
sc_signal< bool > m_s_axi_awlock_converter_signal;
sc_signal< bool > m_S_AXI_transactor_rst_signal;
xtlm::xaximm_xtlm2pin_t<256,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
sc_signal< bool > m_m_axi_awlock_converter_signal;
sc_signal< bool > m_M_AXI_transactor_rst_signal;
xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_rd_socket_stub;
xtlm::xtlm_aximm_target_stub* mp_M_AXI_rd_socket_stub;
};
#endif // XM_SYSTEMC
#ifdef RIVIERA
#include "utils/xtlm_aximm_initiator_stub.h"
#include "utils/xtlm_aximm_target_stub.h"
class DllExport design_1_auto_us_df_1 : public design_1_auto_us_df_1_sc
{
public:
design_1_auto_us_df_1(const sc_core::sc_module_name& nm);
virtual ~design_1_auto_us_df_1();
// module pin-to-pin RTL interface
sc_core::sc_in< bool > s_axi_aclk;
sc_core::sc_in< bool > s_axi_aresetn;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awid;
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
sc_core::sc_in< bool > s_axi_awvalid;
sc_core::sc_out< bool > s_axi_awready;
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
sc_core::sc_in< bool > s_axi_wlast;
sc_core::sc_in< bool > s_axi_wvalid;
sc_core::sc_out< bool > s_axi_wready;
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_bid;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
sc_core::sc_out< bool > s_axi_bvalid;
sc_core::sc_in< bool > s_axi_bready;
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
sc_core::sc_out< bool > m_axi_awvalid;
sc_core::sc_in< bool > m_axi_awready;
sc_core::sc_out< sc_dt::sc_bv<256> > m_axi_wdata;
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wstrb;
sc_core::sc_out< bool > m_axi_wlast;
sc_core::sc_out< bool > m_axi_wvalid;
sc_core::sc_in< bool > m_axi_wready;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
sc_core::sc_in< bool > m_axi_bvalid;
sc_core::sc_out< bool > m_axi_bready;
protected:
virtual void before_end_of_elaboration();
private:
xtlm::xaximm_pin2xtlm_t<128,32,4,1,1,1,1,1>* mp_S_AXI_transactor;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
sc_signal< bool > m_s_axi_awlock_converter_signal;
sc_signal< bool > m_S_AXI_transactor_rst_signal;
xtlm::xaximm_xtlm2pin_t<256,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
sc_signal< bool > m_m_axi_awlock_converter_signal;
sc_signal< bool > m_M_AXI_transactor_rst_signal;
xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_rd_socket_stub;
xtlm::xtlm_aximm_target_stub* mp_M_AXI_rd_socket_stub;
};
#endif // RIVIERA
#ifdef VCSSYSTEMC
#include "utils/xtlm_aximm_initiator_stub.h"
#include "utils/xtlm_aximm_target_stub.h"
class DllExport design_1_auto_us_df_1 : public design_1_auto_us_df_1_sc
{
public:
design_1_auto_us_df_1(const sc_core::sc_module_name& nm);
virtual ~design_1_auto_us_df_1();
// module pin-to-pin RTL interface
sc_core::sc_in< bool > s_axi_aclk;
sc_core::sc_in< bool > s_axi_aresetn;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awid;
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
sc_core::sc_in< bool > s_axi_awvalid;
sc_core::sc_out< bool > s_axi_awready;
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
sc_core::sc_in< bool > s_axi_wlast;
sc_core::sc_in< bool > s_axi_wvalid;
sc_core::sc_out< bool > s_axi_wready;
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_bid;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
sc_core::sc_out< bool > s_axi_bvalid;
sc_core::sc_in< bool > s_axi_bready;
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
sc_core::sc_out< bool > m_axi_awvalid;
sc_core::sc_in< bool > m_axi_awready;
sc_core::sc_out< sc_dt::sc_bv<256> > m_axi_wdata;
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wstrb;
sc_core::sc_out< bool > m_axi_wlast;
sc_core::sc_out< bool > m_axi_wvalid;
sc_core::sc_in< bool > m_axi_wready;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
sc_core::sc_in< bool > m_axi_bvalid;
sc_core::sc_out< bool > m_axi_bready;
protected:
virtual void before_end_of_elaboration();
private:
xtlm::xaximm_pin2xtlm_t<128,32,4,1,1,1,1,1>* mp_S_AXI_transactor;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
sc_signal< bool > m_s_axi_awlock_converter_signal;
sc_signal< bool > m_S_AXI_transactor_rst_signal;
xtlm::xaximm_xtlm2pin_t<256,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
sc_signal< bool > m_m_axi_awlock_converter_signal;
sc_signal< bool > m_M_AXI_transactor_rst_signal;
// Transactor stubs
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
// Socket stubs
xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_rd_socket_stub;
xtlm::xtlm_aximm_target_stub* mp_M_AXI_rd_socket_stub;
};
#endif // VCSSYSTEMC
#ifdef MTI_SYSTEMC
#include "utils/xtlm_aximm_initiator_stub.h"
#include "utils/xtlm_aximm_target_stub.h"
class DllExport design_1_auto_us_df_1 : public design_1_auto_us_df_1_sc
{
public:
design_1_auto_us_df_1(const sc_core::sc_module_name& nm);
virtual ~design_1_auto_us_df_1();
// module pin-to-pin RTL interface
sc_core::sc_in< bool > s_axi_aclk;
sc_core::sc_in< bool > s_axi_aresetn;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awid;
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
sc_core::sc_in< bool > s_axi_awvalid;
sc_core::sc_out< bool > s_axi_awready;
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
sc_core::sc_in< bool > s_axi_wlast;
sc_core::sc_in< bool > s_axi_wvalid;
sc_core::sc_out< bool > s_axi_wready;
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_bid;
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
sc_core::sc_out< bool > s_axi_bvalid;
sc_core::sc_in< bool > s_axi_bready;
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
sc_core::sc_out< bool > m_axi_awvalid;
sc_core::sc_in< bool > m_axi_awready;
sc_core::sc_out< sc_dt::sc_bv<256> > m_axi_wdata;
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wstrb;
sc_core::sc_out< bool > m_axi_wlast;
sc_core::sc_out< bool > m_axi_wvalid;
sc_core::sc_in< bool > m_axi_wready;
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
sc_core::sc_in< bool > m_axi_bvalid;
sc_core::sc_out< bool > m_axi_bready;
protected:
virtual void before_end_of_elaboration();
private:
xtlm::xaximm_pin2xtlm_t<128,32,4,1,1,1,1,1>* mp_S_AXI_transactor;
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
sc_signal< bool > m_s_axi_awlock_converter_signal;
sc_signal< bool > m_S_AXI_transactor_rst_signal;
xtlm::xaximm_xtlm2pin_t<256,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
sc_signal< bool > m_m_axi_awlock_converter_signal;
sc_signal< bool > m_M_AXI_transactor_rst_signal;
// Transactor stubs
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
// Socket stubs
xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_rd_socket_stub;
xtlm::xtlm_aximm_target_stub* mp_M_AXI_rd_socket_stub;
};
#endif // MTI_SYSTEMC
#endif // IP_DESIGN_1_AUTO_US_DF_1_H_

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Firmware/XDMA/FPGA_Module_Rev2_50T/FPGA_Module_Rev2_50T.ip_user_files/mem_init_files/design_1_auto_us_df_1_sc.h
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@ -1,95 +0,0 @@
#ifndef IP_DESIGN_1_AUTO_US_DF_1_SC_H_
#define IP_DESIGN_1_AUTO_US_DF_1_SC_H_
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef XTLM
#include "xtlm.h"
#endif
#ifndef SYSTEMC_INCLUDED
#include <systemc>
#endif
#if defined(_MSC_VER)
#define DllExport __declspec(dllexport)
#elif defined(__GNUC__)
#define DllExport __attribute__ ((visibility("default")))
#else
#define DllExport
#endif
class axi_dwidth_converter;
class DllExport design_1_auto_us_df_1_sc : public sc_core::sc_module
{
public:
design_1_auto_us_df_1_sc(const sc_core::sc_module_name& nm);
virtual ~design_1_auto_us_df_1_sc();
public: // module socket-to-socket TLM interface
xtlm::xtlm_aximm_target_socket* target_rd_socket;
xtlm::xtlm_aximm_target_socket* target_wr_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
protected:
axi_dwidth_converter* mp_impl;
private:
design_1_auto_us_df_1_sc(const design_1_auto_us_df_1_sc&);
const design_1_auto_us_df_1_sc& operator=(const design_1_auto_us_df_1_sc&);
};
#endif // IP_DESIGN_1_AUTO_US_DF_1_SC_H_

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