mirror of
https://github.com/EEVengers/ThunderScope.git
synced 2025-04-11 23:19:16 +00:00
attempt merge from master, minor fixes
This commit is contained in:
Ratan Varghese
commit
68f32911e8
.gitignore
Firmware/Artix7_PCIe/dso_top
Software/waveview
electron
scope_link
src
components
bottombar/subcomponents
graph
sidebar/widgets
configuration
css/sidebar/widgets
redux
initialStates
reducers
util
4
.gitignore
vendored
4
.gitignore
vendored
@ -28,3 +28,7 @@ Software/waveview/ZERO_CHECK.vcxproj.filters
|
||||
Software/waveview/ALL_BUILD.vcxproj.filters
|
||||
Software/waveview/cmake_install.cmake
|
||||
Software/waveview/CMakeCache.txt
|
||||
|
||||
# testing files
|
||||
|
||||
Software/waveview/dump.csv
|
||||
|
||||
Binary file not shown.
@ -12,7 +12,7 @@
|
||||
<Properties Property="PROGRAM.CFG_PROGRAM" value="1"/>
|
||||
<Properties Property="PROGRAM.CHECKSUM" value="0"/>
|
||||
<Properties Property="PROGRAM.ERASE" value="1"/>
|
||||
<Properties Property="PROGRAM.FILES" value="$_project_name_.runs/impl_1/dso_top.bin"/>
|
||||
<Properties Property="PROGRAM.FILES" value="$_project_name_.runs/impl_1/$_project_name_.bin"/>
|
||||
<Properties Property="PROGRAM.PRM_FILE" value=""/>
|
||||
<Properties Property="PROGRAM.UNUSED_PIN_TERMINATION" value="pull-none"/>
|
||||
<Properties Property="PROGRAM.VERIFY" value="1"/>
|
||||
@ -22,7 +22,7 @@
|
||||
<Object name="xc7a100t_0" gui_info="">
|
||||
<Properties Property="FULL_PROBES.FILE" value=""/>
|
||||
<Properties Property="PROBES.FILE" value=""/>
|
||||
<Properties Property="PROGRAM.HW_BITSTREAM" value=""/>
|
||||
<Properties Property="PROGRAM.HW_BITSTREAM" value="C:/Xilinx/Vivado/2020.1/data/xicom/cfgmem/bitfile/spi_xc7a100t_pullnone.bit"/>
|
||||
<Properties Property="PROGRAM.HW_CFGMEM_PART" value="s25fl256sxxxxxx0-spi-x1_x2_x4"/>
|
||||
<Properties Property="SLR.COUNT" value="1"/>
|
||||
</Object>
|
||||
|
||||
@ -1,939 +0,0 @@
|
||||
{
|
||||
"version": "1.0",
|
||||
"modules": {
|
||||
"bd_48ac": {
|
||||
"proto_instances": {
|
||||
"/m00_exit_pipeline/m00_exit/M_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "m_axi_araddr"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARPROT": { "actual": "m_axi_arprot"},
|
||||
"ARREADY": { "actual": "m_axi_arready"},
|
||||
"ARVALID": { "actual": "m_axi_arvalid"},
|
||||
"AWADDR": { "actual": "m_axi_awaddr"},
|
||||
"AWPROT": { "actual": "m_axi_awprot"},
|
||||
"AWREADY": { "actual": "m_axi_awready"},
|
||||
"AWVALID": { "actual": "m_axi_awvalid"},
|
||||
"BREADY": { "actual": "m_axi_bready"},
|
||||
"BRESP": { "actual": "m_axi_bresp"},
|
||||
"BVALID": { "actual": "m_axi_bvalid"},
|
||||
"RDATA": { "actual": "m_axi_rdata"},
|
||||
"RREADY": { "actual": "m_axi_rready"},
|
||||
"RRESP": { "actual": "m_axi_rresp"},
|
||||
"RVALID": { "actual": "m_axi_rvalid"},
|
||||
"WDATA": { "actual": "m_axi_wdata"},
|
||||
"WREADY": { "actual": "m_axi_wready"},
|
||||
"WSTRB": { "actual": "m_axi_wstrb"},
|
||||
"WVALID": { "actual": "m_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/m00_exit_pipeline/m00_exit/S_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "s_axi_araddr"},
|
||||
"ARCACHE": { "actual": "s_axi_arcache"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARID": { "actual": "s_axi_arid"},
|
||||
"ARLEN": { "actual": "s_axi_arlen"},
|
||||
"ARLOCK": { "actual": "s_axi_arlock"},
|
||||
"ARPROT": { "actual": "s_axi_arprot"},
|
||||
"ARQOS": { "actual": "s_axi_arqos"},
|
||||
"ARREADY": { "actual": "s_axi_arready"},
|
||||
"ARUSER": { "actual": "s_axi_aruser"},
|
||||
"ARVALID": { "actual": "s_axi_arvalid"},
|
||||
"AWADDR": { "actual": "s_axi_awaddr"},
|
||||
"AWCACHE": { "actual": "s_axi_awcache"},
|
||||
"AWID": { "actual": "s_axi_awid"},
|
||||
"AWLEN": { "actual": "s_axi_awlen"},
|
||||
"AWLOCK": { "actual": "s_axi_awlock"},
|
||||
"AWPROT": { "actual": "s_axi_awprot"},
|
||||
"AWQOS": { "actual": "s_axi_awqos"},
|
||||
"AWREADY": { "actual": "s_axi_awready"},
|
||||
"AWUSER": { "actual": "s_axi_awuser"},
|
||||
"AWVALID": { "actual": "s_axi_awvalid"},
|
||||
"BID": { "actual": "s_axi_bid"},
|
||||
"BREADY": { "actual": "s_axi_bready"},
|
||||
"BRESP": { "actual": "s_axi_bresp"},
|
||||
"BUSER": { "actual": "s_axi_buser"},
|
||||
"BVALID": { "actual": "s_axi_bvalid"},
|
||||
"RDATA": { "actual": "s_axi_rdata"},
|
||||
"RID": { "actual": "s_axi_rid"},
|
||||
"RLAST": { "actual": "s_axi_rlast"},
|
||||
"RREADY": { "actual": "s_axi_rready"},
|
||||
"RRESP": { "actual": "s_axi_rresp"},
|
||||
"RUSER": { "actual": "s_axi_ruser"},
|
||||
"RVALID": { "actual": "s_axi_rvalid"},
|
||||
"WDATA": { "actual": "s_axi_wdata"},
|
||||
"WLAST": { "actual": "s_axi_wlast"},
|
||||
"WREADY": { "actual": "s_axi_wready"},
|
||||
"WSTRB": { "actual": "s_axi_wstrb"},
|
||||
"WUSER": { "actual": "s_axi_wuser"},
|
||||
"WVALID": { "actual": "s_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/m00_exit_pipeline/m_axi": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "m_axi_araddr"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARPROT": { "actual": "m_axi_arprot"},
|
||||
"ARREADY": { "actual": "m_axi_arready"},
|
||||
"ARVALID": { "actual": "m_axi_arvalid"},
|
||||
"AWADDR": { "actual": "m_axi_awaddr"},
|
||||
"AWPROT": { "actual": "m_axi_awprot"},
|
||||
"AWREADY": { "actual": "m_axi_awready"},
|
||||
"AWVALID": { "actual": "m_axi_awvalid"},
|
||||
"BREADY": { "actual": "m_axi_bready"},
|
||||
"BRESP": { "actual": "m_axi_bresp"},
|
||||
"BVALID": { "actual": "m_axi_bvalid"},
|
||||
"RDATA": { "actual": "m_axi_rdata"},
|
||||
"RREADY": { "actual": "m_axi_rready"},
|
||||
"RRESP": { "actual": "m_axi_rresp"},
|
||||
"RVALID": { "actual": "m_axi_rvalid"},
|
||||
"WDATA": { "actual": "m_axi_wdata"},
|
||||
"WREADY": { "actual": "m_axi_wready"},
|
||||
"WSTRB": { "actual": "m_axi_wstrb"},
|
||||
"WVALID": { "actual": "m_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/m00_exit_pipeline/s_axi": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "s_axi_araddr"},
|
||||
"ARCACHE": { "actual": "s_axi_arcache"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARID": { "actual": "s_axi_arid[0:0]"},
|
||||
"ARLEN": { "actual": "s_axi_arlen"},
|
||||
"ARLOCK": { "actual": "s_axi_arlock"},
|
||||
"ARPROT": { "actual": "s_axi_arprot"},
|
||||
"ARQOS": { "actual": "s_axi_arqos"},
|
||||
"ARREADY": { "actual": "s_axi_arready"},
|
||||
"ARUSER": { "actual": "s_axi_aruser"},
|
||||
"ARVALID": { "actual": "s_axi_arvalid"},
|
||||
"AWADDR": { "actual": "s_axi_awaddr"},
|
||||
"AWCACHE": { "actual": "s_axi_awcache"},
|
||||
"AWID": { "actual": "s_axi_awid[0:0]"},
|
||||
"AWLEN": { "actual": "s_axi_awlen"},
|
||||
"AWLOCK": { "actual": "s_axi_awlock"},
|
||||
"AWPROT": { "actual": "s_axi_awprot"},
|
||||
"AWQOS": { "actual": "s_axi_awqos"},
|
||||
"AWREADY": { "actual": "s_axi_awready"},
|
||||
"AWUSER": { "actual": "s_axi_awuser"},
|
||||
"AWVALID": { "actual": "s_axi_awvalid"},
|
||||
"BID": { "actual": "s_axi_bid[0:0]"},
|
||||
"BREADY": { "actual": "s_axi_bready"},
|
||||
"BRESP": { "actual": "s_axi_bresp"},
|
||||
"BUSER": { "actual": "s_axi_buser"},
|
||||
"BVALID": { "actual": "s_axi_bvalid"},
|
||||
"RDATA": { "actual": "s_axi_rdata"},
|
||||
"RID": { "actual": "s_axi_rid[0:0]"},
|
||||
"RLAST": { "actual": "s_axi_rlast"},
|
||||
"RREADY": { "actual": "s_axi_rready"},
|
||||
"RRESP": { "actual": "s_axi_rresp"},
|
||||
"RUSER": { "actual": "s_axi_ruser"},
|
||||
"RVALID": { "actual": "s_axi_rvalid"},
|
||||
"WDATA": { "actual": "s_axi_wdata"},
|
||||
"WLAST": { "actual": "s_axi_wlast"},
|
||||
"WREADY": { "actual": "s_axi_wready"},
|
||||
"WSTRB": { "actual": "s_axi_wstrb"},
|
||||
"WUSER": { "actual": "s_axi_wuser"},
|
||||
"WVALID": { "actual": "s_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/m00_sc2axi/M_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "m_axi_araddr"},
|
||||
"ARCACHE": { "actual": "m_axi_arcache"},
|
||||
"ARID": { "actual": "m_axi_arid"},
|
||||
"ARLEN": { "actual": "m_axi_arlen"},
|
||||
"ARLOCK": { "actual": "m_axi_arlock"},
|
||||
"ARPROT": { "actual": "m_axi_arprot"},
|
||||
"ARQOS": { "actual": "m_axi_arqos"},
|
||||
"ARREADY": { "actual": "m_axi_arready"},
|
||||
"ARUSER": { "actual": "m_axi_aruser"},
|
||||
"ARVALID": { "actual": "m_axi_arvalid"},
|
||||
"AWADDR": { "actual": "m_axi_awaddr"},
|
||||
"AWCACHE": { "actual": "m_axi_awcache"},
|
||||
"AWID": { "actual": "m_axi_awid"},
|
||||
"AWLEN": { "actual": "m_axi_awlen"},
|
||||
"AWLOCK": { "actual": "m_axi_awlock"},
|
||||
"AWPROT": { "actual": "m_axi_awprot"},
|
||||
"AWQOS": { "actual": "m_axi_awqos"},
|
||||
"AWREADY": { "actual": "m_axi_awready"},
|
||||
"AWUSER": { "actual": "m_axi_awuser"},
|
||||
"AWVALID": { "actual": "m_axi_awvalid"},
|
||||
"BID": { "actual": "m_axi_bid"},
|
||||
"BREADY": { "actual": "m_axi_bready"},
|
||||
"BRESP": { "actual": "m_axi_bresp"},
|
||||
"BUSER": { "actual": "m_axi_buser"},
|
||||
"BVALID": { "actual": "m_axi_bvalid"},
|
||||
"RDATA": { "actual": "m_axi_rdata"},
|
||||
"RID": { "actual": "m_axi_rid"},
|
||||
"RLAST": { "actual": "m_axi_rlast"},
|
||||
"RREADY": { "actual": "m_axi_rready"},
|
||||
"RRESP": { "actual": "m_axi_rresp"},
|
||||
"RUSER": { "actual": "m_axi_ruser"},
|
||||
"RVALID": { "actual": "m_axi_rvalid"},
|
||||
"WDATA": { "actual": "m_axi_wdata"},
|
||||
"WLAST": { "actual": "m_axi_wlast"},
|
||||
"WREADY": { "actual": "m_axi_wready"},
|
||||
"WSTRB": { "actual": "m_axi_wstrb"},
|
||||
"WUSER": { "actual": "m_axi_wuser"},
|
||||
"WVALID": { "actual": "m_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/m01_exit_pipeline/m01_exit/M_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "m_axi_araddr"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARPROT": { "actual": "m_axi_arprot"},
|
||||
"ARREADY": { "actual": "m_axi_arready"},
|
||||
"ARVALID": { "actual": "m_axi_arvalid"},
|
||||
"AWADDR": { "actual": "m_axi_awaddr"},
|
||||
"AWPROT": { "actual": "m_axi_awprot"},
|
||||
"AWREADY": { "actual": "m_axi_awready"},
|
||||
"AWVALID": { "actual": "m_axi_awvalid"},
|
||||
"BREADY": { "actual": "m_axi_bready"},
|
||||
"BRESP": { "actual": "m_axi_bresp"},
|
||||
"BVALID": { "actual": "m_axi_bvalid"},
|
||||
"RDATA": { "actual": "m_axi_rdata"},
|
||||
"RREADY": { "actual": "m_axi_rready"},
|
||||
"RRESP": { "actual": "m_axi_rresp"},
|
||||
"RVALID": { "actual": "m_axi_rvalid"},
|
||||
"WDATA": { "actual": "m_axi_wdata"},
|
||||
"WREADY": { "actual": "m_axi_wready"},
|
||||
"WSTRB": { "actual": "m_axi_wstrb"},
|
||||
"WVALID": { "actual": "m_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/m01_exit_pipeline/m01_exit/S_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "s_axi_araddr"},
|
||||
"ARCACHE": { "actual": "s_axi_arcache"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARID": { "actual": "s_axi_arid"},
|
||||
"ARLEN": { "actual": "s_axi_arlen"},
|
||||
"ARLOCK": { "actual": "s_axi_arlock"},
|
||||
"ARPROT": { "actual": "s_axi_arprot"},
|
||||
"ARQOS": { "actual": "s_axi_arqos"},
|
||||
"ARREADY": { "actual": "s_axi_arready"},
|
||||
"ARUSER": { "actual": "s_axi_aruser"},
|
||||
"ARVALID": { "actual": "s_axi_arvalid"},
|
||||
"AWADDR": { "actual": "s_axi_awaddr"},
|
||||
"AWCACHE": { "actual": "s_axi_awcache"},
|
||||
"AWID": { "actual": "s_axi_awid"},
|
||||
"AWLEN": { "actual": "s_axi_awlen"},
|
||||
"AWLOCK": { "actual": "s_axi_awlock"},
|
||||
"AWPROT": { "actual": "s_axi_awprot"},
|
||||
"AWQOS": { "actual": "s_axi_awqos"},
|
||||
"AWREADY": { "actual": "s_axi_awready"},
|
||||
"AWUSER": { "actual": "s_axi_awuser"},
|
||||
"AWVALID": { "actual": "s_axi_awvalid"},
|
||||
"BID": { "actual": "s_axi_bid"},
|
||||
"BREADY": { "actual": "s_axi_bready"},
|
||||
"BRESP": { "actual": "s_axi_bresp"},
|
||||
"BUSER": { "actual": "s_axi_buser"},
|
||||
"BVALID": { "actual": "s_axi_bvalid"},
|
||||
"RDATA": { "actual": "s_axi_rdata"},
|
||||
"RID": { "actual": "s_axi_rid"},
|
||||
"RLAST": { "actual": "s_axi_rlast"},
|
||||
"RREADY": { "actual": "s_axi_rready"},
|
||||
"RRESP": { "actual": "s_axi_rresp"},
|
||||
"RUSER": { "actual": "s_axi_ruser"},
|
||||
"RVALID": { "actual": "s_axi_rvalid"},
|
||||
"WDATA": { "actual": "s_axi_wdata"},
|
||||
"WLAST": { "actual": "s_axi_wlast"},
|
||||
"WREADY": { "actual": "s_axi_wready"},
|
||||
"WSTRB": { "actual": "s_axi_wstrb"},
|
||||
"WUSER": { "actual": "s_axi_wuser"},
|
||||
"WVALID": { "actual": "s_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/m01_exit_pipeline/m_axi": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "m_axi_araddr"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARPROT": { "actual": "m_axi_arprot"},
|
||||
"ARREADY": { "actual": "m_axi_arready"},
|
||||
"ARVALID": { "actual": "m_axi_arvalid"},
|
||||
"AWADDR": { "actual": "m_axi_awaddr"},
|
||||
"AWPROT": { "actual": "m_axi_awprot"},
|
||||
"AWREADY": { "actual": "m_axi_awready"},
|
||||
"AWVALID": { "actual": "m_axi_awvalid"},
|
||||
"BREADY": { "actual": "m_axi_bready"},
|
||||
"BRESP": { "actual": "m_axi_bresp"},
|
||||
"BVALID": { "actual": "m_axi_bvalid"},
|
||||
"RDATA": { "actual": "m_axi_rdata"},
|
||||
"RREADY": { "actual": "m_axi_rready"},
|
||||
"RRESP": { "actual": "m_axi_rresp"},
|
||||
"RVALID": { "actual": "m_axi_rvalid"},
|
||||
"WDATA": { "actual": "m_axi_wdata"},
|
||||
"WREADY": { "actual": "m_axi_wready"},
|
||||
"WSTRB": { "actual": "m_axi_wstrb"},
|
||||
"WVALID": { "actual": "m_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/m01_exit_pipeline/s_axi": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "s_axi_araddr"},
|
||||
"ARCACHE": { "actual": "s_axi_arcache"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARID": { "actual": "s_axi_arid[0:0]"},
|
||||
"ARLEN": { "actual": "s_axi_arlen"},
|
||||
"ARLOCK": { "actual": "s_axi_arlock"},
|
||||
"ARPROT": { "actual": "s_axi_arprot"},
|
||||
"ARQOS": { "actual": "s_axi_arqos"},
|
||||
"ARREADY": { "actual": "s_axi_arready"},
|
||||
"ARUSER": { "actual": "s_axi_aruser"},
|
||||
"ARVALID": { "actual": "s_axi_arvalid"},
|
||||
"AWADDR": { "actual": "s_axi_awaddr"},
|
||||
"AWCACHE": { "actual": "s_axi_awcache"},
|
||||
"AWID": { "actual": "s_axi_awid[0:0]"},
|
||||
"AWLEN": { "actual": "s_axi_awlen"},
|
||||
"AWLOCK": { "actual": "s_axi_awlock"},
|
||||
"AWPROT": { "actual": "s_axi_awprot"},
|
||||
"AWQOS": { "actual": "s_axi_awqos"},
|
||||
"AWREADY": { "actual": "s_axi_awready"},
|
||||
"AWUSER": { "actual": "s_axi_awuser"},
|
||||
"AWVALID": { "actual": "s_axi_awvalid"},
|
||||
"BID": { "actual": "s_axi_bid[0:0]"},
|
||||
"BREADY": { "actual": "s_axi_bready"},
|
||||
"BRESP": { "actual": "s_axi_bresp"},
|
||||
"BUSER": { "actual": "s_axi_buser"},
|
||||
"BVALID": { "actual": "s_axi_bvalid"},
|
||||
"RDATA": { "actual": "s_axi_rdata"},
|
||||
"RID": { "actual": "s_axi_rid[0:0]"},
|
||||
"RLAST": { "actual": "s_axi_rlast"},
|
||||
"RREADY": { "actual": "s_axi_rready"},
|
||||
"RRESP": { "actual": "s_axi_rresp"},
|
||||
"RUSER": { "actual": "s_axi_ruser"},
|
||||
"RVALID": { "actual": "s_axi_rvalid"},
|
||||
"WDATA": { "actual": "s_axi_wdata"},
|
||||
"WLAST": { "actual": "s_axi_wlast"},
|
||||
"WREADY": { "actual": "s_axi_wready"},
|
||||
"WSTRB": { "actual": "s_axi_wstrb"},
|
||||
"WUSER": { "actual": "s_axi_wuser"},
|
||||
"WVALID": { "actual": "s_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/m01_sc2axi/M_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "m_axi_araddr"},
|
||||
"ARCACHE": { "actual": "m_axi_arcache"},
|
||||
"ARID": { "actual": "m_axi_arid"},
|
||||
"ARLEN": { "actual": "m_axi_arlen"},
|
||||
"ARLOCK": { "actual": "m_axi_arlock"},
|
||||
"ARPROT": { "actual": "m_axi_arprot"},
|
||||
"ARQOS": { "actual": "m_axi_arqos"},
|
||||
"ARREADY": { "actual": "m_axi_arready"},
|
||||
"ARUSER": { "actual": "m_axi_aruser"},
|
||||
"ARVALID": { "actual": "m_axi_arvalid"},
|
||||
"AWADDR": { "actual": "m_axi_awaddr"},
|
||||
"AWCACHE": { "actual": "m_axi_awcache"},
|
||||
"AWID": { "actual": "m_axi_awid"},
|
||||
"AWLEN": { "actual": "m_axi_awlen"},
|
||||
"AWLOCK": { "actual": "m_axi_awlock"},
|
||||
"AWPROT": { "actual": "m_axi_awprot"},
|
||||
"AWQOS": { "actual": "m_axi_awqos"},
|
||||
"AWREADY": { "actual": "m_axi_awready"},
|
||||
"AWUSER": { "actual": "m_axi_awuser"},
|
||||
"AWVALID": { "actual": "m_axi_awvalid"},
|
||||
"BID": { "actual": "m_axi_bid"},
|
||||
"BREADY": { "actual": "m_axi_bready"},
|
||||
"BRESP": { "actual": "m_axi_bresp"},
|
||||
"BUSER": { "actual": "m_axi_buser"},
|
||||
"BVALID": { "actual": "m_axi_bvalid"},
|
||||
"RDATA": { "actual": "m_axi_rdata"},
|
||||
"RID": { "actual": "m_axi_rid"},
|
||||
"RLAST": { "actual": "m_axi_rlast"},
|
||||
"RREADY": { "actual": "m_axi_rready"},
|
||||
"RRESP": { "actual": "m_axi_rresp"},
|
||||
"RUSER": { "actual": "m_axi_ruser"},
|
||||
"RVALID": { "actual": "m_axi_rvalid"},
|
||||
"WDATA": { "actual": "m_axi_wdata"},
|
||||
"WLAST": { "actual": "m_axi_wlast"},
|
||||
"WREADY": { "actual": "m_axi_wready"},
|
||||
"WSTRB": { "actual": "m_axi_wstrb"},
|
||||
"WUSER": { "actual": "m_axi_wuser"},
|
||||
"WVALID": { "actual": "m_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/m02_exit_pipeline/m02_exit/M_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "m_axi_araddr"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARPROT": { "actual": "m_axi_arprot"},
|
||||
"ARREADY": { "actual": "m_axi_arready"},
|
||||
"ARVALID": { "actual": "m_axi_arvalid"},
|
||||
"AWADDR": { "actual": "m_axi_awaddr"},
|
||||
"AWPROT": { "actual": "m_axi_awprot"},
|
||||
"AWREADY": { "actual": "m_axi_awready"},
|
||||
"AWVALID": { "actual": "m_axi_awvalid"},
|
||||
"BREADY": { "actual": "m_axi_bready"},
|
||||
"BRESP": { "actual": "m_axi_bresp"},
|
||||
"BVALID": { "actual": "m_axi_bvalid"},
|
||||
"RDATA": { "actual": "m_axi_rdata"},
|
||||
"RREADY": { "actual": "m_axi_rready"},
|
||||
"RRESP": { "actual": "m_axi_rresp"},
|
||||
"RVALID": { "actual": "m_axi_rvalid"},
|
||||
"WDATA": { "actual": "m_axi_wdata"},
|
||||
"WREADY": { "actual": "m_axi_wready"},
|
||||
"WSTRB": { "actual": "m_axi_wstrb"},
|
||||
"WVALID": { "actual": "m_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/m02_exit_pipeline/m02_exit/S_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "s_axi_araddr"},
|
||||
"ARCACHE": { "actual": "s_axi_arcache"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARID": { "actual": "s_axi_arid"},
|
||||
"ARLEN": { "actual": "s_axi_arlen"},
|
||||
"ARLOCK": { "actual": "s_axi_arlock"},
|
||||
"ARPROT": { "actual": "s_axi_arprot"},
|
||||
"ARQOS": { "actual": "s_axi_arqos"},
|
||||
"ARREADY": { "actual": "s_axi_arready"},
|
||||
"ARUSER": { "actual": "s_axi_aruser"},
|
||||
"ARVALID": { "actual": "s_axi_arvalid"},
|
||||
"AWADDR": { "actual": "s_axi_awaddr"},
|
||||
"AWCACHE": { "actual": "s_axi_awcache"},
|
||||
"AWID": { "actual": "s_axi_awid"},
|
||||
"AWLEN": { "actual": "s_axi_awlen"},
|
||||
"AWLOCK": { "actual": "s_axi_awlock"},
|
||||
"AWPROT": { "actual": "s_axi_awprot"},
|
||||
"AWQOS": { "actual": "s_axi_awqos"},
|
||||
"AWREADY": { "actual": "s_axi_awready"},
|
||||
"AWUSER": { "actual": "s_axi_awuser"},
|
||||
"AWVALID": { "actual": "s_axi_awvalid"},
|
||||
"BID": { "actual": "s_axi_bid"},
|
||||
"BREADY": { "actual": "s_axi_bready"},
|
||||
"BRESP": { "actual": "s_axi_bresp"},
|
||||
"BUSER": { "actual": "s_axi_buser"},
|
||||
"BVALID": { "actual": "s_axi_bvalid"},
|
||||
"RDATA": { "actual": "s_axi_rdata"},
|
||||
"RID": { "actual": "s_axi_rid"},
|
||||
"RLAST": { "actual": "s_axi_rlast"},
|
||||
"RREADY": { "actual": "s_axi_rready"},
|
||||
"RRESP": { "actual": "s_axi_rresp"},
|
||||
"RUSER": { "actual": "s_axi_ruser"},
|
||||
"RVALID": { "actual": "s_axi_rvalid"},
|
||||
"WDATA": { "actual": "s_axi_wdata"},
|
||||
"WLAST": { "actual": "s_axi_wlast"},
|
||||
"WREADY": { "actual": "s_axi_wready"},
|
||||
"WSTRB": { "actual": "s_axi_wstrb"},
|
||||
"WUSER": { "actual": "s_axi_wuser"},
|
||||
"WVALID": { "actual": "s_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/m02_exit_pipeline/m_axi": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "m_axi_araddr"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARPROT": { "actual": "m_axi_arprot"},
|
||||
"ARREADY": { "actual": "m_axi_arready"},
|
||||
"ARVALID": { "actual": "m_axi_arvalid"},
|
||||
"AWADDR": { "actual": "m_axi_awaddr"},
|
||||
"AWPROT": { "actual": "m_axi_awprot"},
|
||||
"AWREADY": { "actual": "m_axi_awready"},
|
||||
"AWVALID": { "actual": "m_axi_awvalid"},
|
||||
"BREADY": { "actual": "m_axi_bready"},
|
||||
"BRESP": { "actual": "m_axi_bresp"},
|
||||
"BVALID": { "actual": "m_axi_bvalid"},
|
||||
"RDATA": { "actual": "m_axi_rdata"},
|
||||
"RREADY": { "actual": "m_axi_rready"},
|
||||
"RRESP": { "actual": "m_axi_rresp"},
|
||||
"RVALID": { "actual": "m_axi_rvalid"},
|
||||
"WDATA": { "actual": "m_axi_wdata"},
|
||||
"WREADY": { "actual": "m_axi_wready"},
|
||||
"WSTRB": { "actual": "m_axi_wstrb"},
|
||||
"WVALID": { "actual": "m_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/m02_exit_pipeline/s_axi": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "s_axi_araddr"},
|
||||
"ARCACHE": { "actual": "s_axi_arcache"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARID": { "actual": "s_axi_arid[0:0]"},
|
||||
"ARLEN": { "actual": "s_axi_arlen"},
|
||||
"ARLOCK": { "actual": "s_axi_arlock"},
|
||||
"ARPROT": { "actual": "s_axi_arprot"},
|
||||
"ARQOS": { "actual": "s_axi_arqos"},
|
||||
"ARREADY": { "actual": "s_axi_arready"},
|
||||
"ARUSER": { "actual": "s_axi_aruser"},
|
||||
"ARVALID": { "actual": "s_axi_arvalid"},
|
||||
"AWADDR": { "actual": "s_axi_awaddr"},
|
||||
"AWCACHE": { "actual": "s_axi_awcache"},
|
||||
"AWID": { "actual": "s_axi_awid[0:0]"},
|
||||
"AWLEN": { "actual": "s_axi_awlen"},
|
||||
"AWLOCK": { "actual": "s_axi_awlock"},
|
||||
"AWPROT": { "actual": "s_axi_awprot"},
|
||||
"AWQOS": { "actual": "s_axi_awqos"},
|
||||
"AWREADY": { "actual": "s_axi_awready"},
|
||||
"AWUSER": { "actual": "s_axi_awuser"},
|
||||
"AWVALID": { "actual": "s_axi_awvalid"},
|
||||
"BID": { "actual": "s_axi_bid[0:0]"},
|
||||
"BREADY": { "actual": "s_axi_bready"},
|
||||
"BRESP": { "actual": "s_axi_bresp"},
|
||||
"BUSER": { "actual": "s_axi_buser"},
|
||||
"BVALID": { "actual": "s_axi_bvalid"},
|
||||
"RDATA": { "actual": "s_axi_rdata"},
|
||||
"RID": { "actual": "s_axi_rid[0:0]"},
|
||||
"RLAST": { "actual": "s_axi_rlast"},
|
||||
"RREADY": { "actual": "s_axi_rready"},
|
||||
"RRESP": { "actual": "s_axi_rresp"},
|
||||
"RUSER": { "actual": "s_axi_ruser"},
|
||||
"RVALID": { "actual": "s_axi_rvalid"},
|
||||
"WDATA": { "actual": "s_axi_wdata"},
|
||||
"WLAST": { "actual": "s_axi_wlast"},
|
||||
"WREADY": { "actual": "s_axi_wready"},
|
||||
"WSTRB": { "actual": "s_axi_wstrb"},
|
||||
"WUSER": { "actual": "s_axi_wuser"},
|
||||
"WVALID": { "actual": "s_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/m02_sc2axi/M_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "m_axi_araddr"},
|
||||
"ARCACHE": { "actual": "m_axi_arcache"},
|
||||
"ARID": { "actual": "m_axi_arid"},
|
||||
"ARLEN": { "actual": "m_axi_arlen"},
|
||||
"ARLOCK": { "actual": "m_axi_arlock"},
|
||||
"ARPROT": { "actual": "m_axi_arprot"},
|
||||
"ARQOS": { "actual": "m_axi_arqos"},
|
||||
"ARREADY": { "actual": "m_axi_arready"},
|
||||
"ARUSER": { "actual": "m_axi_aruser"},
|
||||
"ARVALID": { "actual": "m_axi_arvalid"},
|
||||
"AWADDR": { "actual": "m_axi_awaddr"},
|
||||
"AWCACHE": { "actual": "m_axi_awcache"},
|
||||
"AWID": { "actual": "m_axi_awid"},
|
||||
"AWLEN": { "actual": "m_axi_awlen"},
|
||||
"AWLOCK": { "actual": "m_axi_awlock"},
|
||||
"AWPROT": { "actual": "m_axi_awprot"},
|
||||
"AWQOS": { "actual": "m_axi_awqos"},
|
||||
"AWREADY": { "actual": "m_axi_awready"},
|
||||
"AWUSER": { "actual": "m_axi_awuser"},
|
||||
"AWVALID": { "actual": "m_axi_awvalid"},
|
||||
"BID": { "actual": "m_axi_bid"},
|
||||
"BREADY": { "actual": "m_axi_bready"},
|
||||
"BRESP": { "actual": "m_axi_bresp"},
|
||||
"BUSER": { "actual": "m_axi_buser"},
|
||||
"BVALID": { "actual": "m_axi_bvalid"},
|
||||
"RDATA": { "actual": "m_axi_rdata"},
|
||||
"RID": { "actual": "m_axi_rid"},
|
||||
"RLAST": { "actual": "m_axi_rlast"},
|
||||
"RREADY": { "actual": "m_axi_rready"},
|
||||
"RRESP": { "actual": "m_axi_rresp"},
|
||||
"RUSER": { "actual": "m_axi_ruser"},
|
||||
"RVALID": { "actual": "m_axi_rvalid"},
|
||||
"WDATA": { "actual": "m_axi_wdata"},
|
||||
"WLAST": { "actual": "m_axi_wlast"},
|
||||
"WREADY": { "actual": "m_axi_wready"},
|
||||
"WSTRB": { "actual": "m_axi_wstrb"},
|
||||
"WUSER": { "actual": "m_axi_wuser"},
|
||||
"WVALID": { "actual": "m_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/s00_axi2sc/S_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "s_axi_araddr"},
|
||||
"ARCACHE": { "actual": "s_axi_arcache"},
|
||||
"ARID": { "actual": "s_axi_arid"},
|
||||
"ARLEN": { "actual": "s_axi_arlen"},
|
||||
"ARLOCK": { "actual": "s_axi_arlock"},
|
||||
"ARPROT": { "actual": "s_axi_arprot"},
|
||||
"ARQOS": { "actual": "s_axi_arqos"},
|
||||
"ARREADY": { "actual": "s_axi_arready"},
|
||||
"ARUSER": { "actual": "s_axi_aruser"},
|
||||
"ARVALID": { "actual": "s_axi_arvalid"},
|
||||
"AWADDR": { "actual": "s_axi_awaddr"},
|
||||
"AWCACHE": { "actual": "s_axi_awcache"},
|
||||
"AWID": { "actual": "s_axi_awid"},
|
||||
"AWLEN": { "actual": "s_axi_awlen"},
|
||||
"AWLOCK": { "actual": "s_axi_awlock"},
|
||||
"AWPROT": { "actual": "s_axi_awprot"},
|
||||
"AWQOS": { "actual": "s_axi_awqos"},
|
||||
"AWREADY": { "actual": "s_axi_awready"},
|
||||
"AWUSER": { "actual": "s_axi_awuser"},
|
||||
"AWVALID": { "actual": "s_axi_awvalid"},
|
||||
"BID": { "actual": "s_axi_bid"},
|
||||
"BREADY": { "actual": "s_axi_bready"},
|
||||
"BRESP": { "actual": "s_axi_bresp"},
|
||||
"BUSER": { "actual": "s_axi_buser"},
|
||||
"BVALID": { "actual": "s_axi_bvalid"},
|
||||
"RDATA": { "actual": "s_axi_rdata"},
|
||||
"RID": { "actual": "s_axi_rid"},
|
||||
"RLAST": { "actual": "s_axi_rlast"},
|
||||
"RREADY": { "actual": "s_axi_rready"},
|
||||
"RRESP": { "actual": "s_axi_rresp"},
|
||||
"RUSER": { "actual": "s_axi_ruser"},
|
||||
"RVALID": { "actual": "s_axi_rvalid"},
|
||||
"WDATA": { "actual": "s_axi_wdata"},
|
||||
"WLAST": { "actual": "s_axi_wlast"},
|
||||
"WREADY": { "actual": "s_axi_wready"},
|
||||
"WSTRB": { "actual": "s_axi_wstrb"},
|
||||
"WUSER": { "actual": "s_axi_wuser"},
|
||||
"WVALID": { "actual": "s_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/s00_entry_pipeline/m_axi": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "m_axi_araddr"},
|
||||
"ARCACHE": { "actual": "m_axi_arcache"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARID": { "actual": "m_axi_arid[0:0]"},
|
||||
"ARLEN": { "actual": "m_axi_arlen"},
|
||||
"ARLOCK": { "actual": "m_axi_arlock"},
|
||||
"ARPROT": { "actual": "m_axi_arprot"},
|
||||
"ARQOS": { "actual": "m_axi_arqos"},
|
||||
"ARREADY": { "actual": "m_axi_arready"},
|
||||
"ARUSER": { "actual": "m_axi_aruser"},
|
||||
"ARVALID": { "actual": "m_axi_arvalid"},
|
||||
"AWADDR": { "actual": "m_axi_awaddr"},
|
||||
"AWCACHE": { "actual": "m_axi_awcache"},
|
||||
"AWID": { "actual": "m_axi_awid[0:0]"},
|
||||
"AWLEN": { "actual": "m_axi_awlen"},
|
||||
"AWLOCK": { "actual": "m_axi_awlock"},
|
||||
"AWPROT": { "actual": "m_axi_awprot"},
|
||||
"AWQOS": { "actual": "m_axi_awqos"},
|
||||
"AWREADY": { "actual": "m_axi_awready"},
|
||||
"AWUSER": { "actual": "m_axi_awuser"},
|
||||
"AWVALID": { "actual": "m_axi_awvalid"},
|
||||
"BID": { "actual": "m_axi_bid[0:0]"},
|
||||
"BREADY": { "actual": "m_axi_bready"},
|
||||
"BRESP": { "actual": "m_axi_bresp"},
|
||||
"BUSER": { "actual": "m_axi_buser"},
|
||||
"BVALID": { "actual": "m_axi_bvalid"},
|
||||
"RDATA": { "actual": "m_axi_rdata"},
|
||||
"RID": { "actual": "m_axi_rid[0:0]"},
|
||||
"RLAST": { "actual": "m_axi_rlast"},
|
||||
"RREADY": { "actual": "m_axi_rready"},
|
||||
"RRESP": { "actual": "m_axi_rresp"},
|
||||
"RUSER": { "actual": "m_axi_ruser"},
|
||||
"RVALID": { "actual": "m_axi_rvalid"},
|
||||
"WDATA": { "actual": "m_axi_wdata"},
|
||||
"WLAST": { "actual": "m_axi_wlast"},
|
||||
"WREADY": { "actual": "m_axi_wready"},
|
||||
"WSTRB": { "actual": "m_axi_wstrb"},
|
||||
"WUSER": { "actual": "m_axi_wuser"},
|
||||
"WVALID": { "actual": "m_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/s00_entry_pipeline/s00_mmu/M_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "m_axi_araddr"},
|
||||
"ARBURST": { "actual": "m_axi_arburst"},
|
||||
"ARCACHE": { "actual": "m_axi_arcache"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARLEN": { "actual": "m_axi_arlen"},
|
||||
"ARLOCK": { "actual": "m_axi_arlock"},
|
||||
"ARPROT": { "actual": "m_axi_arprot"},
|
||||
"ARQOS": { "actual": "m_axi_arqos"},
|
||||
"ARREADY": { "actual": "m_axi_arready"},
|
||||
"ARSIZE": { "actual": "m_axi_arsize"},
|
||||
"ARUSER": { "actual": "m_axi_aruser"},
|
||||
"ARVALID": { "actual": "m_axi_arvalid"},
|
||||
"AWADDR": { "actual": "m_axi_awaddr"},
|
||||
"AWBURST": { "actual": "m_axi_awburst"},
|
||||
"AWCACHE": { "actual": "m_axi_awcache"},
|
||||
"AWLEN": { "actual": "m_axi_awlen"},
|
||||
"AWLOCK": { "actual": "m_axi_awlock"},
|
||||
"AWPROT": { "actual": "m_axi_awprot"},
|
||||
"AWQOS": { "actual": "m_axi_awqos"},
|
||||
"AWREADY": { "actual": "m_axi_awready"},
|
||||
"AWSIZE": { "actual": "m_axi_awsize"},
|
||||
"AWUSER": { "actual": "m_axi_awuser"},
|
||||
"AWVALID": { "actual": "m_axi_awvalid"},
|
||||
"BREADY": { "actual": "m_axi_bready"},
|
||||
"BRESP": { "actual": "m_axi_bresp"},
|
||||
"BUSER": { "actual": "m_axi_buser"},
|
||||
"BVALID": { "actual": "m_axi_bvalid"},
|
||||
"RDATA": { "actual": "m_axi_rdata"},
|
||||
"RLAST": { "actual": "m_axi_rlast"},
|
||||
"RREADY": { "actual": "m_axi_rready"},
|
||||
"RRESP": { "actual": "m_axi_rresp"},
|
||||
"RUSER": { "actual": "m_axi_ruser"},
|
||||
"RVALID": { "actual": "m_axi_rvalid"},
|
||||
"WDATA": { "actual": "m_axi_wdata"},
|
||||
"WLAST": { "actual": "m_axi_wlast"},
|
||||
"WREADY": { "actual": "m_axi_wready"},
|
||||
"WSTRB": { "actual": "m_axi_wstrb"},
|
||||
"WUSER": { "actual": "m_axi_wuser"},
|
||||
"WVALID": { "actual": "m_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/s00_entry_pipeline/s00_mmu/S_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "s_axi_araddr"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARPROT": { "actual": "s_axi_arprot"},
|
||||
"ARREADY": { "actual": "s_axi_arready"},
|
||||
"ARVALID": { "actual": "s_axi_arvalid"},
|
||||
"AWADDR": { "actual": "s_axi_awaddr"},
|
||||
"AWPROT": { "actual": "s_axi_awprot"},
|
||||
"AWREADY": { "actual": "s_axi_awready"},
|
||||
"AWVALID": { "actual": "s_axi_awvalid"},
|
||||
"BREADY": { "actual": "s_axi_bready"},
|
||||
"BRESP": { "actual": "s_axi_bresp"},
|
||||
"BVALID": { "actual": "s_axi_bvalid"},
|
||||
"RDATA": { "actual": "s_axi_rdata"},
|
||||
"RREADY": { "actual": "s_axi_rready"},
|
||||
"RRESP": { "actual": "s_axi_rresp"},
|
||||
"RVALID": { "actual": "s_axi_rvalid"},
|
||||
"WDATA": { "actual": "s_axi_wdata"},
|
||||
"WREADY": { "actual": "s_axi_wready"},
|
||||
"WSTRB": { "actual": "s_axi_wstrb"},
|
||||
"WVALID": { "actual": "s_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/s00_entry_pipeline/s00_si_converter/M_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "m_axi_araddr"},
|
||||
"ARCACHE": { "actual": "m_axi_arcache"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARID": { "actual": "m_axi_arid"},
|
||||
"ARLEN": { "actual": "m_axi_arlen"},
|
||||
"ARLOCK": { "actual": "m_axi_arlock"},
|
||||
"ARPROT": { "actual": "m_axi_arprot"},
|
||||
"ARQOS": { "actual": "m_axi_arqos"},
|
||||
"ARREADY": { "actual": "m_axi_arready"},
|
||||
"ARUSER": { "actual": "m_axi_aruser"},
|
||||
"ARVALID": { "actual": "m_axi_arvalid"},
|
||||
"AWADDR": { "actual": "m_axi_awaddr"},
|
||||
"AWCACHE": { "actual": "m_axi_awcache"},
|
||||
"AWID": { "actual": "m_axi_awid"},
|
||||
"AWLEN": { "actual": "m_axi_awlen"},
|
||||
"AWLOCK": { "actual": "m_axi_awlock"},
|
||||
"AWPROT": { "actual": "m_axi_awprot"},
|
||||
"AWQOS": { "actual": "m_axi_awqos"},
|
||||
"AWREADY": { "actual": "m_axi_awready"},
|
||||
"AWUSER": { "actual": "m_axi_awuser"},
|
||||
"AWVALID": { "actual": "m_axi_awvalid"},
|
||||
"BID": { "actual": "m_axi_bid"},
|
||||
"BREADY": { "actual": "m_axi_bready"},
|
||||
"BRESP": { "actual": "m_axi_bresp"},
|
||||
"BUSER": { "actual": "m_axi_buser"},
|
||||
"BVALID": { "actual": "m_axi_bvalid"},
|
||||
"RDATA": { "actual": "m_axi_rdata"},
|
||||
"RID": { "actual": "m_axi_rid"},
|
||||
"RLAST": { "actual": "m_axi_rlast"},
|
||||
"RREADY": { "actual": "m_axi_rready"},
|
||||
"RRESP": { "actual": "m_axi_rresp"},
|
||||
"RUSER": { "actual": "m_axi_ruser"},
|
||||
"RVALID": { "actual": "m_axi_rvalid"},
|
||||
"WDATA": { "actual": "m_axi_wdata"},
|
||||
"WLAST": { "actual": "m_axi_wlast"},
|
||||
"WREADY": { "actual": "m_axi_wready"},
|
||||
"WSTRB": { "actual": "m_axi_wstrb"},
|
||||
"WUSER": { "actual": "m_axi_wuser"},
|
||||
"WVALID": { "actual": "m_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/s00_entry_pipeline/s00_si_converter/S_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "s_axi_araddr"},
|
||||
"ARCACHE": { "actual": "s_axi_arcache"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARID": { "actual": "s_axi_arid"},
|
||||
"ARLEN": { "actual": "s_axi_arlen"},
|
||||
"ARLOCK": { "actual": "s_axi_arlock"},
|
||||
"ARPROT": { "actual": "s_axi_arprot"},
|
||||
"ARQOS": { "actual": "s_axi_arqos"},
|
||||
"ARREADY": { "actual": "s_axi_arready"},
|
||||
"ARSIZE": { "actual": "s_axi_arsize"},
|
||||
"ARUSER": { "actual": "s_axi_aruser"},
|
||||
"ARVALID": { "actual": "s_axi_arvalid"},
|
||||
"AWADDR": { "actual": "s_axi_awaddr"},
|
||||
"AWCACHE": { "actual": "s_axi_awcache"},
|
||||
"AWID": { "actual": "s_axi_awid"},
|
||||
"AWLEN": { "actual": "s_axi_awlen"},
|
||||
"AWLOCK": { "actual": "s_axi_awlock"},
|
||||
"AWPROT": { "actual": "s_axi_awprot"},
|
||||
"AWQOS": { "actual": "s_axi_awqos"},
|
||||
"AWREADY": { "actual": "s_axi_awready"},
|
||||
"AWSIZE": { "actual": "s_axi_awsize"},
|
||||
"AWUSER": { "actual": "s_axi_awuser"},
|
||||
"AWVALID": { "actual": "s_axi_awvalid"},
|
||||
"BID": { "actual": "s_axi_bid"},
|
||||
"BREADY": { "actual": "s_axi_bready"},
|
||||
"BRESP": { "actual": "s_axi_bresp"},
|
||||
"BUSER": { "actual": "s_axi_buser"},
|
||||
"BVALID": { "actual": "s_axi_bvalid"},
|
||||
"RDATA": { "actual": "s_axi_rdata"},
|
||||
"RID": { "actual": "s_axi_rid"},
|
||||
"RLAST": { "actual": "s_axi_rlast"},
|
||||
"RREADY": { "actual": "s_axi_rready"},
|
||||
"RRESP": { "actual": "s_axi_rresp"},
|
||||
"RUSER": { "actual": "s_axi_ruser"},
|
||||
"RVALID": { "actual": "s_axi_rvalid"},
|
||||
"WDATA": { "actual": "s_axi_wdata"},
|
||||
"WLAST": { "actual": "s_axi_wlast"},
|
||||
"WREADY": { "actual": "s_axi_wready"},
|
||||
"WSTRB": { "actual": "s_axi_wstrb"},
|
||||
"WUSER": { "actual": "s_axi_wuser"},
|
||||
"WVALID": { "actual": "s_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/s00_entry_pipeline/s00_transaction_regulator/M_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "m_axi_araddr"},
|
||||
"ARBURST": { "actual": "m_axi_arburst"},
|
||||
"ARCACHE": { "actual": "m_axi_arcache"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARID": { "actual": "m_axi_arid"},
|
||||
"ARLEN": { "actual": "m_axi_arlen"},
|
||||
"ARLOCK": { "actual": "m_axi_arlock"},
|
||||
"ARPROT": { "actual": "m_axi_arprot"},
|
||||
"ARQOS": { "actual": "m_axi_arqos"},
|
||||
"ARREADY": { "actual": "m_axi_arready"},
|
||||
"ARSIZE": { "actual": "m_axi_arsize"},
|
||||
"ARUSER": { "actual": "m_axi_aruser"},
|
||||
"ARVALID": { "actual": "m_axi_arvalid"},
|
||||
"AWADDR": { "actual": "m_axi_awaddr"},
|
||||
"AWBURST": { "actual": "m_axi_awburst"},
|
||||
"AWCACHE": { "actual": "m_axi_awcache"},
|
||||
"AWID": { "actual": "m_axi_awid"},
|
||||
"AWLEN": { "actual": "m_axi_awlen"},
|
||||
"AWLOCK": { "actual": "m_axi_awlock"},
|
||||
"AWPROT": { "actual": "m_axi_awprot"},
|
||||
"AWQOS": { "actual": "m_axi_awqos"},
|
||||
"AWREADY": { "actual": "m_axi_awready"},
|
||||
"AWSIZE": { "actual": "m_axi_awsize"},
|
||||
"AWUSER": { "actual": "m_axi_awuser"},
|
||||
"AWVALID": { "actual": "m_axi_awvalid"},
|
||||
"BID": { "actual": "m_axi_bid"},
|
||||
"BREADY": { "actual": "m_axi_bready"},
|
||||
"BRESP": { "actual": "m_axi_bresp"},
|
||||
"BUSER": { "actual": "m_axi_buser"},
|
||||
"BVALID": { "actual": "m_axi_bvalid"},
|
||||
"RDATA": { "actual": "m_axi_rdata"},
|
||||
"RID": { "actual": "m_axi_rid"},
|
||||
"RLAST": { "actual": "m_axi_rlast"},
|
||||
"RREADY": { "actual": "m_axi_rready"},
|
||||
"RRESP": { "actual": "m_axi_rresp"},
|
||||
"RUSER": { "actual": "m_axi_ruser"},
|
||||
"RVALID": { "actual": "m_axi_rvalid"},
|
||||
"WDATA": { "actual": "m_axi_wdata"},
|
||||
"WLAST": { "actual": "m_axi_wlast"},
|
||||
"WREADY": { "actual": "m_axi_wready"},
|
||||
"WSTRB": { "actual": "m_axi_wstrb"},
|
||||
"WUSER": { "actual": "m_axi_wuser"},
|
||||
"WVALID": { "actual": "m_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/s00_entry_pipeline/s00_transaction_regulator/S_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "s_axi_araddr"},
|
||||
"ARBURST": { "actual": "s_axi_arburst"},
|
||||
"ARCACHE": { "actual": "s_axi_arcache"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARLEN": { "actual": "s_axi_arlen"},
|
||||
"ARLOCK": { "actual": "s_axi_arlock"},
|
||||
"ARPROT": { "actual": "s_axi_arprot"},
|
||||
"ARQOS": { "actual": "s_axi_arqos"},
|
||||
"ARREADY": { "actual": "s_axi_arready"},
|
||||
"ARSIZE": { "actual": "s_axi_arsize"},
|
||||
"ARUSER": { "actual": "s_axi_aruser"},
|
||||
"ARVALID": { "actual": "s_axi_arvalid"},
|
||||
"AWADDR": { "actual": "s_axi_awaddr"},
|
||||
"AWBURST": { "actual": "s_axi_awburst"},
|
||||
"AWCACHE": { "actual": "s_axi_awcache"},
|
||||
"AWLEN": { "actual": "s_axi_awlen"},
|
||||
"AWLOCK": { "actual": "s_axi_awlock"},
|
||||
"AWPROT": { "actual": "s_axi_awprot"},
|
||||
"AWQOS": { "actual": "s_axi_awqos"},
|
||||
"AWREADY": { "actual": "s_axi_awready"},
|
||||
"AWSIZE": { "actual": "s_axi_awsize"},
|
||||
"AWUSER": { "actual": "s_axi_awuser"},
|
||||
"AWVALID": { "actual": "s_axi_awvalid"},
|
||||
"BREADY": { "actual": "s_axi_bready"},
|
||||
"BRESP": { "actual": "s_axi_bresp"},
|
||||
"BUSER": { "actual": "s_axi_buser"},
|
||||
"BVALID": { "actual": "s_axi_bvalid"},
|
||||
"RDATA": { "actual": "s_axi_rdata"},
|
||||
"RLAST": { "actual": "s_axi_rlast"},
|
||||
"RREADY": { "actual": "s_axi_rready"},
|
||||
"RRESP": { "actual": "s_axi_rresp"},
|
||||
"RUSER": { "actual": "s_axi_ruser"},
|
||||
"RVALID": { "actual": "s_axi_rvalid"},
|
||||
"WDATA": { "actual": "s_axi_wdata"},
|
||||
"WLAST": { "actual": "s_axi_wlast"},
|
||||
"WREADY": { "actual": "s_axi_wready"},
|
||||
"WSTRB": { "actual": "s_axi_wstrb"},
|
||||
"WUSER": { "actual": "s_axi_wuser"},
|
||||
"WVALID": { "actual": "s_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/s00_entry_pipeline/s_axi": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "s_axi_araddr"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARPROT": { "actual": "s_axi_arprot"},
|
||||
"ARREADY": { "actual": "s_axi_arready"},
|
||||
"ARVALID": { "actual": "s_axi_arvalid"},
|
||||
"AWADDR": { "actual": "s_axi_awaddr"},
|
||||
"AWPROT": { "actual": "s_axi_awprot"},
|
||||
"AWREADY": { "actual": "s_axi_awready"},
|
||||
"AWVALID": { "actual": "s_axi_awvalid"},
|
||||
"BREADY": { "actual": "s_axi_bready"},
|
||||
"BRESP": { "actual": "s_axi_bresp"},
|
||||
"BVALID": { "actual": "s_axi_bvalid"},
|
||||
"RDATA": { "actual": "s_axi_rdata"},
|
||||
"RREADY": { "actual": "s_axi_rready"},
|
||||
"RRESP": { "actual": "s_axi_rresp"},
|
||||
"RVALID": { "actual": "s_axi_rvalid"},
|
||||
"WDATA": { "actual": "s_axi_wdata"},
|
||||
"WREADY": { "actual": "s_axi_wready"},
|
||||
"WSTRB": { "actual": "s_axi_wstrb"},
|
||||
"WVALID": { "actual": "s_axi_wvalid"}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -115,16 +115,16 @@ module dso_top
|
||||
end
|
||||
assign probe_comp = probe_div_clk;
|
||||
|
||||
//assign adc_data = {~data_deser[63:24],data_deser[23:16],~data_deser[15:0]};
|
||||
assign adc_data = {~data_deser[63:24],data_deser[23:16],~data_deser[15:0]};
|
||||
//assign adc_data = {8'h77,8'h66,8'h55,8'h44,8'h33,8'h22,8'h11,8'h00};
|
||||
reg[7:0] adc_ramp_counter;
|
||||
always @(posedge divclk) begin
|
||||
if (!S01_ARESETN)
|
||||
adc_ramp_counter <= 0;
|
||||
else
|
||||
adc_ramp_counter <= adc_ramp_counter + 1;
|
||||
end
|
||||
assign adc_data = {8{adc_ramp_counter}};
|
||||
// reg[7:0] adc_ramp_counter;
|
||||
// always @(posedge divclk) begin
|
||||
// if (!S01_ARESETN)
|
||||
// adc_ramp_counter <= 0;
|
||||
// else
|
||||
// adc_ramp_counter <= adc_ramp_counter + 1;
|
||||
// end
|
||||
// assign adc_data = {8{adc_ramp_counter}};
|
||||
|
||||
wire serdes_rst;
|
||||
reg [2:0] serdes_rst_cdc = 3'b111;
|
||||
|
||||
@ -28,6 +28,7 @@
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="TRUE"/>
|
||||
@ -72,9 +73,6 @@
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xci">
|
||||
<Proxy FileSetName="design_1_mig_7series_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/imports/dso_top/I2C_Transmit.v">
|
||||
<FileInfo>
|
||||
@ -239,12 +237,6 @@
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="design_1_mig_7series_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_mig_7series_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="design_1_mig_7series_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="fifo_generator_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_generator_0">
|
||||
<File Path="$PSRCDIR/sources_1/ip/fifo_generator_0/fifo_generator_0.xci">
|
||||
<FileInfo>
|
||||
@ -286,10 +278,10 @@
|
||||
<Step Id="synth_design">
|
||||
<Option Id="ResourceSharing">2</Option>
|
||||
<Option Id="FsmExtraction">1</Option>
|
||||
<Option Id="Directive">7</Option>
|
||||
<Option Id="NoCombineLuts">1</Option>
|
||||
<Option Id="ShregMinSize">5</Option>
|
||||
<Option Id="KeepEquivalentRegisters">1</Option>
|
||||
<Option Id="NoCombineLuts">1</Option>
|
||||
<Option Id="Directive">7</Option>
|
||||
</Step>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@ -307,16 +299,6 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_mig_7series_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_mig_7series_0_0" Part="xc7a100tfgg484-2" ConstrsSet="design_1_mig_7series_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_mig_7series_0_0_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="fifo_generator_0_synth_1" Type="Ft3:Synth" SrcSet="fifo_generator_0" Part="xc7a100tfgg484-2" ConstrsSet="fifo_generator_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_generator_0_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
|
||||
@ -370,23 +352,6 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_mig_7series_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a100tfgg484-2" ConstrsSet="design_1_mig_7series_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_mig_7series_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="fifo_generator_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a100tfgg484-2" ConstrsSet="fifo_generator_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_generator_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
||||
|
||||
@ -8,8 +8,8 @@ let mainWindow: BrowserWindow | null;
|
||||
function createWindow() {
|
||||
// Create the browser window.
|
||||
mainWindow = new BrowserWindow({
|
||||
width: 800,
|
||||
height: 600,
|
||||
width: 1600,
|
||||
height: 900,
|
||||
webPreferences: {
|
||||
preload: path.join(__dirname, "preload.js"),
|
||||
nodeIntegration: true,
|
||||
|
||||
@ -22,7 +22,7 @@
|
||||
#define USER_DEVICE_PATH "user"
|
||||
#define C2H_0_DEVICE_PATH "c2h_0"
|
||||
|
||||
#define DATAMOVER_REG_OUT 0x00000 // bit 0: halt, bit 1: reset
|
||||
#define DATAMOVER_REG_OUT 0x00000 // bit 0: !halt, bit 1: !reset
|
||||
#define DATAMOVER_TRANSFER_COUNTER 0x00008 // A 32 bit value, low 16 is transfer counter, bit 31 error bit
|
||||
#define BOARD_REG_OUT 0x10000 // A 32 bit value, bit 0:3: attenuation, bit 4:7: dc_cpl, bit 8: acq_en, bit 9: clk_oe, bit 10: fe_en, 21bits unused
|
||||
#define BOARD_REG_IN 0x10008 // unused for now
|
||||
@ -43,19 +43,55 @@
|
||||
#define CLOCK_GEN_I2C_ADDRESS_READ 0b10110001 //IF WE COULD
|
||||
|
||||
enum ScopeCommand {
|
||||
board_enable,
|
||||
adc_enable,
|
||||
adc_rest,
|
||||
adc_power_down,
|
||||
adc_active,
|
||||
adc_cgain_cfg,
|
||||
adc_btc_mode,
|
||||
adc_chnum_clkdiv_init,
|
||||
clk_enable,
|
||||
init_board,
|
||||
adc_enable_ramp_test,
|
||||
dataMover_enable,
|
||||
dataMover_halt,
|
||||
dataMover_disable,
|
||||
test_write
|
||||
enable_channel,
|
||||
disable_channel,
|
||||
ac_couple,
|
||||
dc_couple,
|
||||
voltage_divison_set,
|
||||
voltage_offset_set,
|
||||
bandwidth_set,
|
||||
test_write,
|
||||
test_adc_data
|
||||
};
|
||||
|
||||
struct VoltageDivSetParam {
|
||||
int ch_num;
|
||||
int voltage_div;
|
||||
};
|
||||
|
||||
struct VoltageOffsetParam {
|
||||
int ch_num;
|
||||
double voltage;
|
||||
};
|
||||
|
||||
struct BandwidthSetParam {
|
||||
int ch_num;
|
||||
int bw;
|
||||
};
|
||||
|
||||
struct BoardState {
|
||||
//general front end en
|
||||
bool board_en;
|
||||
//adc values
|
||||
bool adc_en;
|
||||
uint8_t num_ch_on;
|
||||
bool ch_is_on[4];
|
||||
uint8_t adc_chnum_clkdiv [4];
|
||||
uint8_t adc_in_sel_12[4];
|
||||
uint8_t adc_in_sel_34[4];
|
||||
//pga's
|
||||
uint8_t pga[4][4];
|
||||
//dac
|
||||
uint8_t dac[4][5];
|
||||
//clock values
|
||||
bool clk_en;
|
||||
//Board Register Values
|
||||
uint32_t board_reg_out; // A 32 bit value, bit 0:3: attenuation, bit 4:7: dc_cpl, bit 8: acq_en, bit 9: clk_oe, bit 10: fe_en, 21bits unused
|
||||
uint32_t datamover_reg_out; // bit 0: !halt, bit 1: !reset, bit 4:6: channel
|
||||
};
|
||||
|
||||
class PCIeLink {
|
||||
@ -85,7 +121,6 @@ private:
|
||||
|
||||
char user_device[20] = USER_DEVICE_PATH; //write/read registers
|
||||
char c2h_0_device[20] = C2H_0_DEVICE_PATH; //read memory
|
||||
uint8_t dataMoverReg[1] = {0x00};
|
||||
HANDLE user_handle;
|
||||
char user_connection_string[261] = "";
|
||||
HANDLE c2h_0_handle;
|
||||
@ -93,6 +128,9 @@ private:
|
||||
LARGE_INTEGER freq; //used for perforamnce testing
|
||||
int64_t last_chunk_read;
|
||||
|
||||
//current state
|
||||
BoardState currentBoardState;
|
||||
|
||||
std::atomic<bool> _run;
|
||||
std::atomic<bool> _pause;
|
||||
std::thread PCIeReadThread;
|
||||
@ -106,9 +144,23 @@ private:
|
||||
|
||||
void _Read(HANDLE hPCIE, long long address, uint8_t* buff, int bytesToRead);
|
||||
void _Write(HANDLE hPCIE, long long address, uint8_t* buff, int bytesToWrite);
|
||||
void _Write32(HANDLE hPCIE, long long address, uint32_t val);
|
||||
void _FIFO_WRITE(HANDLE hPCIE, uint8_t* data, uint8_t bytesToWrite);
|
||||
void _Job();
|
||||
|
||||
|
||||
//scope control stuff
|
||||
int _ch_on(int ch_num);
|
||||
int _ch_off(int ch_num);
|
||||
int _dc_cpl(int ch_num);
|
||||
int _ac_cpl(int ch_num);
|
||||
int _vdiv_set(int ch_num, int vdiv);
|
||||
int _voffset_set(int ch_num, double voffset);
|
||||
int _bw_set(int ch_num, int bw);
|
||||
int _adc_ch_cfg();
|
||||
void _adc_power_down();
|
||||
void _adc_active();
|
||||
|
||||
protected:
|
||||
|
||||
};
|
||||
|
||||
@ -39,6 +39,8 @@ public:
|
||||
void setMathSign(bool newSign);
|
||||
void getData();
|
||||
void setFileName(int8_t newFile);
|
||||
void hardWareCommand(int command, int channel, int val1, double val2);
|
||||
void testADCData();
|
||||
|
||||
private:
|
||||
// external queue
|
||||
|
||||
@ -222,17 +222,7 @@ boost::lockfree::queue<buffer*, boost::lockfree::fixed_sized<false>> testerDataQ
|
||||
void runPCIeTest() {
|
||||
|
||||
controller* troller = new controller(&testerDataQueue);
|
||||
troller->controllerUnPause();
|
||||
|
||||
std::this_thread::sleep_for(std::chrono::milliseconds(500));
|
||||
|
||||
/*FILE* fp = fopen("TestData.txt","w");
|
||||
for(int i = 0; i < (1 << 23); i+= 8) {
|
||||
fprintf(fp,"%X,%X,%X,%X,%X,%X,%X,%X\n",
|
||||
buff[i],buff[i + 1],buff[i + 2],buff[i + 3],buff[i + 4],buff[i + 5],buff[i + 6],buff[i + 7]);
|
||||
}
|
||||
fclose(fp); */
|
||||
|
||||
|
||||
troller->setWindowSize(1000);
|
||||
troller->testADCData();
|
||||
delete troller;
|
||||
}
|
||||
@ -174,9 +174,7 @@ void PCIeLink::Read(uint8_t* buff) {
|
||||
}
|
||||
|
||||
void PCIeLink::InitBoard() {
|
||||
Write(board_enable,nullptr);
|
||||
Write(clk_enable,nullptr);
|
||||
Write(adc_enable,nullptr);
|
||||
Write(init_board,nullptr);
|
||||
Write(dataMover_enable,nullptr);
|
||||
}
|
||||
|
||||
@ -204,18 +202,83 @@ void PCIeLink::Stop() {
|
||||
*************************************************************/
|
||||
void PCIeLink::Write(ScopeCommand command, void* val) {
|
||||
switch(command) {
|
||||
case board_enable:
|
||||
case init_board:
|
||||
INFO << "Enabling Board";
|
||||
{
|
||||
uint8_t en[] = {0x00, 0x00};
|
||||
_Read(user_handle,BOARD_REG_OUT,en,2);
|
||||
en[1] |= 0x01; //acq->on fe->off
|
||||
_Write(user_handle,BOARD_REG_OUT,en,2);
|
||||
currentBoardState.board_reg_out |= 0x0100; //acq->on fe->off
|
||||
_Write32(user_handle,BOARD_REG_OUT,currentBoardState.board_reg_out);
|
||||
std::this_thread::sleep_for(std::chrono::milliseconds(5));
|
||||
}
|
||||
break;
|
||||
case adc_enable:
|
||||
|
||||
INFO << "Enabling PLL";
|
||||
{
|
||||
uint16_t config_clk_gen[] = {
|
||||
0x0010, 0x010B, 0x0233, 0x08B0,
|
||||
0x0901, 0x1000, 0x1180, 0x1501,
|
||||
0x1600, 0x1705, 0x1900, 0x1A32,
|
||||
0x1B00, 0x1C00, 0x1D00, 0x1E00,
|
||||
0x1F00, 0x2001, 0x210C, 0x2228,
|
||||
0x2303, 0x2408, 0x2500, 0x2600,
|
||||
0x2700, 0x2F00, 0x3000, 0x3110,
|
||||
0x3200, 0x3300, 0x3400, 0x3500,
|
||||
0x3800, 0x4802 }; //correct bytes to configure the clock gen
|
||||
|
||||
//write to the clock generator
|
||||
for(int i = 0; i < 34; i++) {
|
||||
uint8_t data[] = {I2C_BYTE_PLL, CLOCK_GEN_I2C_ADDRESS_WRITE, (uint8_t)((config_clk_gen[i] & 0xFF00) >> 8),(uint8_t)(config_clk_gen[i] & 0xFF)};
|
||||
//printf("DataPacket: %X %X %X %X\n",data[0],data[1],data[2],data[3]);
|
||||
_FIFO_WRITE(user_handle,data,4);
|
||||
}
|
||||
|
||||
currentBoardState.board_reg_out |= 0x0200;
|
||||
_Write32(user_handle,BOARD_REG_OUT,currentBoardState.board_reg_out);
|
||||
}
|
||||
|
||||
INFO << "Enabling ADC";
|
||||
{
|
||||
//Reset ADC
|
||||
uint8_t resetADC[] = {0xFD,0x00,0x00,0x01};
|
||||
_FIFO_WRITE(user_handle,resetADC,4);
|
||||
//Power Down ADC
|
||||
_adc_power_down();
|
||||
//Set Channel and Clock Div
|
||||
_FIFO_WRITE(user_handle,currentBoardState.adc_chnum_clkdiv,sizeof(currentBoardState.adc_chnum_clkdiv));
|
||||
//invert channels
|
||||
uint8_t channel_invert[] = {0xFD,0x24,0x00,0x7F};
|
||||
_FIFO_WRITE(user_handle,channel_invert,4);
|
||||
//Adjust full scale value
|
||||
uint8_t full_scale_adjust[] = {0xFD,0x55,0x00,0x10};
|
||||
_FIFO_WRITE(user_handle,full_scale_adjust,4);
|
||||
//Course Gain On
|
||||
uint8_t course_gain_on[] = {0xFD,0x33,0x00,0x00};
|
||||
_FIFO_WRITE(user_handle,course_gain_on,4);
|
||||
//Course Gain 4-CH set
|
||||
uint8_t course_gain4[] = {0xFD,0x2A,0xAA,0xAA};
|
||||
_FIFO_WRITE(user_handle,course_gain4,4);
|
||||
//Course Gain 1-CH & 2-CH set
|
||||
uint8_t course_gain12[] = {0xFD,0x2B,0x0A,0xAA};
|
||||
_FIFO_WRITE(user_handle,course_gain12,4);
|
||||
//Set adc into active mode
|
||||
_adc_active();
|
||||
_FIFO_WRITE(user_handle,currentBoardState.adc_in_sel_12,sizeof(currentBoardState.adc_in_sel_12));
|
||||
_FIFO_WRITE(user_handle,currentBoardState.adc_in_sel_34,sizeof(currentBoardState.adc_in_sel_34));
|
||||
}
|
||||
|
||||
INFO << "Enabling the front end";
|
||||
{
|
||||
currentBoardState.board_reg_out |= 0x0400; //fe->on
|
||||
_Write32(user_handle,BOARD_REG_OUT,currentBoardState.board_reg_out);
|
||||
std::this_thread::sleep_for(std::chrono::milliseconds(5));
|
||||
//enable the pga
|
||||
for(int i = 0; i < 4; i++) {
|
||||
_FIFO_WRITE(user_handle,currentBoardState.pga[i],sizeof(currentBoardState.pga[i]));
|
||||
_FIFO_WRITE(user_handle,currentBoardState.dac[i],sizeof(currentBoardState.dac[i]));
|
||||
}
|
||||
}
|
||||
|
||||
break;
|
||||
case adc_enable_ramp_test:
|
||||
INFO << "Enabling ADC RAMP MODE";
|
||||
{
|
||||
//Reset ADC
|
||||
uint8_t resetADC[] = {0xFD,0x00,0x00,0x01};
|
||||
@ -244,31 +307,53 @@ void PCIeLink::Write(ScopeCommand command, void* val) {
|
||||
_FIFO_WRITE(user_handle,adcActiveMode,4);
|
||||
}
|
||||
break;
|
||||
case clk_enable:
|
||||
INFO << "Enabling PLL";
|
||||
case dataMover_enable:
|
||||
INFO << "Enabling DataMover";
|
||||
{
|
||||
uint16_t config_clk_gen[] = {
|
||||
0x0010, 0x010B, 0x0233, 0x08B0,
|
||||
0x0901, 0x1000, 0x1180, 0x1501,
|
||||
0x1600, 0x1705, 0x1900, 0x1A32,
|
||||
0x1B00, 0x1C00, 0x1D00, 0x1E00,
|
||||
0x1F00, 0x2001, 0x210C, 0x2228,
|
||||
0x2303, 0x2408, 0x2500, 0x2600,
|
||||
0x2700, 0x2F00, 0x3000, 0x3110,
|
||||
0x3200, 0x3300, 0x3400, 0x3500,
|
||||
0x3800, 0x4802 }; //correct bytes to configure the clock gen
|
||||
|
||||
//write to the clock generator
|
||||
for(int i = 0; i < 34; i++) {
|
||||
uint8_t data[] = {I2C_BYTE_PLL, CLOCK_GEN_I2C_ADDRESS_WRITE, (uint8_t)((config_clk_gen[i] & 0xFF00) >> 8),(uint8_t)(config_clk_gen[i] & 0xFF)};
|
||||
//printf("DataPacket: %X %X %X %X\n",data[0],data[1],data[2],data[3]);
|
||||
_FIFO_WRITE(user_handle,data,4);
|
||||
}
|
||||
|
||||
uint8_t en[] = {0x00, 0x00};
|
||||
_Read(user_handle,BOARD_REG_OUT,en,2);
|
||||
en[1] |= 0x02; //clk->on
|
||||
_Write(user_handle,BOARD_REG_OUT,en,2);
|
||||
currentBoardState.datamover_reg_out |= 0x03;
|
||||
_Write32(user_handle,DATAMOVER_REG_OUT,currentBoardState.datamover_reg_out);
|
||||
}
|
||||
break;
|
||||
case dataMover_disable:
|
||||
INFO << "Disabling DataMover";
|
||||
{
|
||||
currentBoardState.datamover_reg_out &= ~(0x01);
|
||||
_Write32(user_handle,DATAMOVER_REG_OUT,currentBoardState.datamover_reg_out);
|
||||
currentBoardState.datamover_reg_out &= ~(0x02);
|
||||
_Write32(user_handle,DATAMOVER_REG_OUT,currentBoardState.datamover_reg_out);
|
||||
}
|
||||
break;
|
||||
case enable_channel:
|
||||
_ch_on(*((int*)val));
|
||||
break;
|
||||
case disable_channel:
|
||||
_ch_off(*((int*)val));
|
||||
break;
|
||||
case ac_couple:
|
||||
_ac_cpl(*((int*)val));
|
||||
break;
|
||||
case dc_couple:
|
||||
_dc_cpl(*((int*)val));
|
||||
break;
|
||||
case voltage_divison_set:
|
||||
{
|
||||
VoltageDivSetParam* param = (VoltageDivSetParam*)val;
|
||||
DEBUG << "Setting Channel " << param->ch_num << " Voltage Division To " << param->voltage_div;
|
||||
_vdiv_set(param->ch_num,param->voltage_div);
|
||||
}
|
||||
break;
|
||||
case voltage_offset_set:
|
||||
{
|
||||
VoltageOffsetParam* param = (VoltageOffsetParam*)val;
|
||||
DEBUG << "Setting Channel " << param->ch_num << " DC Voltage Offset To " << param->voltage << "mV";
|
||||
_voffset_set(param->ch_num,param->voltage);
|
||||
}
|
||||
break;
|
||||
case bandwidth_set:
|
||||
{
|
||||
BandwidthSetParam* param = (BandwidthSetParam*)val;
|
||||
DEBUG << "Setting Channel " << param->ch_num << " Bandwidth To: " << param->bw;
|
||||
_bw_set(param->ch_num,param->bw);
|
||||
}
|
||||
break;
|
||||
case test_write:
|
||||
@ -293,20 +378,49 @@ void PCIeLink::Write(ScopeCommand command, void* val) {
|
||||
printf("After writting 0 again, the read value is: %d\n",rxBuff[0]);
|
||||
}
|
||||
break;
|
||||
case dataMover_enable:
|
||||
INFO << "Enabling DataMover";
|
||||
case test_adc_data:
|
||||
{
|
||||
dataMoverReg[0] |= 0x03;
|
||||
_Write(user_handle,DATAMOVER_REG_OUT,dataMoverReg,1);
|
||||
}
|
||||
break;
|
||||
case dataMover_disable:
|
||||
INFO << "Disabling DataMover";
|
||||
{
|
||||
dataMoverReg[0] &= ~(0x01);
|
||||
_Write(user_handle,DATAMOVER_REG_OUT,dataMoverReg,1);
|
||||
dataMoverReg[0] &= ~(0x02);
|
||||
_Write(user_handle,DATAMOVER_REG_OUT,dataMoverReg,1);
|
||||
int num_buffers = 4;
|
||||
uint8_t* preBuff = (uint8_t*)malloc(BUFFER_SIZE * sizeof(uint8_t));
|
||||
int8_t **buffers = (int8_t**)malloc(num_buffers * sizeof(int8_t*));
|
||||
for(int i = 0; i < num_buffers; i++) {
|
||||
buffers[i] = (int8_t*)malloc(BUFFER_SIZE * sizeof(int8_t));
|
||||
}
|
||||
|
||||
for(int i = 0; i < num_buffers; i++) {
|
||||
Read(preBuff);
|
||||
for(int q = 0; q < BUFFER_SIZE; q++) {
|
||||
if(preBuff[q] & 0x80) {
|
||||
//postive
|
||||
buffers[i][q] = (int)(preBuff[q] & 0x7F);
|
||||
} else {
|
||||
//negative
|
||||
buffers[i][q] = (-128 + ((int)(preBuff[q] & 0x7F)));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for(int i = 0; i < num_buffers; i++) {
|
||||
char name[100];
|
||||
sprintf(name,"ADC_DATA_FILE%d.csv",i);
|
||||
FILE* file = fopen(name,"w");
|
||||
for(int q = 0; q < BUFFER_SIZE;) {
|
||||
fprintf(file,"%d,",buffers[i][q++]);
|
||||
fprintf(file,"%d,",buffers[i][q++]);
|
||||
fprintf(file,"%d,",buffers[i][q++]);
|
||||
fprintf(file,"%d,",buffers[i][q++]);
|
||||
fprintf(file,"%d,",buffers[i][q++]);
|
||||
fprintf(file,"%d,",buffers[i][q++]);
|
||||
fprintf(file,"%d,",buffers[i][q++]);
|
||||
fprintf(file,"%d\n",buffers[i][q++]);
|
||||
}
|
||||
}
|
||||
|
||||
for(int i = 0; i < num_buffers; i++) {
|
||||
free(buffers[i]);
|
||||
}
|
||||
free(preBuff);
|
||||
free(buffers);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
@ -399,7 +513,34 @@ void PCIeLink::_Write(HANDLE hPCIE, int64_t address, uint8_t* buff, int bytesToW
|
||||
}
|
||||
}
|
||||
|
||||
void PCIeLink::_Write32(HANDLE hPCIE, long long address, uint32_t val) {
|
||||
if(hPCIE == INVALID_HANDLE_VALUE) {
|
||||
ERROR << "INVALID HANDLE PASSED INTO PCIeLink::_Write(): " << hPCIE;
|
||||
return;
|
||||
}
|
||||
|
||||
LARGE_INTEGER offset;
|
||||
offset.QuadPart = address;
|
||||
// set file pointer to offset of target address within PCIe BAR
|
||||
if (INVALID_SET_FILE_POINTER == SetFilePointerEx(hPCIE, offset, NULL, FILE_BEGIN)) {
|
||||
ERROR << "Error setting file pointer for PCIeLink::_Write(), win32 error code: " << GetLastError();
|
||||
}
|
||||
|
||||
// write from buffer to device
|
||||
DWORD bytesWritten;
|
||||
uint8_t bytes[4];
|
||||
bytes[3] = (uint8_t)( (val & 0xFF000000) >> 24);
|
||||
bytes[2] = (uint8_t)( (val & 0x00FF0000) >> 16);
|
||||
bytes[1] = (uint8_t)( (val & 0x0000FF00) >> 8);
|
||||
bytes[0] = (uint8_t)( (val & 0x000000FF));
|
||||
if (!WriteFile(hPCIE, bytes, 4, &bytesWritten, NULL)) {
|
||||
ERROR << "_Write() failed with Win32 error code: " << GetLastError();
|
||||
}
|
||||
}
|
||||
|
||||
void PCIeLink::_Job() {
|
||||
|
||||
uint8_t* preBuff = (uint8_t*)malloc(sizeof(uint8_t) * BUFFER_SIZE);
|
||||
while(_run.load()) {
|
||||
while(_pause.load()) {
|
||||
std::this_thread::sleep_for(std::chrono::milliseconds(2));
|
||||
@ -409,36 +550,111 @@ void PCIeLink::_Job() {
|
||||
buff = bufferAllocator.allocate(1);
|
||||
bufferAllocator.construct(buff);
|
||||
//read from the PCIeLink
|
||||
Read((uint8_t*)buff->data);
|
||||
Read(preBuff);
|
||||
for(int i = 0; i < BUFFER_SIZE; i++) {
|
||||
if(preBuff[i] & 0x80) {
|
||||
//postive
|
||||
buff->data[i] = (int)(preBuff[i] & 0x7F);
|
||||
} else {
|
||||
//negative
|
||||
buff->data[i] = (-128 + ((int)(preBuff[i] & 0x7F)));
|
||||
}
|
||||
}
|
||||
//push to queue
|
||||
outputQueue->push(buff);
|
||||
}
|
||||
free(preBuff);
|
||||
}
|
||||
|
||||
PCIeLink::PCIeLink(boost::lockfree::queue<buffer*, boost::lockfree::fixed_sized<false>> *outputQueue) {
|
||||
user_handle = INVALID_HANDLE_VALUE;
|
||||
c2h_0_handle = INVALID_HANDLE_VALUE;
|
||||
dataMoverReg[0] = 0x00;
|
||||
last_chunk_read = -1;
|
||||
_run = true;
|
||||
_pause = true;
|
||||
QueryPerformanceFrequency(&freq);
|
||||
this->outputQueue = outputQueue;
|
||||
//keep the read thread alive but paused
|
||||
_run = true;
|
||||
_pause = true;
|
||||
//init board state vairable
|
||||
currentBoardState.board_en = false;
|
||||
currentBoardState.adc_en = false;
|
||||
currentBoardState.clk_en = false;
|
||||
currentBoardState.num_ch_on = 0;
|
||||
|
||||
//adc stuff
|
||||
currentBoardState.adc_chnum_clkdiv[0] = 0xFD;
|
||||
currentBoardState.adc_chnum_clkdiv[1] = 0x31;
|
||||
currentBoardState.adc_chnum_clkdiv[2] = 0x00;
|
||||
currentBoardState.adc_chnum_clkdiv[3] = 0x01; //default single channel
|
||||
|
||||
currentBoardState.adc_in_sel_12[0] = 0xFD;
|
||||
currentBoardState.adc_in_sel_12[1] = 0x3A;
|
||||
currentBoardState.adc_in_sel_12[2] = 0x02; //default CH1
|
||||
currentBoardState.adc_in_sel_12[3] = 0x02; //default CH1
|
||||
|
||||
currentBoardState.adc_in_sel_34[0] = 0xFD;
|
||||
currentBoardState.adc_in_sel_34[1] = 0x3B;
|
||||
currentBoardState.adc_in_sel_34[2] = 0x02; //default CH1
|
||||
currentBoardState.adc_in_sel_34[3] = 0x02; //default CH1
|
||||
|
||||
for(int i = 0; i < 4; i++) {
|
||||
currentBoardState.ch_is_on[i] = 0;
|
||||
//init dac state
|
||||
currentBoardState.dac[i][0] = 0xFF;
|
||||
currentBoardState.dac[i][1] = 0xC2;
|
||||
currentBoardState.dac[i][3] = 0x07;
|
||||
currentBoardState.dac[i][4] = 0x80;
|
||||
//init pga state
|
||||
currentBoardState.pga[i][1] = 0x00;
|
||||
currentBoardState.pga[i][2] = 0x04;
|
||||
currentBoardState.pga[i][3] = 0x0A;
|
||||
}
|
||||
//init pga state address
|
||||
currentBoardState.pga[0][0] = 0xFB;
|
||||
currentBoardState.pga[1][0] = 0xFA;
|
||||
currentBoardState.pga[2][0] = 0xF9;
|
||||
currentBoardState.pga[3][0] = 0xF8;
|
||||
|
||||
currentBoardState.dac[0][2] = 0x40;
|
||||
currentBoardState.dac[1][2] = 0x42;
|
||||
currentBoardState.dac[2][2] = 0x44;
|
||||
currentBoardState.dac[3][2] = 0x46;
|
||||
|
||||
//init register values
|
||||
currentBoardState.datamover_reg_out = 0x00;
|
||||
currentBoardState.board_reg_out = 0xFF; // FOR FUCKS SAKE CHANGE THIS!
|
||||
|
||||
//connect to the board and start the adc + read thread
|
||||
Connect();
|
||||
InitBoard();
|
||||
PCIeReadThread = std::thread(&PCIeLink::_Job, this);
|
||||
}
|
||||
|
||||
PCIeLink::~PCIeLink() {
|
||||
if(user_handle != INVALID_HANDLE_VALUE)
|
||||
CloseHandle(user_handle);
|
||||
if(c2h_0_handle != INVALID_HANDLE_VALUE)
|
||||
CloseHandle(c2h_0_handle);
|
||||
|
||||
//turn off the adc
|
||||
INFO << "Powering down adc";
|
||||
_adc_power_down();
|
||||
//disable the front end and board power
|
||||
INFO << "Turning Off Power To Front End";
|
||||
currentBoardState.board_reg_out = 0;
|
||||
_Write32(user_handle,BOARD_REG_OUT,currentBoardState.board_reg_out);
|
||||
|
||||
_pause.store(false);
|
||||
_run.store(true);
|
||||
_run.store(false);
|
||||
|
||||
DEBUG << "Waiting to join PCIeReadThread";
|
||||
PCIeReadThread.join();
|
||||
DEBUG << "Joined PCIeReadThread";
|
||||
|
||||
if(user_handle != INVALID_HANDLE_VALUE) {
|
||||
CloseHandle(user_handle);
|
||||
user_handle = INVALID_HANDLE_VALUE;
|
||||
}
|
||||
if(c2h_0_handle != INVALID_HANDLE_VALUE) {
|
||||
CloseHandle(c2h_0_handle);
|
||||
c2h_0_handle = INVALID_HANDLE_VALUE;
|
||||
}
|
||||
}
|
||||
|
||||
void PCIeLink::ClockTick1() {
|
||||
@ -466,11 +682,224 @@ double PCIeLink::GetTimeDelta() {
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/************************************************************************ SCOPE CONTROL STUFF ***********************************************/
|
||||
|
||||
int PCIeLink::_ch_on(int ch_num){
|
||||
|
||||
if (currentBoardState.ch_is_on[ch_num])
|
||||
return 0; //Channel already on
|
||||
|
||||
currentBoardState.num_ch_on++;
|
||||
currentBoardState.ch_is_on[ch_num] = true;
|
||||
_adc_ch_cfg();
|
||||
|
||||
_FIFO_WRITE(user_handle,currentBoardState.dac[ch_num],sizeof(currentBoardState.dac[ch_num]));
|
||||
_FIFO_WRITE(user_handle,currentBoardState.pga[ch_num],sizeof(currentBoardState.pga[ch_num]));
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int PCIeLink::_ch_off(int ch_num){
|
||||
|
||||
if (!currentBoardState.ch_is_on[ch_num])
|
||||
return 0; //Channel already off
|
||||
|
||||
currentBoardState.num_ch_on--;
|
||||
currentBoardState.ch_is_on[ch_num] = false;
|
||||
_adc_ch_cfg();
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int PCIeLink::_dc_cpl(int ch_num){
|
||||
if (ch_num == 0)
|
||||
currentBoardState.board_reg_out |= (1 << 4);
|
||||
else if (ch_num == 1)
|
||||
currentBoardState.board_reg_out |= (1 << 5);
|
||||
else if (ch_num == 2)
|
||||
currentBoardState.board_reg_out |= (1 << 6);
|
||||
else if (ch_num == 3)
|
||||
currentBoardState.board_reg_out |= (1 << 7);
|
||||
|
||||
_Write32(user_handle,BOARD_REG_OUT,currentBoardState.board_reg_out);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int PCIeLink::_ac_cpl(int ch_num){
|
||||
if (ch_num == 0)
|
||||
currentBoardState.board_reg_out &= ~(1 << 4);
|
||||
else if (ch_num == 1)
|
||||
currentBoardState.board_reg_out &= ~(1 << 5);
|
||||
else if (ch_num == 2)
|
||||
currentBoardState.board_reg_out &= ~(1 << 6);
|
||||
else if (ch_num == 3)
|
||||
currentBoardState.board_reg_out &= ~(1 << 7);
|
||||
|
||||
_Write32(user_handle,BOARD_REG_OUT,currentBoardState.board_reg_out);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
//expect vdiv in millivolts
|
||||
int PCIeLink::_vdiv_set(int ch_num, int vdiv){
|
||||
|
||||
if (vdiv <= 100){ //Attenuator relay on for higher v/divs
|
||||
if (ch_num == 0)
|
||||
currentBoardState.board_reg_out |= (1 << 0);
|
||||
else if (ch_num == 1)
|
||||
currentBoardState.board_reg_out |= (1 << 1);
|
||||
else if (ch_num == 2)
|
||||
currentBoardState.board_reg_out |= (1 << 2);
|
||||
else if (ch_num == 3)
|
||||
currentBoardState.board_reg_out |= (1 << 3);
|
||||
}
|
||||
else{ //Attenuator relay off for lower v/divs
|
||||
if (ch_num == 0)
|
||||
currentBoardState.board_reg_out &= ~(1 << 0);
|
||||
else if (ch_num == 1)
|
||||
currentBoardState.board_reg_out &= ~(1 << 1);
|
||||
else if (ch_num == 2)
|
||||
currentBoardState.board_reg_out &= ~(1 << 2);
|
||||
else if (ch_num == 3)
|
||||
currentBoardState.board_reg_out &= ~(1 << 3);
|
||||
}
|
||||
|
||||
if (vdiv == 10000 || vdiv == 100){
|
||||
currentBoardState.pga[ch_num][3] &= 0xE0;
|
||||
currentBoardState.pga[ch_num][3] |= 0x0A;
|
||||
}
|
||||
else if (vdiv == 5000 || vdiv == 50){
|
||||
currentBoardState.pga[ch_num][3] &= 0xE0;
|
||||
currentBoardState.pga[ch_num][3] |= 0x07;
|
||||
}
|
||||
else if (vdiv == 2000 || vdiv == 20){
|
||||
currentBoardState.pga[ch_num][3] &= 0xE0;
|
||||
currentBoardState.pga[ch_num][3] |= 0x03;
|
||||
}
|
||||
else if (vdiv == 1000 || vdiv == 10){
|
||||
currentBoardState.pga[ch_num][3] &= 0xE0;
|
||||
currentBoardState.pga[ch_num][3] |= 0x1A;
|
||||
}
|
||||
else if (vdiv == 500 || vdiv == 5){
|
||||
currentBoardState.pga[ch_num][3] &= 0xE0;
|
||||
currentBoardState.pga[ch_num][3] |= 0x17;
|
||||
}
|
||||
else if (vdiv == 200 || vdiv == 2){
|
||||
currentBoardState.pga[ch_num][3] &= 0xE0;
|
||||
currentBoardState.pga[ch_num][3] |= 0x13;
|
||||
}
|
||||
else if (vdiv == 1){
|
||||
currentBoardState.pga[ch_num][3] &= 0xE0;
|
||||
currentBoardState.pga[ch_num][3] |= 0x10;
|
||||
}
|
||||
|
||||
_Write32(user_handle,BOARD_REG_OUT,currentBoardState.board_reg_out);
|
||||
_FIFO_WRITE(user_handle,currentBoardState.pga[ch_num],sizeof(currentBoardState.pga[ch_num]));
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int PCIeLink::_voffset_set(int ch_num, double voffset){
|
||||
unsigned int dac_value = (unsigned int)round((voffset + 0.5) * 4095);
|
||||
|
||||
currentBoardState.dac[ch_num][4] = (unsigned char)(0xFF & dac_value);
|
||||
currentBoardState.dac[ch_num][3] = (unsigned char)(0x0F & (dac_value >> 8));
|
||||
|
||||
_FIFO_WRITE(user_handle,currentBoardState.dac[ch_num],sizeof(currentBoardState.dac[ch_num]));
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int PCIeLink::_bw_set(int ch_num, int bw){
|
||||
if (bw == 20){
|
||||
currentBoardState.pga[ch_num][3] &= 0x1F;
|
||||
currentBoardState.pga[ch_num][3] |= 0x40;
|
||||
}
|
||||
else if (bw == 100){
|
||||
currentBoardState.pga[ch_num][3] &= 0x1F;
|
||||
currentBoardState.pga[ch_num][3] |= 0x80;
|
||||
}
|
||||
else if (bw == 200){
|
||||
currentBoardState.pga[ch_num][3] &= 0x1F;
|
||||
currentBoardState.pga[ch_num][3] |= 0xC0;
|
||||
}
|
||||
else if (bw == 350){
|
||||
currentBoardState.pga[ch_num][3] &= 0x1F;
|
||||
}
|
||||
|
||||
_FIFO_WRITE(user_handle,currentBoardState.pga[ch_num],sizeof(currentBoardState.pga[ch_num]));
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int PCIeLink::_adc_ch_cfg(){
|
||||
unsigned char cmd_temp [4];
|
||||
int i;
|
||||
|
||||
if (currentBoardState.num_ch_on == 0){
|
||||
return 1;
|
||||
}
|
||||
else if (currentBoardState.num_ch_on == 1) {
|
||||
currentBoardState.adc_chnum_clkdiv[3] = 0x01;
|
||||
currentBoardState.adc_chnum_clkdiv[2] = 0x00;
|
||||
|
||||
for (i=0; !currentBoardState.ch_is_on[i]; i++); //Find channel that is on
|
||||
|
||||
currentBoardState.adc_in_sel_12[3] = (2 << i); //Set all 4 ADCs to sample that channel
|
||||
currentBoardState.adc_in_sel_12[2] = (2 << i);
|
||||
currentBoardState.adc_in_sel_34[3] = (2 << i);
|
||||
currentBoardState.adc_in_sel_34[2] = (2 << i);
|
||||
currentBoardState.datamover_reg_out &= ~(0xF0);
|
||||
} else if (currentBoardState.num_ch_on == 2){
|
||||
currentBoardState.adc_chnum_clkdiv[3] = 0x02;
|
||||
currentBoardState.adc_chnum_clkdiv[2] = 0x01;
|
||||
|
||||
for (i=0; !currentBoardState.ch_is_on[i]; i++); //Find first on channel
|
||||
|
||||
currentBoardState.adc_in_sel_12[3] = (2 << i); //Set 2 ADCs to sample first channel
|
||||
currentBoardState.adc_in_sel_12[2] = (2 << i);
|
||||
|
||||
for (; !currentBoardState.ch_is_on[i]; i++); //Find second on channel
|
||||
|
||||
currentBoardState.adc_in_sel_34[3] = (2 << i); //Set 2 ADCs to sample second channel
|
||||
currentBoardState.adc_in_sel_34[2] = (2 << i);
|
||||
|
||||
currentBoardState.datamover_reg_out &= ~(0xF0);
|
||||
currentBoardState.datamover_reg_out |= 0x10;
|
||||
} else {
|
||||
currentBoardState.adc_chnum_clkdiv[3] = 0x04;
|
||||
currentBoardState.adc_chnum_clkdiv[2] = 0x02;
|
||||
currentBoardState.adc_in_sel_12[3] = (2 << 0); //Set each ADC to sample one channel
|
||||
currentBoardState.adc_in_sel_12[2] = (2 << 1);
|
||||
currentBoardState.adc_in_sel_34[3] = (2 << 2);
|
||||
currentBoardState.adc_in_sel_34[2] = (2 << 3);
|
||||
currentBoardState.datamover_reg_out &= ~(0xF0);
|
||||
currentBoardState.datamover_reg_out |= 0x30;
|
||||
}
|
||||
|
||||
|
||||
_adc_power_down();
|
||||
|
||||
_FIFO_WRITE(user_handle,currentBoardState.adc_chnum_clkdiv,sizeof(currentBoardState.adc_chnum_clkdiv));
|
||||
|
||||
_adc_active();
|
||||
|
||||
_FIFO_WRITE(user_handle,currentBoardState.adc_in_sel_12,sizeof(currentBoardState.adc_in_sel_12));
|
||||
_FIFO_WRITE(user_handle,currentBoardState.adc_in_sel_34,sizeof(currentBoardState.adc_in_sel_34));
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
void PCIeLink::_adc_power_down() {
|
||||
uint8_t power_down_bytes[4] = {0xFD,0x0F,0x02,0x00};
|
||||
_FIFO_WRITE(user_handle,power_down_bytes,sizeof(power_down_bytes));
|
||||
}
|
||||
|
||||
void PCIeLink::_adc_active() {
|
||||
uint8_t adc_active_bytes[4] = {0xFD,0x0F,0x00,0x00};
|
||||
_FIFO_WRITE(user_handle,adc_active_bytes,sizeof(adc_active_bytes));
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
@ -436,8 +436,8 @@ int Bridge::InitTxBridge() {
|
||||
// pipe already exists...
|
||||
PIPE_TYPE_MESSAGE | PIPE_READMODE_MESSAGE | PIPE_WAIT | PIPE_REJECT_REMOTE_CLIENTS,
|
||||
1,
|
||||
4096 * 16,
|
||||
4096 * 16,
|
||||
4096 * 4096 * 16,
|
||||
4096 * 4096 * 16,
|
||||
NMPWAIT_USE_DEFAULT_WAIT,
|
||||
NULL);
|
||||
|
||||
@ -503,8 +503,8 @@ int Bridge::InitRxBridge() {
|
||||
PIPE_TYPE_MESSAGE | PIPE_READMODE_MESSAGE |
|
||||
PIPE_WAIT | PIPE_REJECT_REMOTE_CLIENTS,
|
||||
1,
|
||||
4096 * 16,
|
||||
4096 * 16,
|
||||
4096 * 4096 * 16,
|
||||
4096 * 4096 * 16,
|
||||
NMPWAIT_USE_DEFAULT_WAIT,
|
||||
NULL);
|
||||
|
||||
|
||||
@ -30,7 +30,7 @@ controller::controller(boost::lockfree::queue<buffer*, boost::lockfree::fixed_si
|
||||
// set default values
|
||||
setCh(1);
|
||||
setTriggerCh(1);
|
||||
setLevel(50);
|
||||
setLevel(64);
|
||||
setPerSize(1);
|
||||
setWindowSize(1000);
|
||||
|
||||
@ -69,6 +69,7 @@ controller::~controller()
|
||||
delete processorThread;
|
||||
delete postProcessorThread;
|
||||
delete bridgeThread;
|
||||
delete pcieLinkThread;
|
||||
|
||||
DEBUG << "Controller Destroyed";
|
||||
}
|
||||
@ -434,7 +435,7 @@ void controller::controllerLoop()
|
||||
}
|
||||
|
||||
//Sleep, but don't oversleep
|
||||
std::this_thread::sleep_for(std::chrono::milliseconds(5));
|
||||
std::this_thread::sleep_for(std::chrono::microseconds(250));
|
||||
}
|
||||
}
|
||||
|
||||
@ -841,3 +842,69 @@ void controller::setFileName(int8_t newFile)
|
||||
free(inputFile);
|
||||
inputFile = filename;
|
||||
}
|
||||
|
||||
void controller::hardWareCommand(int command, int channel, int val1, double val2) {
|
||||
ScopeCommand cmd = static_cast<ScopeCommand>(command);
|
||||
|
||||
switch(cmd) {
|
||||
case init_board:
|
||||
|
||||
break;
|
||||
case adc_enable_ramp_test:
|
||||
|
||||
break;
|
||||
case dataMover_enable:
|
||||
|
||||
break;
|
||||
case dataMover_disable:
|
||||
|
||||
break;
|
||||
case test_write:
|
||||
|
||||
break;
|
||||
case enable_channel:
|
||||
pcieLinkThread->Write(cmd,(void*)&channel);
|
||||
break;
|
||||
case disable_channel:
|
||||
pcieLinkThread->Write(cmd,(void*)&channel);
|
||||
break;
|
||||
case ac_couple:
|
||||
pcieLinkThread->Write(cmd,(void*)&channel);
|
||||
break;
|
||||
case dc_couple:
|
||||
pcieLinkThread->Write(cmd,(void*)&channel);
|
||||
break;
|
||||
case voltage_divison_set:
|
||||
{
|
||||
VoltageDivSetParam param;
|
||||
param.ch_num = channel;
|
||||
param.voltage_div = val1;
|
||||
pcieLinkThread->Write(cmd,(void*)¶m);
|
||||
}
|
||||
break;
|
||||
case voltage_offset_set:
|
||||
{
|
||||
VoltageOffsetParam param;
|
||||
param.ch_num = channel;
|
||||
param.voltage = val2;
|
||||
pcieLinkThread->Write(cmd,(void*)¶m);
|
||||
}
|
||||
break;
|
||||
case bandwidth_set:
|
||||
{
|
||||
BandwidthSetParam param;
|
||||
param.ch_num = channel;
|
||||
param.bw = val1;
|
||||
pcieLinkThread->Write(cmd,(void*)¶m);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void controller::testADCData() {
|
||||
pcieLinkThread->Write(test_adc_data,nullptr);
|
||||
}
|
||||
@ -407,6 +407,9 @@ void runCli() {
|
||||
|
||||
parseThings = parseCli(line);
|
||||
}
|
||||
|
||||
if(controllerThread != NULL)
|
||||
delete controllerThread;
|
||||
}
|
||||
int main(int argc, char** args)
|
||||
{
|
||||
|
||||
@ -11,9 +11,9 @@ class Channel extends React.Component<any, any> {
|
||||
<label>
|
||||
CH{this.props.channelNumber}:
|
||||
{" "}
|
||||
{this.props.verticalWidget.settings[this.props.channelNumber-1].controlMode === ControlMode.Course
|
||||
&& this.props.verticalWidget.timePerDivision[this.props.channelNumber-1].course.value.toString()
|
||||
+ this.props.verticalWidget.timePerDivision[this.props.channelNumber-1].course.unit.toString() + "/div"}
|
||||
{this.props.verticalWidget.settings[this.props.channelNumber-1].controlMode === ControlMode.Coarse
|
||||
&& this.props.verticalWidget.timePerDivision[this.props.channelNumber-1].coarse.value.toString()
|
||||
+ this.props.verticalWidget.timePerDivision[this.props.channelNumber-1].coarse.unit.toString() + "/div"}
|
||||
{this.props.verticalWidget.settings[this.props.channelNumber-1].controlMode === ControlMode.Fine
|
||||
&& (this.props.verticalWidget.settings[this.props.channelNumber-1].probeMode === ProbeMode.x1
|
||||
? this.props.verticalWidget.timePerDivision[this.props.channelNumber-1].fine.value.toString()
|
||||
|
||||
@ -7,8 +7,8 @@ class TimePerDivision extends React.Component<any, any> {
|
||||
render() {
|
||||
return(
|
||||
<div className="TimePerDivisionComponent">
|
||||
{this.props.horizontalWidget.horizontalTimeBase.mode === ControlMode.Course && this.props.horizontalWidget.horizontalTimeBase.course.value.toString()}
|
||||
{this.props.horizontalWidget.horizontalTimeBase.mode === ControlMode.Course && this.props.horizontalWidget.horizontalTimeBase.course.unit.toString() + "/div"}
|
||||
{this.props.horizontalWidget.horizontalTimeBase.mode === ControlMode.Coarse && this.props.horizontalWidget.horizontalTimeBase.coarse.value.toString()}
|
||||
{this.props.horizontalWidget.horizontalTimeBase.mode === ControlMode.Coarse && this.props.horizontalWidget.horizontalTimeBase.coarse.unit.toString() + "/div"}
|
||||
{this.props.horizontalWidget.horizontalTimeBase.mode === ControlMode.Fine && this.props.horizontalWidget.horizontalTimeBase.fine.value.toString()}
|
||||
{this.props.horizontalWidget.horizontalTimeBase.mode === ControlMode.Fine && this.props.horizontalWidget.horizontalTimeBase.fine.unit.toString() + "/div"}
|
||||
</div>
|
||||
|
||||
@ -42,7 +42,7 @@ class Graph extends React.Component<any, any> {
|
||||
}
|
||||
|
||||
render() {
|
||||
let base = this.props.horizontalWidget.horizontalTimeBase.course;
|
||||
let base = this.props.horizontalWidget.horizontalTimeBase.coarse;
|
||||
let dCount = DefaultValues.divisions.time;
|
||||
let winSize = dCount * convertTime(base.value, base.unit, TimeUnit.NanoSecond);
|
||||
let yTicks = [-128, -96, -64, -32, 0, 32, 64, 96, 128]
|
||||
|
||||
@ -60,12 +60,12 @@ class HorizontalWidget extends React.Component<any, any> {
|
||||
|
||||
<div className="TimeBaseMode">
|
||||
<button
|
||||
className="CourseControlButton"
|
||||
onClick={() => this.changeTimeBaseMode(ControlMode.Course)}>
|
||||
className="CoarseControlButton"
|
||||
onClick={() => this.changeTimeBaseMode(ControlMode.Coarse)}>
|
||||
<label
|
||||
className=""
|
||||
style={{fontWeight: this.props.horizontalWidget.horizontalTimeBase.mode === ControlMode.Course ? "bold" : "normal"}}>
|
||||
Course
|
||||
style={{fontWeight: this.props.horizontalWidget.horizontalTimeBase.mode === ControlMode.Coarse ? "bold" : "normal"}}>
|
||||
Coarse
|
||||
</label>
|
||||
</button>
|
||||
<button
|
||||
@ -82,21 +82,21 @@ class HorizontalWidget extends React.Component<any, any> {
|
||||
<div className="HorizontalWidgetAdjustBlock-HorizontalTimeBase">
|
||||
<button
|
||||
className="MinusButton"
|
||||
onClick={() => this.props.horizontalWidget.horizontalTimeBase.mode === ControlMode.Course ? this.decrementTimeBase() : this.decrementTimeBaseFine()}>
|
||||
onClick={() => this.props.horizontalWidget.horizontalTimeBase.mode === ControlMode.Coarse ? this.decrementTimeBase() : this.decrementTimeBaseFine()}>
|
||||
-
|
||||
</button>
|
||||
<label
|
||||
className="AdjustValueBlockHorizontalTimeBase"
|
||||
style={{color: "white"}}
|
||||
>
|
||||
{this.props.horizontalWidget.horizontalTimeBase.mode === ControlMode.Course && this.props.horizontalWidget.horizontalTimeBase.course.value.toString()}
|
||||
{this.props.horizontalWidget.horizontalTimeBase.mode === ControlMode.Course && this.props.horizontalWidget.horizontalTimeBase.course.unit.toString() + "/div"}
|
||||
{this.props.horizontalWidget.horizontalTimeBase.mode === ControlMode.Coarse && this.props.horizontalWidget.horizontalTimeBase.coarse.value.toString()}
|
||||
{this.props.horizontalWidget.horizontalTimeBase.mode === ControlMode.Coarse && this.props.horizontalWidget.horizontalTimeBase.coarse.unit.toString() + "/div"}
|
||||
{this.props.horizontalWidget.horizontalTimeBase.mode === ControlMode.Fine && this.props.horizontalWidget.horizontalTimeBase.fine.value.toString()}
|
||||
{this.props.horizontalWidget.horizontalTimeBase.mode === ControlMode.Fine && this.props.horizontalWidget.horizontalTimeBase.fine.unit.toString() + "/div"}
|
||||
</label>
|
||||
<button
|
||||
className="PlusButton"
|
||||
onClick={() => this.props.horizontalWidget.horizontalTimeBase.mode === ControlMode.Course ? this.incrementTimeBase() : this.incrementTimeBaseFine()}>
|
||||
onClick={() => this.props.horizontalWidget.horizontalTimeBase.mode === ControlMode.Coarse ? this.incrementTimeBase() : this.incrementTimeBaseFine()}>
|
||||
+
|
||||
</button>
|
||||
</div>
|
||||
|
||||
@ -17,18 +17,18 @@ class TriggerWidget extends React.Component<any, any> {
|
||||
|
||||
changeChannel1 = (channelNumber: number) => {
|
||||
let w = this.props.mathWidget;
|
||||
if(w.channel2 != channelNumber) {
|
||||
if(w.channel2 !== channelNumber) {
|
||||
Plumber.getInstance().handleMath(w.mathEnabled, channelNumber, w.channel2, w.mathOperator);
|
||||
this.props.dispatch({type: 'math/changeChannel1', payload: channelNumber });
|
||||
}
|
||||
this.props.dispatch({type: 'math/changeChannel1', payload: channelNumber });
|
||||
}
|
||||
|
||||
changeChannel2 = (channelNumber: number) => {
|
||||
let w = this.props.mathWidget;
|
||||
if(w.channel1 != channelNumber) {
|
||||
if(w.channel1 !== channelNumber) {
|
||||
Plumber.getInstance().handleMath(w.mathEnabled, w.channel1, channelNumber, w.mathOperator);
|
||||
this.props.dispatch({type: 'math/changeChannel2', payload: channelNumber });
|
||||
}
|
||||
this.props.dispatch({type: 'math/changeChannel2', payload: channelNumber });
|
||||
}
|
||||
|
||||
changeOperator = (operator: MathOperators) => {
|
||||
|
||||
@ -31,7 +31,7 @@ class MeasurementsWidget extends React.Component<any, any> {
|
||||
//TODO: unit analysis
|
||||
let channels = this.props.measurementsWidget.displayChannel as boolean[];
|
||||
let channelNum = channels.map(v => v ? 1 : 0) as number[];
|
||||
if(channelNum.reduce((a, b) => a + b) == 0) {
|
||||
if(channelNum.reduce((a, b) => a + b) === 0) {
|
||||
return; //Don't bother C if we don't need to.
|
||||
}
|
||||
let maxArgs: PlumberArgs = {
|
||||
@ -129,8 +129,8 @@ class MeasurementsWidget extends React.Component<any, any> {
|
||||
className="Channel1-MaxValue"
|
||||
style={{color: this.props.settings.colors.channel[0]}}>
|
||||
{this.props.measurementsWidget.max[0].value}
|
||||
{this.props.verticalWidget.settings[0].controlMode === ControlMode.Course
|
||||
&& this.props.verticalWidget.timePerDivision[0].course.unit.toString()}
|
||||
{this.props.verticalWidget.settings[0].controlMode === ControlMode.Coarse
|
||||
&& this.props.verticalWidget.timePerDivision[0].coarse.unit.toString()}
|
||||
{this.props.verticalWidget.settings[0].controlMode === ControlMode.Fine
|
||||
&& + this.props.verticalWidget.timePerDivision[0].fine.unit.toString()}
|
||||
</label>
|
||||
@ -144,8 +144,8 @@ class MeasurementsWidget extends React.Component<any, any> {
|
||||
className="Channel1-MinValue"
|
||||
style={{color: this.props.settings.colors.channel[0]}}>
|
||||
{this.props.measurementsWidget.min[0].value}
|
||||
{this.props.verticalWidget.settings[0].controlMode === ControlMode.Course
|
||||
&& this.props.verticalWidget.timePerDivision[0].course.unit.toString()}
|
||||
{this.props.verticalWidget.settings[0].controlMode === ControlMode.Coarse
|
||||
&& this.props.verticalWidget.timePerDivision[0].coarse.unit.toString()}
|
||||
{this.props.verticalWidget.settings[0].controlMode === ControlMode.Fine
|
||||
&& + this.props.verticalWidget.timePerDivision[0].fine.unit.toString()}
|
||||
</label>
|
||||
@ -169,8 +169,8 @@ class MeasurementsWidget extends React.Component<any, any> {
|
||||
className="Channel2-MaxValue"
|
||||
style={{color: this.props.settings.colors.channel[1]}}>
|
||||
{this.props.measurementsWidget.max[1].value}
|
||||
{this.props.verticalWidget.settings[1].controlMode === ControlMode.Course
|
||||
&& this.props.verticalWidget.timePerDivision[1].course.unit.toString()}
|
||||
{this.props.verticalWidget.settings[1].controlMode === ControlMode.Coarse
|
||||
&& this.props.verticalWidget.timePerDivision[1].coarse.unit.toString()}
|
||||
{this.props.verticalWidget.settings[1].controlMode === ControlMode.Fine
|
||||
&& + this.props.verticalWidget.timePerDivision[1].fine.unit.toString()}
|
||||
</label>
|
||||
@ -184,8 +184,8 @@ class MeasurementsWidget extends React.Component<any, any> {
|
||||
className="Channel2-MinValue"
|
||||
style={{color: this.props.settings.colors.channel[1]}}>
|
||||
{this.props.measurementsWidget.min[1].value}
|
||||
{this.props.verticalWidget.settings[1].controlMode === ControlMode.Course
|
||||
&& this.props.verticalWidget.timePerDivision[1].course.unit.toString()}
|
||||
{this.props.verticalWidget.settings[1].controlMode === ControlMode.Coarse
|
||||
&& this.props.verticalWidget.timePerDivision[1].coarse.unit.toString()}
|
||||
{this.props.verticalWidget.settings[1].controlMode === ControlMode.Fine
|
||||
&& + this.props.verticalWidget.timePerDivision[1].fine.unit.toString()}
|
||||
</label>
|
||||
@ -209,8 +209,8 @@ class MeasurementsWidget extends React.Component<any, any> {
|
||||
className="Channel3-MaxValue"
|
||||
style={{color: this.props.settings.colors.channel[2]}}>
|
||||
{this.props.measurementsWidget.max[2].value}
|
||||
{this.props.verticalWidget.settings[2].controlMode === ControlMode.Course
|
||||
&& this.props.verticalWidget.timePerDivision[2].course.unit.toString()}
|
||||
{this.props.verticalWidget.settings[2].controlMode === ControlMode.Coarse
|
||||
&& this.props.verticalWidget.timePerDivision[2].coarse.unit.toString()}
|
||||
{this.props.verticalWidget.settings[2].controlMode === ControlMode.Fine
|
||||
&& + this.props.verticalWidget.timePerDivision[2].fine.unit.toString()}
|
||||
</label>
|
||||
@ -224,8 +224,8 @@ class MeasurementsWidget extends React.Component<any, any> {
|
||||
className="Channel3-MinValue"
|
||||
style={{color: this.props.settings.colors.channel[2]}}>
|
||||
{this.props.measurementsWidget.min[2].value}
|
||||
{this.props.verticalWidget.settings[2].controlMode === ControlMode.Course
|
||||
&& this.props.verticalWidget.timePerDivision[2].course.unit.toString()}
|
||||
{this.props.verticalWidget.settings[2].controlMode === ControlMode.Coarse
|
||||
&& this.props.verticalWidget.timePerDivision[2].coarse.unit.toString()}
|
||||
{this.props.verticalWidget.settings[2].controlMode === ControlMode.Fine
|
||||
&& + this.props.verticalWidget.timePerDivision[2].fine.unit.toString()}
|
||||
</label>
|
||||
@ -249,8 +249,8 @@ class MeasurementsWidget extends React.Component<any, any> {
|
||||
className="Channel4-MaxValue"
|
||||
style={{color: this.props.settings.colors.channel[3]}}>
|
||||
{this.props.measurementsWidget.max[3].value}
|
||||
{this.props.verticalWidget.settings[3].controlMode === ControlMode.Course
|
||||
&& this.props.verticalWidget.timePerDivision[3].course.unit.toString()}
|
||||
{this.props.verticalWidget.settings[3].controlMode === ControlMode.Coarse
|
||||
&& this.props.verticalWidget.timePerDivision[3].coarse.unit.toString()}
|
||||
{this.props.verticalWidget.settings[3].controlMode === ControlMode.Fine
|
||||
&& + this.props.verticalWidget.timePerDivision[3].fine.unit.toString()}
|
||||
</label>
|
||||
@ -264,8 +264,8 @@ class MeasurementsWidget extends React.Component<any, any> {
|
||||
className="Channel4-MinValue"
|
||||
style={{color: this.props.settings.colors.channel[3]}}>
|
||||
{this.props.measurementsWidget.min[3].value}
|
||||
{this.props.verticalWidget.settings[3].controlMode === ControlMode.Course
|
||||
&& this.props.verticalWidget.timePerDivision[3].course.unit.toString()}
|
||||
{this.props.verticalWidget.settings[3].controlMode === ControlMode.Coarse
|
||||
&& this.props.verticalWidget.timePerDivision[3].coarse.unit.toString()}
|
||||
{this.props.verticalWidget.settings[3].controlMode === ControlMode.Fine
|
||||
&& + this.props.verticalWidget.timePerDivision[3].fine.unit.toString()}
|
||||
</label>
|
||||
|
||||
@ -22,15 +22,16 @@ class TriggerWidget extends React.Component<any, any> {
|
||||
changeChannel = (channelNumber: number) => {
|
||||
let chStatus = (this.props.verticalWidget.settings as any[]).map(x => x.status > 0);
|
||||
let setChState = setChHelper(chStatus[0], chStatus[1], chStatus[2], chStatus[3], channelNumber);
|
||||
Plumber.getInstance().handleSetchState(setChState);
|
||||
Plumber.getInstance().handleSetChState(setChState);
|
||||
this.props.dispatch({type: 'vertical/setChannelOrder', payload: setChState.chOrder});
|
||||
this.props.dispatch({type: 'trigger/changeChannel', payload: channelNumber});
|
||||
this.props.dispatch({type: 'vertical/changeChannelStatus', payload: channelNumber});
|
||||
// this.props.dispatch({type: 'vertical/changeChannelStatus', payload: channelNumber - 1});
|
||||
// This was making it so that clicking on Trigger will activate that channel in the UX. We do not want the UX to show this, only the backend needs to know.
|
||||
}
|
||||
|
||||
// Trigger Type
|
||||
changeTriggerType = (triggerType: TriggerType) => {
|
||||
let edgeNum = (triggerType == TriggerType.RisingEdge) ? 1 : 2;
|
||||
let edgeNum = (triggerType === TriggerType.RisingEdge) ? 1 : 2;
|
||||
let args: PlumberArgs = {
|
||||
headCheck: () => true,
|
||||
bodyCheck: () => true,
|
||||
@ -47,8 +48,9 @@ class TriggerWidget extends React.Component<any, any> {
|
||||
let tw = this.props.triggerWidget;
|
||||
let lvl = tw.triggerLevel[tw.triggerChannel-1];
|
||||
let vw = this.props.verticalWidget;
|
||||
let div = vw.timePerDivision[tw.triggerChannel-1].course;
|
||||
Plumber.getInstance().handleSetLevel(lvl.value+0.1, lvl.unit, div.value, div.unit);
|
||||
let div = vw.timePerDivision[tw.triggerChannel-1].coarse;
|
||||
console.log(lvl);
|
||||
Plumber.getInstance().handleSetLevel(lvl.value+1, lvl.unit, div.value, div.unit);
|
||||
this.props.dispatch({type: 'trigger/increaseTriggerLevelValue'});
|
||||
}
|
||||
|
||||
@ -56,8 +58,9 @@ class TriggerWidget extends React.Component<any, any> {
|
||||
let tw = this.props.triggerWidget;
|
||||
let lvl = tw.triggerLevel[tw.triggerChannel-1];
|
||||
let vw = this.props.verticalWidget;
|
||||
let div = vw.timePerDivision[tw.triggerChannel-1].course;
|
||||
Plumber.getInstance().handleSetLevel(lvl.value-0.1, lvl.unit, div.value, div.unit);
|
||||
let div = vw.timePerDivision[tw.triggerChannel-1].coarse;
|
||||
console.log(lvl);
|
||||
Plumber.getInstance().handleSetLevel(lvl.value-1, lvl.unit, div.value, div.unit);
|
||||
this.props.dispatch({type: 'trigger/decreaseTriggerLevelValue'});
|
||||
}
|
||||
|
||||
@ -66,7 +69,7 @@ class TriggerWidget extends React.Component<any, any> {
|
||||
let tw = this.props.triggerWidget;
|
||||
let lvl = tw.triggerLevel[tw.triggerChannel-1];
|
||||
let vw = this.props.verticalWidget;
|
||||
let div = vw.timePerDivision[tw.triggerChannel-1].course;
|
||||
let div = vw.timePerDivision[tw.triggerChannel-1].coarse;
|
||||
Plumber.getInstance().handleSetLevel(lvl.value, voltageUnit, div.value, div.unit);
|
||||
this.props.dispatch({type: 'trigger/changeTriggerLevelUnit', payload: voltageUnit});
|
||||
}
|
||||
|
||||
@ -21,14 +21,19 @@ class VerticalWidget extends React.Component<any, any> {
|
||||
let v = this.props.verticalWidget;
|
||||
let idx = v.timePerDivision[v.activeChannel-1].index - 1;
|
||||
Plumber.getInstance().handleVert(v.activeChannel, idx);
|
||||
this.props.dispatch({type: 'vertical/increaseTimePerDivision'});
|
||||
if(idx !== 0) {
|
||||
this.props.dispatch({type: 'vertical/increaseTimePerDivision'});
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
decrementTimePerDivision = () => {
|
||||
let v = this.props.verticalWidget;
|
||||
let idx = v.timePerDivision[v.activeChannel-1].index + 1;
|
||||
Plumber.getInstance().handleVert(v.activeChannel, idx);
|
||||
this.props.dispatch({type: 'vertical/decreaseTimePerDivision'});
|
||||
if(idx < 12) {
|
||||
this.props.dispatch({type: 'vertical/decreaseTimePerDivision'});
|
||||
}
|
||||
}
|
||||
|
||||
incrementTimePerDivisionFine = () => {
|
||||
@ -64,7 +69,7 @@ class VerticalWidget extends React.Component<any, any> {
|
||||
chStatus[channelNumber] = !chStatus[channelNumber];
|
||||
let triggerCh = this.props.triggerWidget.triggerChannel;
|
||||
let setChState = setChHelper(chStatus[0], chStatus[1], chStatus[2], chStatus[3], triggerCh);
|
||||
Plumber.getInstance().handleSetchState(setChState);
|
||||
Plumber.getInstance().handleSetChState(setChState);
|
||||
this.props.dispatch({type: 'vertical/setChannelOrder', payload: setChState.chOrder})
|
||||
this.props.dispatch({type: 'trigger/changeChannel', payload: triggerCh});
|
||||
this.props.dispatch({type: 'vertical/changeChannelStatus', payload: channelNumber});
|
||||
@ -138,12 +143,12 @@ class VerticalWidget extends React.Component<any, any> {
|
||||
</div>
|
||||
<div className="DivisionMode">
|
||||
<button
|
||||
className="CourseControlButton"
|
||||
onClick={() => this.changeControlMode(ControlMode.Course)}>
|
||||
className="CoarseControlButton"
|
||||
onClick={() => this.changeControlMode(ControlMode.Coarse)}>
|
||||
<label
|
||||
className=""
|
||||
style={{fontWeight: this.props.verticalWidget.settings[this.props.verticalWidget.activeChannel-1].controlMode === ControlMode.Course ? "bold" : "normal"}}>
|
||||
Course
|
||||
style={{fontWeight: this.props.verticalWidget.settings[this.props.verticalWidget.activeChannel-1].controlMode === ControlMode.Coarse ? "bold" : "normal"}}>
|
||||
Coarse
|
||||
</label>
|
||||
</button>
|
||||
<button
|
||||
@ -160,16 +165,16 @@ class VerticalWidget extends React.Component<any, any> {
|
||||
<div className="VerticalWidgetAdjustBlock-TimePerDivision">
|
||||
<button
|
||||
className="MinusButton"
|
||||
onClick={() => this.props.verticalWidget.settings[this.props.verticalWidget.activeChannel-1].controlMode === ControlMode.Course ? this.decrementTimePerDivision() : this.decrementTimePerDivisionFine()}>
|
||||
onClick={() => this.props.verticalWidget.settings[this.props.verticalWidget.activeChannel-1].controlMode === ControlMode.Coarse ? this.decrementTimePerDivision() : this.decrementTimePerDivisionFine()}>
|
||||
-
|
||||
</button>
|
||||
<label
|
||||
className="AdjustValueBlockTimePerDivision"
|
||||
style={{color: this.props.settings.colors.channel[this.props.verticalWidget.activeChannel-1]}}
|
||||
>
|
||||
{this.props.verticalWidget.settings[this.props.verticalWidget.activeChannel-1].controlMode === ControlMode.Course
|
||||
&& this.props.verticalWidget.timePerDivision[this.props.verticalWidget.activeChannel-1].course.value.toString()
|
||||
+ this.props.verticalWidget.timePerDivision[this.props.verticalWidget.activeChannel-1].course.unit.toString() + "/div"}
|
||||
{this.props.verticalWidget.settings[this.props.verticalWidget.activeChannel-1].controlMode === ControlMode.Coarse
|
||||
&& this.props.verticalWidget.timePerDivision[this.props.verticalWidget.activeChannel-1].coarse.value.toString()
|
||||
+ this.props.verticalWidget.timePerDivision[this.props.verticalWidget.activeChannel-1].coarse.unit.toString() + "/div"}
|
||||
{this.props.verticalWidget.settings[this.props.verticalWidget.activeChannel-1].controlMode === ControlMode.Fine
|
||||
&& (this.props.verticalWidget.settings[this.props.verticalWidget.activeChannel-1].probeMode === ProbeMode.x1
|
||||
? this.props.verticalWidget.timePerDivision[this.props.verticalWidget.activeChannel-1].fine.value.toString()
|
||||
@ -178,7 +183,7 @@ class VerticalWidget extends React.Component<any, any> {
|
||||
</label>
|
||||
<button
|
||||
className="PlusButton"
|
||||
onClick={() => this.props.verticalWidget.settings[this.props.verticalWidget.activeChannel-1].controlMode === ControlMode.Course ? this.incrementTimePerDivision() : this.incrementTimePerDivisionFine()}>
|
||||
onClick={() => this.props.verticalWidget.settings[this.props.verticalWidget.activeChannel-1].controlMode === ControlMode.Coarse ? this.incrementTimePerDivision() : this.incrementTimePerDivisionFine()}>
|
||||
+
|
||||
</button>
|
||||
</div>
|
||||
|
||||
@ -248,9 +248,11 @@ let divisions = {
|
||||
time: 10
|
||||
}
|
||||
|
||||
export default {
|
||||
let DefaultValues = {
|
||||
x1ProbeValues,
|
||||
x10ProbeValues,
|
||||
horizontalTimeBases,
|
||||
divisions
|
||||
};
|
||||
}
|
||||
|
||||
export default DefaultValues;
|
||||
@ -1,5 +1,5 @@
|
||||
enum ControlMode {
|
||||
Course,
|
||||
Coarse,
|
||||
Fine
|
||||
}
|
||||
|
||||
|
||||
@ -32,7 +32,7 @@
|
||||
font-weight: bold;
|
||||
}
|
||||
|
||||
.CourseControlButton {
|
||||
.CoarseControlButton {
|
||||
margin-right: 1vw;
|
||||
margin-left: 1vw;
|
||||
margin-bottom: 1vh;
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user