Adding the KiCad Design for the FPGA Module Board with no DRC errors

Hardware/KiCad/FPGA_Module_Rev2/README.md

@@ -0,0 +1,3 @@
+<a rel="license" href="http://creativecommons.org/licenses/by/4.0/">
+<img alt="Creative Commons License" style="border-width:0" src="https://i.creativecommons.org/l/by/4.0/88x31.png"/>
+</a><br/>All the hardware for this project is licensed under a <a rel="license" href="http://creativecommons.org/licenses/by/4.0/">Creative Commons Attribution 4.0 International License</a>.

Hardware/KiCad/FPGA_Module_Rev2/TS_FPGA_Module_Rev2.kicad_prl

@@ -1,7 +1,7 @@
 {
   "board": {
-    "active_layer": 0,
-    "active_layer_preset": "Top Layer",
+    "active_layer": 39,
+    "active_layer_preset": "",
     "auto_track_width": true,
     "hidden_netclasses": [],
     "hidden_nets": [],
@@ -64,11 +64,11 @@
       36,
       40
     ],
-    "visible_layers": "0001080_00000001",
+    "visible_layers": "0001080_80000001",
     "zone_display_mode": 0
   },
   "meta": {
-    "filename": "Thunderscope.kicad_prl",
+    "filename": "TS_FPGA_Module_Rev2.kicad_prl",
     "version": 3
   },
   "project": {

Hardware/KiCad/FPGA_Module_Rev2/TS_FPGA_Module_Rev2.kicad_pro

@@ -35,8 +35,8 @@
         "other_text_upright": false,
         "pads": {
           "drill": 3.2,
-          "height": 3.2,
-          "width": 3.2
+          "height": 5.2,
+          "width": 5.2
         },
         "silk_line_width": 0.15,
         "silk_text_italic": false,
@@ -56,7 +56,7 @@
         }
       ],
       "drc_exclusions": [
-        "solder_mask_bridge|138538281|112491419|f10d398f-94b9-40e6-910b-55f634d09b4d|2b63c60d-776a-4350-a46d-3638dd2e9007",
+        "solder_mask_bridge|138732030|112297670|f10d398f-94b9-40e6-910b-55f634d09b4d|d1a4033f-8378-45fd-b92e-8955092590c3",
         "via_dangling|140751100|115403600|919ea3d4-cfb3-4632-ac5b-5300ef71bff7|00000000-0000-0000-0000-000000000000"
       ],
       "meta": {
@@ -90,9 +90,9 @@
         "missing_courtyard": "ignore",
         "missing_footprint": "error",
         "net_conflict": "error",
-        "npth_inside_courtyard": "ignore",
+        "npth_inside_courtyard": "warning",
         "padstack": "warning",
-        "pth_inside_courtyard": "ignore",
+        "pth_inside_courtyard": "warning",
         "shorting_items": "error",
         "silk_edge_clearance": "error",
         "silk_over_copper": "warning",
@@ -109,7 +109,7 @@
         "tracks_crossing": "error",
         "unconnected_items": "error",
         "unresolved_variable": "error",
-        "via_dangling": "error",
+        "via_dangling": "warning",
         "zones_intersect": "error"
       },
       "rules": {
@@ -491,7 +491,7 @@
       "no_connect_connected": "warning",
       "no_connect_dangling": "warning",
       "pin_not_connected": "error",
-      "pin_not_driven": "error",
+      "pin_not_driven": "ignore",
       "pin_to_pin": "error",
       "power_pin_not_driven": "ignore",
       "similar_labels": "warning",
@@ -533,7 +533,17 @@
     "meta": {
       "version": 3
     },
-    "net_colors": null,
+    "net_colors": {
+      "+1V0": "rgb(0, 0, 255)",
+      "+1V0_MGT": "rgb(0, 0, 255)",
+      "+1V2_MGT": "rgb(255, 153, 0)",
+      "+1V35": "rgb(0, 255, 255)",
+      "+1V8": "rgb(255, 0, 255)",
+      "+3.3V": "rgb(0, 255, 0)",
+      "+3V3_IN": "rgb(0, 255, 0)",
+      "GND": "rgb(255, 255, 0)",
+      "GNDA": "rgb(255, 255, 0)"
+    },
     "netclass_assignments": null,
     "netclass_patterns": []
   },
@@ -594,24 +604,24 @@
   },
   "sheets": [
     [
-      "6b735303-d28c-464a-808f-5226a2b5e25c",
-      "Connectors"
+      "fafe3e93-a008-4527-acc3-c5f1c7f50c1a",
+      ""
     ],
     [
-      "d5369f19-1d04-48bb-b113-8fac117fa2c0",
-      "FPGA_Bank_IO"
+      "b51d681c-ce34-43c4-a51d-550b36f8a8af",
+      "FPGA_CFG"
     ],
     [
       "68aa6128-56c4-4799-97cf-58f73419a96d",
-      "FPGA_Banks_DDR3"
+      "FPGA_Banks_14_15_DDR3"
     ],
     [
       "e6294fa0-c86d-4f48-a97b-01b636f82c55",
       "FPGA_MGT"
     ],
     [
-      "b51d681c-ce34-43c4-a51d-550b36f8a8af",
-      "FPGA_CFG"
+      "d5369f19-1d04-48bb-b113-8fac117fa2c0",
+      "FPGA_Bank_34_IO"
     ],
     [
       "64736990-fdbb-45b6-a6fe-226ec4e31c68",
@@ -619,11 +629,7 @@
     ],
     [
       "9ef6784b-c4f0-4982-9777-5b7155fec79d",
-      "PWR"
-    ],
-    [
-      "fafe3e93-a008-4527-acc3-c5f1c7f50c1a",
-      ""
+      "Board_PWR"
     ]
   ],
   "text_variables": {

Hardware/KiCad/FPGA_Module_Rev2/fp-lib-table

@@ -0,0 +1,5 @@
+(fp_lib_table
+  (version 7)
+  (lib (name "DSO.PcbLib")(type "Altium Designer")(uri "${KIPRJMOD}/DSO.PcbLib")(options "")(descr ""))
+  (lib (name "Custom_Footprints")(type "KiCad")(uri "${KIPRJMOD}/Custom_Footprints.pretty")(options "")(descr ""))
+)

Hardware/KiCad/FPGA_Module_Rev2/sym-lib-table

@@ -2,4 +2,6 @@
   (version 7)
   (lib (name "Thunderscope-altium-import")(type "KiCad")(uri "${KIPRJMOD}/Thunderscope-altium-import.kicad_sym")(options "")(descr ""))
   (lib (name "Custom_Power_Symbols")(type "KiCad")(uri "${KIPRJMOD}/Custom_Power_Symbols.kicad_sym")(options "")(descr ""))
+  (lib (name "scratch-altium-import")(type "KiCad")(uri "${KIPRJMOD}/scratch-altium-import.kicad_sym")(options "")(descr ""))
+  (lib (name "root_0_mirrored_conn lshm-150-04.0-l-dv-a-s-k-tr_1")(type "KiCad")(uri "${KIPRJMOD}/root_0_mirrored_conn lshm-150-04.0-l-dv-a-s-k-tr_1.kicad_sym")(options "")(descr ""))
 )