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Rev 5 WIP
Added probe comp variants
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parent
be80acdca3
commit
992a437638
Hardware/KiCad/Thunderscope_Rev5
ACQ_FE_VREG.kicad_schADC.kicad_schCON_PCIe_X4.kicad_schFE.kicad_schFE_Channel.kicad_schFPGA.kicad_schFPGA_Bank_IO.kicad_schFPGA_CFG_MGT.kicad_schFPGA_PWR.kicad_schFPGA_VREG.kicad_schM2_KEY_M.kicad_schPLL.kicad_schThunderscope_Rev5.kicad_prlThunderscope_Rev5.kicad_proThunderscope_Rev5.kicad_schThunderscope_Rev5.kicad_symThunderscope_Rev5.pdf
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@ -1,7 +1,7 @@
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{
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"board": {
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"active_layer": 19,
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"active_layer_preset": "",
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"active_layer": 2,
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"active_layer_preset": "Back Layers",
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"auto_track_width": true,
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"hidden_netclasses": [],
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"hidden_nets": [],
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@ -29,42 +29,26 @@
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"zones": true
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},
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"visible_items": [
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0,
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43
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"vias",
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"footprint_text",
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"footprint_anchors",
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"ratsnest",
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"grid",
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"footprints_front",
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"footprints_back",
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"footprint_values",
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"footprint_references",
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"tracks",
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"drc_errors",
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"drawing_sheet",
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"bitmaps",
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"pads",
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"drc_warnings",
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"locked_item_shadows",
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"conflict_shadows",
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"shapes"
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],
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"visible_layers": "ffffffff_ffffffff",
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"visible_layers": "00000000_00000000_00000002_2200888c",
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"zone_display_mode": 0
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},
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"git": {
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@ -75,7 +59,7 @@
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},
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"meta": {
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"filename": "Thunderscope_Rev5.kicad_prl",
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"version": 4
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"version": 5
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},
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"net_inspector_panel": {
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"col_hidden": [
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@ -138,6 +122,7 @@
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"sort_ascending": true,
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"sorting_column": 0
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},
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"open_jobsets": [],
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"project": {
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"files": []
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},
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@ -91,9 +91,11 @@
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"lib_footprint_mismatch": "warning",
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"malformed_courtyard": "error",
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"microvia_drill_out_of_range": "error",
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"mirrored_text_on_front_layer": "warning",
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"missing_courtyard": "ignore",
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"missing_footprint": "warning",
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"net_conflict": "warning",
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"nonmirrored_text_on_back_layer": "warning",
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"npth_inside_courtyard": "ignore",
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"padstack": "warning",
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"pth_inside_courtyard": "ignore",
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@ -487,7 +489,7 @@
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},
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"meta": {
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"filename": "Thunderscope_Rev5.kicad_pro",
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"version": 2
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"version": 3
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},
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"net_settings": {
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"classes": [
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@ -533,7 +535,7 @@
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},
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"schematic": {
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"annotate_start_num": 0,
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"bom_export_filename": "${PROJECTNAME}.csv",
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"bom_export_filename": "TS-PCIE.csv",
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"bom_fmt_presets": [],
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"bom_fmt_settings": {
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"field_delimiter": ",",
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@ -715,6 +717,12 @@
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"label": "Description",
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"name": "Description",
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"show": false
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},
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{
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"group_by": false,
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"label": "SUPPLIER PART NUMBER",
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"name": "SUPPLIER PART NUMBER",
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"show": false
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}
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],
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"filter_string": "",
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@ -722,7 +730,7 @@
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"include_excluded_from_bom": false,
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"name": "",
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"sort_asc": true,
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"sort_field": "${EXCLUDE_FROM_BOARD}"
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"sort_field": "Reference"
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},
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"connection_grid_size": 50.0,
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"drawing": {
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@ -805,14 +813,6 @@
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"0f922f52-a6e9-41f0-8991-df4889546a95",
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"FPGA"
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],
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[
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"038472ca-999a-4bdd-b362-e2f5a3e05e32",
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"FPGA Power Inputs"
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],
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[
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"578d4253-e95a-4587-beab-a07f275c1e48",
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"FPGA Voltage Regs"
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],
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[
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"3dc749f1-bb54-4961-a356-74c6bb9263ea",
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"FPGA IO Banks"
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@ -821,6 +821,14 @@
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"9e3a6ae2-4fbe-4717-950b-8a09c623e35a",
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"FPGA Config and Transceivers"
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],
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[
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"038472ca-999a-4bdd-b362-e2f5a3e05e32",
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"FPGA Power Inputs"
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],
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[
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"578d4253-e95a-4587-beab-a07f275c1e48",
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"FPGA Voltage Regs"
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],
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[
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"95dd7985-f010-4388-84bb-3ad8f1a365a2",
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"TS-PCIe Components"
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