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Switched from normal to strict ordering to save LUTs
This commit is contained in:
Aleksa
parent
747d00166e
commit
9c54824470
Firmware/Artix7_PCIe/dso_top
dso_top.cache
ip/2020.1/8abae3f1fc384d9a
8abae3f1fc384d9a.xcidesign_1_mig_7series_0_0.dcpdesign_1_mig_7series_0_0_sim_netlist.vdesign_1_mig_7series_0_0_sim_netlist.vhdldesign_1_mig_7series_0_0_stub.vdesign_1_mig_7series_0_0_stub.vhdl
wt
dso_top.runs
.jobs
design_1_mig_7series_0_0_synth_1
.vivado.begin.rstdesign_1_mig_7series_0_0.dcpdesign_1_mig_7series_0_0.vdsdesign_1_mig_7series_0_0_utilization_synth.pbdesign_1_mig_7series_0_0_utilization_synth.rptgen_run.xmlrunme.logvivado.jouvivado.pb
impl_1
.init_design.begin.rst.opt_design.begin.rst.place_design.begin.rst.route_design.begin.rst.vivado.begin.rst.write_bitstream.begin.rstdso_top.bindso_top.bitdso_top.hwdefdso_top.vdidso_top_bus_skew_routed.pbdso_top_bus_skew_routed.rptdso_top_bus_skew_routed.rpxdso_top_clock_utilization_routed.rptdso_top_control_sets_placed.rptdso_top_drc_opted.rptdso_top_drc_opted.rpxdso_top_drc_routed.pbdso_top_drc_routed.rptdso_top_drc_routed.rpxdso_top_io_placed.rptdso_top_methodology_drc_routed.rptdso_top_methodology_drc_routed.rpxdso_top_opt.dcpdso_top_placed.dcpdso_top_power_routed.rptdso_top_power_routed.rpxdso_top_power_summary_routed.pbdso_top_route_status.pbdso_top_route_status.rptdso_top_routed.dcpdso_top_timing_summary_routed.pbdso_top_timing_summary_routed.rptdso_top_timing_summary_routed.rpxdso_top_utilization_placed.pbdso_top_utilization_placed.rptgen_run.xmlinit_design.pbopt_design.pbplace_design.pbroute_design.pbrunme.logusage_statistics_webtalk.htmlusage_statistics_webtalk.xmlvivado.jouvivado.pbwrite_bitstream.pb
synth_1
dso_top.srcs/sources_1/bd/design_1
design_1.bddesign_1.bxml
dso_top.xprvivado.jouvivado.logvivado_7464.backup.jouvivado_7464.backup.loghdl
hw_handoff
ip/design_1_mig_7series_0_0
design_1_mig_7series_0_0.dcpdesign_1_mig_7series_0_0.xcidesign_1_mig_7series_0_0.xml
design_1_mig_7series_0_0
design_1_mig_7series_0_0_sim_netlist.vdesign_1_mig_7series_0_0_sim_netlist.vhdldesign_1_mig_7series_0_0_stub.vdesign_1_mig_7series_0_0_stub.vhdlmig_a.prjxil_txt.insim
synth
ui
@ -0,0 +1,49 @@
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||||
<?xml version="1.0" encoding="UTF-8"?>
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||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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||||
<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>ipcache</spirit:library>
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<spirit:name>8abae3f1fc384d9a</spirit:name>
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<spirit:version>0</spirit:version>
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<spirit:componentInstances>
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<spirit:componentInstance>
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<spirit:instanceName>design_1_mig_7series_0_0</spirit:instanceName>
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<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="mig_7series" spirit:version="4.2"/>
|
||||
<spirit:configurableElementValues>
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||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT0.FREQ_HZ">10</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT1.FREQ_HZ">10</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT2.FREQ_HZ">10</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT3.FREQ_HZ">10</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT4.FREQ_HZ">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_CLK_I.FREQ_HZ">200000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BOARD_MIG_PARAM">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_mig_7series_0_0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MIG_DONT_TOUCH_PARAM">Custom</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.XML_INPUT_FILE">mig_a.prj</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a100t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fgg484</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">8abae3f1fc384d9a</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">153</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISOPTS">-directive areaoptimized_high -control_set_opt_threshold 1</spirit:configurableElementValue>
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</spirit:configurableElementValues>
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</spirit:componentInstance>
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</spirit:componentInstances>
|
||||
</spirit:design>
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||||
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@ -0,0 +1,90 @@
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// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
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||||
// Date : Wed May 19 10:55:16 2021
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||||
// Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
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// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_mig_7series_0_0_stub.v
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// Design : design_1_mig_7series_0_0
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// Purpose : Stub declaration of top-level module interface
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||||
// Device : xc7a100tfgg484-2
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||||
// --------------------------------------------------------------------------------
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(ddr3_dq, ddr3_dqs_n, ddr3_dqs_p, ddr3_addr,
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ddr3_ba, ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, ddr3_ck_p, ddr3_ck_n, ddr3_cke,
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ddr3_cs_n, ddr3_dm, ddr3_odt, sys_clk_i, ui_clk, ui_clk_sync_rst, mmcm_locked, aresetn,
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app_sr_active, app_ref_ack, app_zq_ack, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize,
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s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awqos, s_axi_awvalid,
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s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready,
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s_axi_bready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_arid, s_axi_araddr, s_axi_arlen,
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s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arqos,
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s_axi_arvalid, s_axi_arready, s_axi_rready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast,
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s_axi_rvalid, init_calib_complete, device_temp, sys_rst)
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/* synthesis syn_black_box black_box_pad_pin="ddr3_dq[31:0],ddr3_dqs_n[3:0],ddr3_dqs_p[3:0],ddr3_addr[14:0],ddr3_ba[2:0],ddr3_ras_n,ddr3_cas_n,ddr3_we_n,ddr3_reset_n,ddr3_ck_p[0:0],ddr3_ck_n[0:0],ddr3_cke[0:0],ddr3_cs_n[0:0],ddr3_dm[3:0],ddr3_odt[0:0],sys_clk_i,ui_clk,ui_clk_sync_rst,mmcm_locked,aresetn,app_sr_active,app_ref_ack,app_zq_ack,s_axi_awid[0:0],s_axi_awaddr[29:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[255:0],s_axi_wstrb[31:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bready,s_axi_bid[0:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_arid[0:0],s_axi_araddr[29:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rready,s_axi_rid[0:0],s_axi_rdata[255:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,init_calib_complete,device_temp[11:0],sys_rst" */;
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inout [31:0]ddr3_dq;
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inout [3:0]ddr3_dqs_n;
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inout [3:0]ddr3_dqs_p;
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output [14:0]ddr3_addr;
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output [2:0]ddr3_ba;
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output ddr3_ras_n;
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output ddr3_cas_n;
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output ddr3_we_n;
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output ddr3_reset_n;
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output [0:0]ddr3_ck_p;
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output [0:0]ddr3_ck_n;
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output [0:0]ddr3_cke;
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output [0:0]ddr3_cs_n;
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output [3:0]ddr3_dm;
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output [0:0]ddr3_odt;
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input sys_clk_i;
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output ui_clk;
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output ui_clk_sync_rst;
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output mmcm_locked;
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input aresetn;
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output app_sr_active;
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output app_ref_ack;
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output app_zq_ack;
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input [0:0]s_axi_awid;
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input [29:0]s_axi_awaddr;
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input [7:0]s_axi_awlen;
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input [2:0]s_axi_awsize;
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input [1:0]s_axi_awburst;
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input [0:0]s_axi_awlock;
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input [3:0]s_axi_awcache;
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input [2:0]s_axi_awprot;
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input [3:0]s_axi_awqos;
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input s_axi_awvalid;
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output s_axi_awready;
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input [255:0]s_axi_wdata;
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input [31:0]s_axi_wstrb;
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input s_axi_wlast;
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input s_axi_wvalid;
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output s_axi_wready;
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input s_axi_bready;
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output [0:0]s_axi_bid;
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output [1:0]s_axi_bresp;
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output s_axi_bvalid;
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input [0:0]s_axi_arid;
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input [29:0]s_axi_araddr;
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input [7:0]s_axi_arlen;
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input [2:0]s_axi_arsize;
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input [1:0]s_axi_arburst;
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input [0:0]s_axi_arlock;
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input [3:0]s_axi_arcache;
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input [2:0]s_axi_arprot;
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input [3:0]s_axi_arqos;
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input s_axi_arvalid;
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output s_axi_arready;
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input s_axi_rready;
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output [0:0]s_axi_rid;
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output [255:0]s_axi_rdata;
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output [1:0]s_axi_rresp;
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output s_axi_rlast;
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output s_axi_rvalid;
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output init_calib_complete;
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output [11:0]device_temp;
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input sys_rst;
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endmodule
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@ -0,0 +1,90 @@
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-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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-- --------------------------------------------------------------------------------
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-- Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
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-- Date : Wed May 19 10:55:16 2021
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-- Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
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-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_mig_7series_0_0_stub.vhdl
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-- Design : design_1_mig_7series_0_0
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-- Purpose : Stub declaration of top-level module interface
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-- Device : xc7a100tfgg484-2
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-- --------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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Port (
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ddr3_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
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ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
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ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
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ddr3_addr : out STD_LOGIC_VECTOR ( 14 downto 0 );
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ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
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ddr3_ras_n : out STD_LOGIC;
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ddr3_cas_n : out STD_LOGIC;
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ddr3_we_n : out STD_LOGIC;
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||||
ddr3_reset_n : out STD_LOGIC;
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ddr3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
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ddr3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
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ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
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ddr3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
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ddr3_dm : out STD_LOGIC_VECTOR ( 3 downto 0 );
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ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
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sys_clk_i : in STD_LOGIC;
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ui_clk : out STD_LOGIC;
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ui_clk_sync_rst : out STD_LOGIC;
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mmcm_locked : out STD_LOGIC;
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aresetn : in STD_LOGIC;
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app_sr_active : out STD_LOGIC;
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app_ref_ack : out STD_LOGIC;
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app_zq_ack : out STD_LOGIC;
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s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
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s_axi_awaddr : in STD_LOGIC_VECTOR ( 29 downto 0 );
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s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
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s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
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||||
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
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s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
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||||
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
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s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
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||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
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s_axi_wdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
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||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
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s_axi_wlast : in STD_LOGIC;
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s_axi_wvalid : in STD_LOGIC;
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s_axi_wready : out STD_LOGIC;
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s_axi_bready : in STD_LOGIC;
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s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
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s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
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s_axi_bvalid : out STD_LOGIC;
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s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
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s_axi_araddr : in STD_LOGIC_VECTOR ( 29 downto 0 );
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||||
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
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||||
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
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||||
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
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||||
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
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||||
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
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||||
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
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||||
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
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||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
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s_axi_rready : in STD_LOGIC;
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||||
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
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||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 255 downto 0 );
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||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rlast : out STD_LOGIC;
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
init_calib_complete : out STD_LOGIC;
|
||||
device_temp : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
sys_rst : in STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "ddr3_dq[31:0],ddr3_dqs_n[3:0],ddr3_dqs_p[3:0],ddr3_addr[14:0],ddr3_ba[2:0],ddr3_ras_n,ddr3_cas_n,ddr3_we_n,ddr3_reset_n,ddr3_ck_p[0:0],ddr3_ck_n[0:0],ddr3_cke[0:0],ddr3_cs_n[0:0],ddr3_dm[3:0],ddr3_odt[0:0],sys_clk_i,ui_clk,ui_clk_sync_rst,mmcm_locked,aresetn,app_sr_active,app_ref_ack,app_zq_ack,s_axi_awid[0:0],s_axi_awaddr[29:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[255:0],s_axi_wstrb[31:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bready,s_axi_bid[0:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_arid[0:0],s_axi_araddr[29:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rready,s_axi_rid[0:0],s_axi_rdata[255:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,init_calib_complete,device_temp[11:0],sys_rst";
|
||||
begin
|
||||
end;
|
||||
@ -1,16 +1,16 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3536:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3538:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6366676d656d7061727463686f6f7365725f7461626c65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6d65737361676573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:3232:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6d65737361676573:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:3235:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6d6d616e6473696e7075745f747970655f74636c5f636f6d6d616e645f68657265:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f7265747265657461626c6570616e656c5f636f72655f747265655f7461626c65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:64657369676e74696d696e6773756d73656374696f6e70616e656c5f776f7273745f6e656761746976655f736c61636b:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e6d656e755f72657365745f616e645f67656e65726174655f6f75747075745f70726f6475637473:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:3931:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3637:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3535:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:3932:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3732:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3537:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6861636763746578746669656c645f76616c75655f6f665f7370656369666965645f706172616d65746572:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6861636763746578746669656c645f76616c75655f6f665f7370656369666965645f706172616d657465725f6d616e75616c:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f636c6f7365:31:00:00
|
||||
@ -18,17 +18,17 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68666f6c64657263686f6f73657268656c706572735f75705f6f6e655f6c6576656c:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68696e70757468616e646c65725f746f67676c655f626c6f636b5f636f6d6d656e7473:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:686a66696c6563686f6f736572726563656e746c697374707265766965775f726563656e745f6469726563746f72696573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68617264776172657472656570616e656c5f68617264776172655f747265655f7461626c65:3138:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68617264776172657472656570616e656c5f68617264776172655f747265655f7461626c65:3139:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f636865636b706f696e74:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6578706f7274:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:3532:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:3534:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6970:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6f70656e5f726563656e745f70726f6a656374:3232:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:3338:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6f70656e5f726563656e745f70726f6a656374:3233:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:3430:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746578745f656469746f72:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746f6f6c73:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d69676c6963656e7365706167655f616363657074:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d696770696e73656c656374696f6e706167655f76616c6964617465:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746f6f6c73:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d69676c6963656e7365706167655f616363657074:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d696770696e73656c656374696f6e706167655f76616c6964617465:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f646973636172645f757365725f637265617465645f6d65737361676573:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f7365766572697479:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:37:00:00
|
||||
@ -37,35 +37,35 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f7761726e696e675f6d65737361676573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e6176696761626c6574696d696e677265706f72747461625f74696d696e675f7265706f72745f6e617669676174696f6e5f74726565:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f636f6e6669675f6d656d6f7279:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f626f6f745f646576696365:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f696d706c5f73657474696e6773:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f68617264776172655f6d616e61676572:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f68617264776172655f6d616e61676572:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f70726f6a656374:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f70726f6772616d5f636f6e6669675f6d656d6f7279:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f70726f6772616d5f636f6e6669675f6d656d6f7279:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f726567656e65726174655f6c61796f7574:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f736176655f70726f6a6563745f6173:3134:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f736176655f7273625f64657369676e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f76616c69646174655f7273625f64657369676e:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:3139:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:3230:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f73797374656d:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706174686d656e755f7365745f66616c73655f70617468:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706174686d656e755f7365745f6d6178696d756d5f64656c6179:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706174686d656e755f7365745f6d756c74696379636c655f70617468:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d6366676d656d6469616c6f675f636f6e74656e74735f6f665f636f6e66696775726174696f6e5f66696c65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d64656275677461625f6f70656e5f746172676574:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d64656275677461625f6f70656e5f746172676574:3132:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d6f7074696f6e7370616e656c696d706c5f7374726174656779:3236:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f6261636b67726f756e64:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f63616e63656c:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f63686f6f73655f70726f6a6563745f6c6f636174696f6e:3134:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:3135:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473756d6d61727974696d696e6770616e656c5f70726f6a6563745f73756d6d6172795f74696d696e675f70616e656c5f746162626564:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473756d6d6172797574696c697a6174696f6e70616e656c5f70726f6a6563745f73756d6d6172795f7574696c697a6174696f6e5f70616e656c5f746162626564:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473756d6d6172797574696c697a6174696f6e70616e656c5f70726f6a6563745f73756d6d6172795f7574696c697a6174696f6e5f70616e656c5f746162626564:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f70726f70657274696573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72756e6761646765745f72756e5f6761646765745f7461626265645f70616e65:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72756e6761646765745f7461626c65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f73617665:3134:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f73617665:3135:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73656c6563746d656e755f686967686c69676874:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73656c6563746d656e755f6d61726b:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:31:00:00
|
||||
@ -77,4 +77,4 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73797374656d6275696c646572766965775f6f7074696d697a655f726f7574696e67:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e676974656d666c61747461626c6570616e656c5f666c6f6f72706c616e6e696e67:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e676974656d666c61747461626c6570616e656c5f7461626c65:39:00:00
|
||||
eof:2617920610
|
||||
eof:397969358
|
||||
|
||||
@ -1,21 +1,21 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6164646366676d656d:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65727362626c6f636b:3330:00:00
|
||||
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|
||||
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|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697470726f70657274696573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:66696c6565786974:36:00:00
|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:66696c6565786974:37:00:00
|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:32:00:00
|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d6366676d656d:3132:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:32:00:00
|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:3231:00:00
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b70726f6a6563746d616e61676572:3131:00:00
|
||||
eof:698484351
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b70726f6a6563746d616e61676572:3132:00:00
|
||||
eof:2166436748
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
version:1
|
||||
57656254616c6b5472616e736d697373696f6e417474656d70746564:16
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:17
|
||||
57656254616c6b5472616e736d697373696f6e417474656d70746564:17
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:18
|
||||
eof:
|
||||
|
||||
@ -35,6 +35,6 @@ version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323873:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313036302e3037384d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:34342e3231314d42:00:00
|
||||
eof:983042598
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313035382e3533314d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:34332e3030344d42:00:00
|
||||
eof:122310102
|
||||
|
||||
@ -3,10 +3,10 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Tue May 18 14:42:15 2021">
|
||||
<application name="pa" timeStamp="Wed May 19 11:08:47 2021">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="22cd7da0d8814ac4ba10473639199647" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="21" type="ProjectIteration"/>
|
||||
<property name="ProjectIteration" value="22" type="ProjectIteration"/>
|
||||
</section>
|
||||
<section name="PlanAhead Usage" visible="true">
|
||||
<item name="Project Data">
|
||||
@ -18,38 +18,38 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddCfgMem" value="2" type="JavaHandler"/>
|
||||
<property name="AutoConnectTarget" value="10" type="JavaHandler"/>
|
||||
<property name="CustomizeRSBBlock" value="30" type="JavaHandler"/>
|
||||
<property name="AutoConnectTarget" value="11" type="JavaHandler"/>
|
||||
<property name="CustomizeRSBBlock" value="31" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="6" type="JavaHandler"/>
|
||||
<property name="EditProperties" value="1" type="JavaHandler"/>
|
||||
<property name="FileExit" value="6" type="JavaHandler"/>
|
||||
<property name="OpenHardwareManager" value="11" type="JavaHandler"/>
|
||||
<property name="FileExit" value="7" type="JavaHandler"/>
|
||||
<property name="OpenHardwareManager" value="12" type="JavaHandler"/>
|
||||
<property name="OpenProject" value="2" type="JavaHandler"/>
|
||||
<property name="ProgramCfgMem" value="11" type="JavaHandler"/>
|
||||
<property name="ProgramCfgMem" value="12" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="2" type="JavaHandler"/>
|
||||
<property name="RegenerateRSBLayout" value="3" type="JavaHandler"/>
|
||||
<property name="RunBitgen" value="21" type="JavaHandler"/>
|
||||
<property name="RunBitgen" value="22" type="JavaHandler"/>
|
||||
<property name="RunImplementation" value="1" type="JavaHandler"/>
|
||||
<property name="RunSynthesis" value="3" type="JavaHandler"/>
|
||||
<property name="SaveProjectAs" value="14" type="JavaHandler"/>
|
||||
<property name="SaveRSBDesign" value="2" type="JavaHandler"/>
|
||||
<property name="ToolsSettings" value="2" type="JavaHandler"/>
|
||||
<property name="ValidateRSBDesign" value="4" type="JavaHandler"/>
|
||||
<property name="ViewTaskProjectManager" value="11" type="JavaHandler"/>
|
||||
<property name="ViewTaskProjectManager" value="12" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="BaseDialog_CANCEL" value="3" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="56" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="58" type="GuiHandlerData"/>
|
||||
<property name="CfgMemPartChooser_TABLE" value="2" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_MESSAGES" value="1" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_OK" value="22" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_MESSAGES" value="2" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_OK" value="25" type="GuiHandlerData"/>
|
||||
<property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="2" type="GuiHandlerData"/>
|
||||
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="2" type="GuiHandlerData"/>
|
||||
<property name="DesignTimingSumSectionPanel_WORST_NEGATIVE_SLACK" value="2" type="GuiHandlerData"/>
|
||||
<property name="ExpRunMenu_RESET_AND_GENERATE_OUTPUT_PRODUCTS" value="1" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="91" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="67" type="GuiHandlerData"/>
|
||||
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="55" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="92" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="72" type="GuiHandlerData"/>
|
||||
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="57" type="GuiHandlerData"/>
|
||||
<property name="HACGCTextField_VALUE_OF_SPECIFIED_PARAMETER" value="3" type="GuiHandlerData"/>
|
||||
<property name="HACGCTextField_VALUE_OF_SPECIFIED_PARAMETER_MANUAL" value="1" type="GuiHandlerData"/>
|
||||
<property name="HCodeEditor_CLOSE" value="1" type="GuiHandlerData"/>
|
||||
@ -57,17 +57,17 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="HFolderChooserHelpers_UP_ONE_LEVEL" value="4" type="GuiHandlerData"/>
|
||||
<property name="HInputHandler_TOGGLE_BLOCK_COMMENTS" value="1" type="GuiHandlerData"/>
|
||||
<property name="HJFileChooserRecentListPreview_RECENT_DIRECTORIES" value="1" type="GuiHandlerData"/>
|
||||
<property name="HardwareTreePanel_HARDWARE_TREE_TABLE" value="18" type="GuiHandlerData"/>
|
||||
<property name="HardwareTreePanel_HARDWARE_TREE_TABLE" value="19" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_CHECKPOINT" value="7" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_EXPORT" value="1" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FILE" value="52" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FILE" value="54" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_IP" value="4" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="22" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_PROJECT" value="38" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="23" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_PROJECT" value="40" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_TEXT_EDITOR" value="1" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_TOOLS" value="2" type="GuiHandlerData"/>
|
||||
<property name="MigLicensePage_ACCEPT" value="2" type="GuiHandlerData"/>
|
||||
<property name="MigPinSelectionPage_VALIDATE" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_TOOLS" value="4" type="GuiHandlerData"/>
|
||||
<property name="MigLicensePage_ACCEPT" value="3" type="GuiHandlerData"/>
|
||||
<property name="MigPinSelectionPage_VALIDATE" value="3" type="GuiHandlerData"/>
|
||||
<property name="MsgTreePanel_DISCARD_USER_CREATED_MESSAGES" value="2" type="GuiHandlerData"/>
|
||||
<property name="MsgTreePanel_MESSAGE_SEVERITY" value="3" type="GuiHandlerData"/>
|
||||
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="7" type="GuiHandlerData"/>
|
||||
@ -76,35 +76,35 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="MsgView_WARNING_MESSAGES" value="1" type="GuiHandlerData"/>
|
||||
<property name="NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_CONFIG_MEMORY" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="10" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="11" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_BOOT_DEVICE" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_IMPL_SETTINGS" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_HARDWARE_MANAGER" value="5" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_HARDWARE_MANAGER" value="6" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_PROJECT" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_PROGRAM_CONFIG_MEMORY" value="9" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_PROGRAM_CONFIG_MEMORY" value="10" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_REGENERATE_LAYOUT" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SAVE_PROJECT_AS" value="14" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SAVE_RSB_DESIGN" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_VALIDATE_RSB_DESIGN" value="4" type="GuiHandlerData"/>
|
||||
<property name="PAViews_CODE" value="2" type="GuiHandlerData"/>
|
||||
<property name="PAViews_PROJECT_SUMMARY" value="19" type="GuiHandlerData"/>
|
||||
<property name="PAViews_PROJECT_SUMMARY" value="20" type="GuiHandlerData"/>
|
||||
<property name="PAViews_SYSTEM" value="2" type="GuiHandlerData"/>
|
||||
<property name="PathMenu_SET_FALSE_PATH" value="5" type="GuiHandlerData"/>
|
||||
<property name="PathMenu_SET_MAXIMUM_DELAY" value="2" type="GuiHandlerData"/>
|
||||
<property name="PathMenu_SET_MULTICYCLE_PATH" value="5" type="GuiHandlerData"/>
|
||||
<property name="ProgramCfgMemDialog_CONTENTS_OF_CONFIGURATION_FILE" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProgramDebugTab_OPEN_TARGET" value="11" type="GuiHandlerData"/>
|
||||
<property name="ProgramDebugTab_OPEN_TARGET" value="12" type="GuiHandlerData"/>
|
||||
<property name="ProgramOptionsPanelImpl_STRATEGY" value="26" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_CANCEL" value="3" type="GuiHandlerData"/>
|
||||
<property name="ProjectNameChooser_CHOOSE_PROJECT_LOCATION" value="14" type="GuiHandlerData"/>
|
||||
<property name="ProjectNameChooser_PROJECT_NAME" value="15" type="GuiHandlerData"/>
|
||||
<property name="ProjectSummaryTimingPanel_PROJECT_SUMMARY_TIMING_PANEL_TABBED" value="6" type="GuiHandlerData"/>
|
||||
<property name="ProjectSummaryUtilizationPanel_PROJECT_SUMMARY_UTILIZATION_PANEL_TABBED" value="4" type="GuiHandlerData"/>
|
||||
<property name="ProjectSummaryUtilizationPanel_PROJECT_SUMMARY_UTILIZATION_PANEL_TABBED" value="5" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_PROPERTIES" value="1" type="GuiHandlerData"/>
|
||||
<property name="RunGadget_RUN_GADGET_TABBED_PANE" value="5" type="GuiHandlerData"/>
|
||||
<property name="RunGadget_TABLE" value="1" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_SAVE" value="14" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_SAVE" value="15" type="GuiHandlerData"/>
|
||||
<property name="SelectMenu_HIGHLIGHT" value="2" type="GuiHandlerData"/>
|
||||
<property name="SelectMenu_MARK" value="3" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="1" type="GuiHandlerData"/>
|
||||
@ -118,9 +118,9 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="TimingItemFlatTablePanel_TABLE" value="9" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="64" type="GuiMode"/>
|
||||
<property name="GuiMode" value="70" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="56" type="TclMode"/>
|
||||
<property name="TclMode" value="62" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
@ -0,0 +1,16 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="design_1_mig_7series_0_0_synth_1" LaunchDir="C:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.runs/design_1_mig_7series_0_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Run Id="synth_1" LaunchDir="C:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado">
|
||||
<Parent Id="design_1_mig_7series_0_0_synth_1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" LaunchDir="C:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
|
||||
<Parent Id="synth_1"/>
|
||||
<Parent Id="design_1_mig_7series_0_0_synth_1"/>
|
||||
</Run>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado.bat" Owner="Aleksa" Host="DESKTOP-J72MK93" Pid="6732" HostCore="16" HostMemory="034270351360">
|
||||
<Process Command="vivado.bat" Owner="Aleksa" Host="DESKTOP-J72MK93" Pid="9732" HostCore="16" HostMemory="034270351360">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
||||
Binary file not shown.
@ -2,8 +2,8 @@
|
||||
# Vivado v2020.1 (64-bit)
|
||||
# SW Build 2902540 on Wed May 27 19:54:49 MDT 2020
|
||||
# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
|
||||
# Start of session at: Tue May 18 14:05:23 2021
|
||||
# Process ID: 3096
|
||||
# Start of session at: Wed May 19 10:52:45 2021
|
||||
# Process ID: 4108
|
||||
# Current directory: C:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.runs/design_1_mig_7series_0_0_synth_1
|
||||
# Command line: vivado.exe -log design_1_mig_7series_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_mig_7series_0_0.tcl
|
||||
# Log file: C:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.runs/design_1_mig_7series_0_0_synth_1/design_1_mig_7series_0_0.vds
|
||||
@ -17,9 +17,9 @@ INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100
|
||||
INFO: [Device 21-403] Loading part xc7a100tfgg484-2
|
||||
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
|
||||
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 12052
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 11080
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1015.949 ; gain = 0.000
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1015.938 ; gain = 0.000
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'design_1_mig_7series_0_0' [c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/design_1_mig_7series_0_0.v:70]
|
||||
INFO: [Synth 8-6157] synthesizing module 'design_1_mig_7series_0_0_mig' [c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/design_1_mig_7series_0_0_mig.v:75]
|
||||
@ -148,7 +148,7 @@ INFO: [Synth 8-6157] synthesizing module 'design_1_mig_7series_0_0_mig' [c:/User
|
||||
Parameter CKE_ODT_AUX bound to: FALSE - type: string
|
||||
Parameter USER_REFRESH bound to: OFF - type: string
|
||||
Parameter WRLVL bound to: ON - type: string
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter CALIB_ROW_ADD bound to: 16'b0000000000000000
|
||||
Parameter CALIB_COL_ADD bound to: 12'b000000000000
|
||||
Parameter CALIB_BA_ADD bound to: 3'b000
|
||||
@ -442,7 +442,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_memc_ui_top_axi' [c:/
|
||||
Parameter nBANK_MACHS bound to: 3 - type: integer
|
||||
Parameter nCK_PER_CLK bound to: 4 - type: integer
|
||||
Parameter nCS_PER_RANK bound to: 1 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter IBUF_LPWR_MODE bound to: OFF - type: string
|
||||
Parameter BANK_TYPE bound to: HR_IO - type: string
|
||||
Parameter DATA_IO_PRIM_TYPE bound to: HR_LP - type: string
|
||||
@ -648,7 +648,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mem_intfc' [c:/Users/
|
||||
Parameter nCK_PER_CLK bound to: 4 - type: integer
|
||||
Parameter nCS_PER_RANK bound to: 1 - type: integer
|
||||
Parameter PHYCTL_CMD_FIFO bound to: FALSE - type: string
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter PHASE_DETECT bound to: OFF - type: string
|
||||
Parameter IBUF_LPWR_MODE bound to: OFF - type: string
|
||||
Parameter BANK_TYPE bound to: HR_IO - type: string
|
||||
@ -741,7 +741,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mc' [c:/Users/Aleksa/
|
||||
Parameter nCS_PER_RANK bound to: 1 - type: integer
|
||||
Parameter nREFRESH_BANK bound to: 1 - type: integer
|
||||
Parameter nSLOTS bound to: 1 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter PAYLOAD_WIDTH bound to: 32 - type: integer
|
||||
Parameter RANK_WIDTH bound to: 1 - type: integer
|
||||
Parameter RANKS bound to: 1 - type: integer
|
||||
@ -919,7 +919,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_mach' [c:/Users/
|
||||
Parameter nSLOTS bound to: 1 - type: integer
|
||||
Parameter nWR bound to: 6 - type: integer
|
||||
Parameter nXSDLL bound to: 512 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter RANK_BM_BV_WIDTH bound to: 3 - type: integer
|
||||
Parameter RANK_WIDTH bound to: 1 - type: integer
|
||||
Parameter RANKS bound to: 1 - type: integer
|
||||
@ -958,7 +958,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl' [c:/Users
|
||||
Parameter nRTP bound to: 4 - type: integer
|
||||
Parameter nRP bound to: 6 - type: integer
|
||||
Parameter nWTP_CLKS bound to: 5 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter RANK_WIDTH bound to: 1 - type: integer
|
||||
Parameter RANKS bound to: 1 - type: integer
|
||||
Parameter RAS_TIMER_WIDTH bound to: 2 - type: integer
|
||||
@ -994,7 +994,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state' [c:/Users
|
||||
Parameter nRTP bound to: 4 - type: integer
|
||||
Parameter nRCD bound to: 6 - type: integer
|
||||
Parameter nWTP_CLKS bound to: 5 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter RANKS bound to: 1 - type: integer
|
||||
Parameter RANK_WIDTH bound to: 1 - type: integer
|
||||
Parameter RAS_TIMER_WIDTH bound to: 2 - type: integer
|
||||
@ -1019,7 +1019,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue' [c:/Users
|
||||
Parameter TCQ bound to: 100 - type: integer
|
||||
Parameter BM_CNT_WIDTH bound to: 2 - type: integer
|
||||
Parameter nBANK_MACHS bound to: 3 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter ID bound to: 0 - type: integer
|
||||
Parameter ZERO bound to: 0 - type: integer
|
||||
Parameter ONE bound to: 1 - type: integer
|
||||
@ -1047,7 +1047,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameter
|
||||
Parameter nRTP bound to: 4 - type: integer
|
||||
Parameter nRP bound to: 6 - type: integer
|
||||
Parameter nWTP_CLKS bound to: 5 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter RANK_WIDTH bound to: 1 - type: integer
|
||||
Parameter RANKS bound to: 1 - type: integer
|
||||
Parameter RAS_TIMER_WIDTH bound to: 2 - type: integer
|
||||
@ -1071,7 +1071,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameter
|
||||
Parameter nRTP bound to: 4 - type: integer
|
||||
Parameter nRCD bound to: 6 - type: integer
|
||||
Parameter nWTP_CLKS bound to: 5 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter RANKS bound to: 1 - type: integer
|
||||
Parameter RANK_WIDTH bound to: 1 - type: integer
|
||||
Parameter RAS_TIMER_WIDTH bound to: 2 - type: integer
|
||||
@ -1096,7 +1096,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameter
|
||||
Parameter TCQ bound to: 100 - type: integer
|
||||
Parameter BM_CNT_WIDTH bound to: 2 - type: integer
|
||||
Parameter nBANK_MACHS bound to: 3 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter ID bound to: 1 - type: integer
|
||||
Parameter ZERO bound to: 0 - type: integer
|
||||
Parameter ONE bound to: 1 - type: integer
|
||||
@ -1124,7 +1124,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameter
|
||||
Parameter nRTP bound to: 4 - type: integer
|
||||
Parameter nRP bound to: 6 - type: integer
|
||||
Parameter nWTP_CLKS bound to: 5 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter RANK_WIDTH bound to: 1 - type: integer
|
||||
Parameter RANKS bound to: 1 - type: integer
|
||||
Parameter RAS_TIMER_WIDTH bound to: 2 - type: integer
|
||||
@ -1148,7 +1148,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameter
|
||||
Parameter nRTP bound to: 4 - type: integer
|
||||
Parameter nRCD bound to: 6 - type: integer
|
||||
Parameter nWTP_CLKS bound to: 5 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter RANKS bound to: 1 - type: integer
|
||||
Parameter RANK_WIDTH bound to: 1 - type: integer
|
||||
Parameter RAS_TIMER_WIDTH bound to: 2 - type: integer
|
||||
@ -1173,7 +1173,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameter
|
||||
Parameter TCQ bound to: 100 - type: integer
|
||||
Parameter BM_CNT_WIDTH bound to: 2 - type: integer
|
||||
Parameter nBANK_MACHS bound to: 3 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter ID bound to: 2 - type: integer
|
||||
Parameter ZERO bound to: 0 - type: integer
|
||||
Parameter ONE bound to: 1 - type: integer
|
||||
@ -4046,7 +4046,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_top' [c:/Users/Ale
|
||||
Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer
|
||||
Parameter ECC bound to: OFF - type: string
|
||||
Parameter ECC_TEST bound to: OFF - type: string
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter nCK_PER_CLK bound to: 4 - type: integer
|
||||
Parameter RANKS bound to: 1 - type: integer
|
||||
Parameter REG_CTRL bound to: ON - type: string
|
||||
@ -4090,18 +4090,12 @@ INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instan
|
||||
Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer
|
||||
Parameter ECC bound to: OFF - type: string
|
||||
Parameter nCK_PER_CLK bound to: 4 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter RD_BUF_WIDTH bound to: 256 - type: integer
|
||||
Parameter FULL_RAM_CNT bound to: 42 - type: integer
|
||||
Parameter REMAINDER bound to: 4 - type: integer
|
||||
Parameter RAM_CNT bound to: 43 - type: integer
|
||||
Parameter RAM_WIDTH bound to: 258 - type: integer
|
||||
INFO: [Synth 8-155] case statement is not full and has no default [c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:406]
|
||||
WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_cnt_r' should be on the sensitivity list [c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403]
|
||||
WARNING: [Synth 8-567] referenced signal 'not_strict_mode.free_rd_buf' should be on the sensitivity list [c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403]
|
||||
WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_minus_one' should be on the sensitivity list [c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403]
|
||||
WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_plus_one' should be on the sensitivity list [c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403]
|
||||
WARNING: [Synth 8-567] referenced signal 'not_strict_mode.rd_data_buf_addr_r_lcl' should be on the sensitivity list [c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:432]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_rd_data' (67#1) [c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:140]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_top' (68#1) [c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_top.v:71]
|
||||
Parameter C_FAMILY bound to: virtex7 - type: string
|
||||
@ -4374,19 +4368,19 @@ INFO: [Synth 8-155] case statement is not full and has no default [c:/Users/Alek
|
||||
Parameter C_AXI_STARVE_CNT_WIDTH bound to: 8 - type: integer
|
||||
Parameter C_RD_WR_ARB_ALGORITHM bound to: RD_PRI_REG_STARVE_LIMIT - type: string
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1210.234 ; gain = 194.285
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1207.121 ; gain = 191.184
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1210.234 ; gain = 194.285
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1207.121 ; gain = 191.184
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1210.234 ; gain = 194.285
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1207.121 ; gain = 191.184
|
||||
---------------------------------------------------------------------------------
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.696 . Memory (MB): peak = 1210.234 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 213 Unisim elements for replacement
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.643 . Memory (MB): peak = 1207.121 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 169 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
@ -4403,24 +4397,24 @@ Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_mig
|
||||
INFO: [Timing 38-2] Deriving generated clocks
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1335.184 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1332.695 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 133 instances were transformed.
|
||||
A total of 89 instances were transformed.
|
||||
IOBUFDS_DIFF_OUT_INTERMDISABLE => IOBUFDS_DIFF_OUT_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 4 instances
|
||||
IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 32 instances
|
||||
OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance
|
||||
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 96 instances
|
||||
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 52 instances
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.353 . Memory (MB): peak = 1335.309 ; gain = 0.125
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.292 . Memory (MB): peak = 1332.918 ; gain = 0.223
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 1335.309 ; gain = 319.359
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 1332.918 ; gain = 316.980
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7a100tfgg484-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 1335.309 ; gain = 319.359
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 1332.918 ; gain = 316.980
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
@ -4428,7 +4422,7 @@ Start Applying 'set_property' XDC Constraints
|
||||
Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_n[0]. (constraint file c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/constraints/design_1_mig_7series_0_0.xdc, line 27).
|
||||
Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_p[0]. (constraint file c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/constraints/design_1_mig_7series_0_0.xdc, line 28).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 1335.309 ; gain = 319.359
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 1332.918 ; gain = 316.980
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-802] inferred FSM for state register 'xadc_supplied_temperature.tempmon_state_reg' in module 'mig_7series_v4_2_tempmon'
|
||||
INFO: [Synth 8-802] inferred FSM for state register 'wl_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_wrlvl'
|
||||
@ -4554,7 +4548,7 @@ INFO: [Synth 8-3898] No Re-encoding of one hot register 'tempmon_state_reg' in m
|
||||
---------------------------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'mig_7series_v4_2_axi_mc_r_channel'
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:46 ; elapsed = 00:00:49 . Memory (MB): peak = 1335.309 ; gain = 319.359
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 1332.918 ; gain = 316.980
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
@ -4571,7 +4565,7 @@ Detailed RTL Component Info :
|
||||
2 Input 9 Bit Adders := 5
|
||||
2 Input 8 Bit Adders := 11
|
||||
2 Input 7 Bit Adders := 6
|
||||
2 Input 6 Bit Adders := 50
|
||||
2 Input 6 Bit Adders := 49
|
||||
3 Input 6 Bit Adders := 22
|
||||
4 Input 6 Bit Adders := 1
|
||||
2 Input 5 Bit Adders := 47
|
||||
@ -4594,7 +4588,7 @@ Detailed RTL Component Info :
|
||||
2 Input 1 Bit XORs := 1
|
||||
+---Registers :
|
||||
288 Bit Registers := 1
|
||||
256 Bit Registers := 5
|
||||
256 Bit Registers := 4
|
||||
160 Bit Registers := 1
|
||||
88 Bit Registers := 1
|
||||
80 Bit Registers := 4
|
||||
@ -4612,14 +4606,14 @@ Detailed RTL Component Info :
|
||||
9 Bit Registers := 18
|
||||
8 Bit Registers := 30
|
||||
7 Bit Registers := 3
|
||||
6 Bit Registers := 125
|
||||
5 Bit Registers := 57
|
||||
6 Bit Registers := 124
|
||||
5 Bit Registers := 55
|
||||
4 Bit Registers := 89
|
||||
3 Bit Registers := 76
|
||||
2 Bit Registers := 63
|
||||
1 Bit Registers := 1896
|
||||
2 Bit Registers := 62
|
||||
1 Bit Registers := 1891
|
||||
+---Muxes :
|
||||
2 Input 256 Bit Muxes := 11
|
||||
2 Input 256 Bit Muxes := 10
|
||||
4 Input 256 Bit Muxes := 1
|
||||
2 Input 255 Bit Muxes := 1
|
||||
2 Input 80 Bit Muxes := 12
|
||||
@ -4651,15 +4645,15 @@ Detailed RTL Component Info :
|
||||
3 Input 7 Bit Muxes := 2
|
||||
4 Input 7 Bit Muxes := 1
|
||||
5 Input 7 Bit Muxes := 2
|
||||
2 Input 6 Bit Muxes := 131
|
||||
2 Input 6 Bit Muxes := 126
|
||||
4 Input 6 Bit Muxes := 19
|
||||
27 Input 6 Bit Muxes := 6
|
||||
5 Input 6 Bit Muxes := 2
|
||||
16 Input 6 Bit Muxes := 1
|
||||
24 Input 6 Bit Muxes := 5
|
||||
23 Input 6 Bit Muxes := 6
|
||||
3 Input 6 Bit Muxes := 3
|
||||
2 Input 5 Bit Muxes := 39
|
||||
3 Input 6 Bit Muxes := 1
|
||||
2 Input 5 Bit Muxes := 38
|
||||
8 Input 5 Bit Muxes := 4
|
||||
27 Input 5 Bit Muxes := 1
|
||||
58 Input 5 Bit Muxes := 1
|
||||
@ -4679,14 +4673,14 @@ Detailed RTL Component Info :
|
||||
8 Input 3 Bit Muxes := 2
|
||||
9 Input 3 Bit Muxes := 1
|
||||
10 Input 3 Bit Muxes := 1
|
||||
2 Input 2 Bit Muxes := 91
|
||||
3 Input 2 Bit Muxes := 7
|
||||
2 Input 2 Bit Muxes := 90
|
||||
3 Input 2 Bit Muxes := 6
|
||||
8 Input 2 Bit Muxes := 8
|
||||
24 Input 2 Bit Muxes := 1
|
||||
23 Input 2 Bit Muxes := 3
|
||||
4 Input 2 Bit Muxes := 3
|
||||
5 Input 2 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 774
|
||||
2 Input 1 Bit Muxes := 772
|
||||
3 Input 1 Bit Muxes := 31
|
||||
4 Input 1 Bit Muxes := 150
|
||||
8 Input 1 Bit Muxes := 8
|
||||
@ -4713,7 +4707,7 @@ Finished Part Resource Summary
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:53 ; elapsed = 00:01:58 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:52 ; elapsed = 00:01:56 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP and Shift Register Reporting
|
||||
@ -4755,13 +4749,13 @@ Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-3321] set_false_path : Empty through list for constraint at line 509 of c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/constraints/design_1_mig_7series_0_0.xdc. [c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/constraints/design_1_mig_7series_0_0.xdc:509]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:59 ; elapsed = 00:02:05 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:58 ; elapsed = 00:02:03 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:02:02 ; elapsed = 00:02:07 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Finished Timing Optimization : Time (s): cpu = 00:02:01 ; elapsed = 00:02:05 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP and Shift Register Reporting
|
||||
@ -4792,7 +4786,7 @@ Finished ROM, RAM, DSP and Shift Register Reporting
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:02:07 ; elapsed = 00:02:13 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Finished Technology Mapping : Time (s): cpu = 00:02:06 ; elapsed = 00:02:11 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
@ -4810,37 +4804,37 @@ Start Final Netlist Cleanup
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:02:11 ; elapsed = 00:02:16 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Finished IO Insertion : Time (s): cpu = 00:02:09 ; elapsed = 00:02:14 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:02:11 ; elapsed = 00:02:16 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:02:09 ; elapsed = 00:02:14 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:13 ; elapsed = 00:02:18 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:11 ; elapsed = 00:02:16 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:02:13 ; elapsed = 00:02:18 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:02:11 ; elapsed = 00:02:16 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:02:13 ; elapsed = 00:02:18 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:02:12 ; elapsed = 00:02:16 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:02:13 ; elapsed = 00:02:19 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:02:12 ; elapsed = 00:02:16 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP and Shift Register Reporting
|
||||
@ -4902,12 +4896,12 @@ Report Cell Usage:
|
||||
|7 |IDELAYE2 | 32|
|
||||
|8 |IN_FIFO | 4|
|
||||
|9 |ISERDESE2 | 32|
|
||||
|10 |LUT1 | 458|
|
||||
|11 |LUT2 | 661|
|
||||
|12 |LUT3 | 2175|
|
||||
|13 |LUT4 | 1188|
|
||||
|14 |LUT5 | 1520|
|
||||
|15 |LUT6 | 1177|
|
||||
|10 |LUT1 | 451|
|
||||
|11 |LUT2 | 641|
|
||||
|12 |LUT3 | 1932|
|
||||
|13 |LUT4 | 1168|
|
||||
|14 |LUT5 | 1531|
|
||||
|15 |LUT6 | 1169|
|
||||
|16 |MMCME2_ADV | 1|
|
||||
|17 |MUXF7 | 2|
|
||||
|18 |ODDR | 9|
|
||||
@ -4918,14 +4912,14 @@ Report Cell Usage:
|
||||
|27 |PHASER_REF | 2|
|
||||
|28 |PHY_CONTROL | 2|
|
||||
|29 |PLLE2_ADV | 1|
|
||||
|30 |RAM32M | 222|
|
||||
|30 |RAM32M | 177|
|
||||
|31 |SRL16E | 18|
|
||||
|32 |SRLC32E | 259|
|
||||
|33 |XADC | 1|
|
||||
|34 |FDCE | 3|
|
||||
|35 |FDPE | 76|
|
||||
|36 |FDRE | 5525|
|
||||
|37 |FDSE | 260|
|
||||
|36 |FDRE | 5234|
|
||||
|37 |FDSE | 259|
|
||||
|38 |IOBUFDS_DIFF_OUT_INTERMDISABLE | 4|
|
||||
|39 |IOBUF_INTERMDISABLE | 32|
|
||||
|40 |OBUF | 25|
|
||||
@ -4933,37 +4927,37 @@ Report Cell Usage:
|
||||
|42 |OBUFT | 4|
|
||||
+------+-------------------------------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:02:13 ; elapsed = 00:02:19 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:02:12 ; elapsed = 00:02:16 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:01:46 ; elapsed = 00:02:09 . Memory (MB): peak = 1397.359 ; gain = 256.336
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:02:13 ; elapsed = 00:02:19 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:01:47 ; elapsed = 00:02:07 . Memory (MB): peak = 1396.910 ; gain = 255.176
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:02:12 ; elapsed = 00:02:16 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.554 . Memory (MB): peak = 1397.359 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 468 Unisim elements for replacement
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.463 . Memory (MB): peak = 1396.910 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 423 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 4 inverter(s) to 32 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1397.359 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1396.910 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 259 instances were transformed.
|
||||
A total of 214 instances were transformed.
|
||||
IOBUFDS_DIFF_OUT_INTERMDISABLE => IOBUFDS_DIFF_OUT_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 4 instances
|
||||
IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 32 instances
|
||||
OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance
|
||||
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 222 instances
|
||||
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 177 instances
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
245 Infos, 34 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
244 Infos, 29 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:02:22 ; elapsed = 00:02:28 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
synth_design: Time (s): cpu = 00:02:20 ; elapsed = 00:02:25 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.runs/design_1_mig_7series_0_0_synth_1/design_1_mig_7series_0_0.dcp' has been generated.
|
||||
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP design_1_mig_7series_0_0, cache-ID = de240defa7bad4ca
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP design_1_mig_7series_0_0, cache-ID = 8abae3f1fc384d9a
|
||||
INFO: [Coretcl 2-1174] Renamed 106 cell refs.
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.runs/design_1_mig_7series_0_0_synth_1/design_1_mig_7series_0_0.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file design_1_mig_7series_0_0_utilization_synth.rpt -pb design_1_mig_7series_0_0_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue May 18 14:08:07 2021...
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed May 19 10:55:24 2021...
|
||||
|
||||
Binary file not shown.
@ -1,7 +1,7 @@
|
||||
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
|
||||
| Date : Tue May 18 14:08:03 2021
|
||||
| Date : Wed May 19 10:55:21 2021
|
||||
| Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file design_1_mig_7series_0_0_utilization_synth.rpt -pb design_1_mig_7series_0_0_utilization_synth.pb
|
||||
| Design : design_1_mig_7series_0_0
|
||||
@ -30,13 +30,13 @@ Table of Contents
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 6829 | 0 | 63400 | 10.77 |
|
||||
| LUT as Logic | 5664 | 0 | 63400 | 8.93 |
|
||||
| LUT as Memory | 1165 | 0 | 19000 | 6.13 |
|
||||
| LUT as Distributed RAM | 888 | 0 | | |
|
||||
| Slice LUTs* | 6349 | 0 | 63400 | 10.01 |
|
||||
| LUT as Logic | 5364 | 0 | 63400 | 8.46 |
|
||||
| LUT as Memory | 985 | 0 | 19000 | 5.18 |
|
||||
| LUT as Distributed RAM | 708 | 0 | | |
|
||||
| LUT as Shift Register | 277 | 0 | | |
|
||||
| Slice Registers | 5864 | 0 | 126800 | 4.62 |
|
||||
| Register as Flip Flop | 5864 | 0 | 126800 | 4.62 |
|
||||
| Slice Registers | 5572 | 0 | 126800 | 4.39 |
|
||||
| Register as Flip Flop | 5572 | 0 | 126800 | 4.39 |
|
||||
| Register as Latch | 0 | 0 | 126800 | 0.00 |
|
||||
| F7 Muxes | 2 | 0 | 31700 | <0.01 |
|
||||
| F8 Muxes | 0 | 0 | 15850 | 0.00 |
|
||||
@ -58,8 +58,8 @@ Table of Contents
|
||||
| 0 | Yes | - | - |
|
||||
| 76 | Yes | - | Set |
|
||||
| 3 | Yes | - | Reset |
|
||||
| 260 | Yes | Set | - |
|
||||
| 5525 | Yes | Reset | - |
|
||||
| 259 | Yes | Set | - |
|
||||
| 5234 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
@ -158,17 +158,17 @@ Table of Contents
|
||||
+--------------------------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+--------------------------+------+---------------------+
|
||||
| FDRE | 5525 | Flop & Latch |
|
||||
| LUT3 | 2175 | LUT |
|
||||
| LUT5 | 1520 | LUT |
|
||||
| RAMD32 | 1332 | Distributed Memory |
|
||||
| LUT4 | 1188 | LUT |
|
||||
| LUT6 | 1177 | LUT |
|
||||
| LUT2 | 661 | LUT |
|
||||
| LUT1 | 454 | LUT |
|
||||
| RAMS32 | 444 | Distributed Memory |
|
||||
| FDSE | 260 | Flop & Latch |
|
||||
| FDRE | 5234 | Flop & Latch |
|
||||
| LUT3 | 1932 | LUT |
|
||||
| LUT5 | 1531 | LUT |
|
||||
| LUT6 | 1169 | LUT |
|
||||
| LUT4 | 1168 | LUT |
|
||||
| RAMD32 | 1062 | Distributed Memory |
|
||||
| LUT2 | 641 | LUT |
|
||||
| LUT1 | 447 | LUT |
|
||||
| RAMS32 | 354 | Distributed Memory |
|
||||
| SRLC32E | 259 | Distributed Memory |
|
||||
| FDSE | 259 | Flop & Latch |
|
||||
| CARRY4 | 127 | CarryLogic |
|
||||
| FDPE | 76 | Flop & Latch |
|
||||
| OSERDESE2 | 64 | IO |
|
||||
|
||||
@ -1,11 +1,14 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="design_1_mig_7series_0_0_synth_1" LaunchPart="xc7a100tfgg484-2" LaunchTime="1621361120">
|
||||
<GenRun Id="design_1_mig_7series_0_0_synth_1" LaunchPart="xc7a100tfgg484-2" LaunchTime="1621435963">
|
||||
<File Type="PA-TCL" Name="design_1_mig_7series_0_0.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="design_1_mig_7series_0_0_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="design_1_mig_7series_0_0_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="design_1_mig_7series_0_0.vds"/>
|
||||
<File Type="RDS-UTIL" Name="design_1_mig_7series_0_0_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="design_1_mig_7series_0_0_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="design_1_mig_7series_0_0.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="design_1_mig_7series_0_0_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="design_1_mig_7series_0_0_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_mig_7series_0_0">
|
||||
<File Path="$PSRCDIR/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xci">
|
||||
<FileInfo>
|
||||
|
||||
@ -17,9 +17,9 @@ INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100
|
||||
INFO: [Device 21-403] Loading part xc7a100tfgg484-2
|
||||
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
|
||||
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 12052
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 11080
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1015.949 ; gain = 0.000
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1015.938 ; gain = 0.000
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'design_1_mig_7series_0_0' [c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/design_1_mig_7series_0_0.v:70]
|
||||
INFO: [Synth 8-6157] synthesizing module 'design_1_mig_7series_0_0_mig' [c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/design_1_mig_7series_0_0_mig.v:75]
|
||||
@ -148,7 +148,7 @@ INFO: [Synth 8-6157] synthesizing module 'design_1_mig_7series_0_0_mig' [c:/User
|
||||
Parameter CKE_ODT_AUX bound to: FALSE - type: string
|
||||
Parameter USER_REFRESH bound to: OFF - type: string
|
||||
Parameter WRLVL bound to: ON - type: string
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter CALIB_ROW_ADD bound to: 16'b0000000000000000
|
||||
Parameter CALIB_COL_ADD bound to: 12'b000000000000
|
||||
Parameter CALIB_BA_ADD bound to: 3'b000
|
||||
@ -442,7 +442,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_memc_ui_top_axi' [c:/
|
||||
Parameter nBANK_MACHS bound to: 3 - type: integer
|
||||
Parameter nCK_PER_CLK bound to: 4 - type: integer
|
||||
Parameter nCS_PER_RANK bound to: 1 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter IBUF_LPWR_MODE bound to: OFF - type: string
|
||||
Parameter BANK_TYPE bound to: HR_IO - type: string
|
||||
Parameter DATA_IO_PRIM_TYPE bound to: HR_LP - type: string
|
||||
@ -648,7 +648,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mem_intfc' [c:/Users/
|
||||
Parameter nCK_PER_CLK bound to: 4 - type: integer
|
||||
Parameter nCS_PER_RANK bound to: 1 - type: integer
|
||||
Parameter PHYCTL_CMD_FIFO bound to: FALSE - type: string
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter PHASE_DETECT bound to: OFF - type: string
|
||||
Parameter IBUF_LPWR_MODE bound to: OFF - type: string
|
||||
Parameter BANK_TYPE bound to: HR_IO - type: string
|
||||
@ -741,7 +741,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mc' [c:/Users/Aleksa/
|
||||
Parameter nCS_PER_RANK bound to: 1 - type: integer
|
||||
Parameter nREFRESH_BANK bound to: 1 - type: integer
|
||||
Parameter nSLOTS bound to: 1 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter PAYLOAD_WIDTH bound to: 32 - type: integer
|
||||
Parameter RANK_WIDTH bound to: 1 - type: integer
|
||||
Parameter RANKS bound to: 1 - type: integer
|
||||
@ -919,7 +919,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_mach' [c:/Users/
|
||||
Parameter nSLOTS bound to: 1 - type: integer
|
||||
Parameter nWR bound to: 6 - type: integer
|
||||
Parameter nXSDLL bound to: 512 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter RANK_BM_BV_WIDTH bound to: 3 - type: integer
|
||||
Parameter RANK_WIDTH bound to: 1 - type: integer
|
||||
Parameter RANKS bound to: 1 - type: integer
|
||||
@ -958,7 +958,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl' [c:/Users
|
||||
Parameter nRTP bound to: 4 - type: integer
|
||||
Parameter nRP bound to: 6 - type: integer
|
||||
Parameter nWTP_CLKS bound to: 5 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter RANK_WIDTH bound to: 1 - type: integer
|
||||
Parameter RANKS bound to: 1 - type: integer
|
||||
Parameter RAS_TIMER_WIDTH bound to: 2 - type: integer
|
||||
@ -994,7 +994,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state' [c:/Users
|
||||
Parameter nRTP bound to: 4 - type: integer
|
||||
Parameter nRCD bound to: 6 - type: integer
|
||||
Parameter nWTP_CLKS bound to: 5 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter RANKS bound to: 1 - type: integer
|
||||
Parameter RANK_WIDTH bound to: 1 - type: integer
|
||||
Parameter RAS_TIMER_WIDTH bound to: 2 - type: integer
|
||||
@ -1019,7 +1019,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue' [c:/Users
|
||||
Parameter TCQ bound to: 100 - type: integer
|
||||
Parameter BM_CNT_WIDTH bound to: 2 - type: integer
|
||||
Parameter nBANK_MACHS bound to: 3 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter ID bound to: 0 - type: integer
|
||||
Parameter ZERO bound to: 0 - type: integer
|
||||
Parameter ONE bound to: 1 - type: integer
|
||||
@ -1047,7 +1047,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameter
|
||||
Parameter nRTP bound to: 4 - type: integer
|
||||
Parameter nRP bound to: 6 - type: integer
|
||||
Parameter nWTP_CLKS bound to: 5 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter RANK_WIDTH bound to: 1 - type: integer
|
||||
Parameter RANKS bound to: 1 - type: integer
|
||||
Parameter RAS_TIMER_WIDTH bound to: 2 - type: integer
|
||||
@ -1071,7 +1071,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameter
|
||||
Parameter nRTP bound to: 4 - type: integer
|
||||
Parameter nRCD bound to: 6 - type: integer
|
||||
Parameter nWTP_CLKS bound to: 5 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter RANKS bound to: 1 - type: integer
|
||||
Parameter RANK_WIDTH bound to: 1 - type: integer
|
||||
Parameter RAS_TIMER_WIDTH bound to: 2 - type: integer
|
||||
@ -1096,7 +1096,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameter
|
||||
Parameter TCQ bound to: 100 - type: integer
|
||||
Parameter BM_CNT_WIDTH bound to: 2 - type: integer
|
||||
Parameter nBANK_MACHS bound to: 3 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter ID bound to: 1 - type: integer
|
||||
Parameter ZERO bound to: 0 - type: integer
|
||||
Parameter ONE bound to: 1 - type: integer
|
||||
@ -1124,7 +1124,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameter
|
||||
Parameter nRTP bound to: 4 - type: integer
|
||||
Parameter nRP bound to: 6 - type: integer
|
||||
Parameter nWTP_CLKS bound to: 5 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter RANK_WIDTH bound to: 1 - type: integer
|
||||
Parameter RANKS bound to: 1 - type: integer
|
||||
Parameter RAS_TIMER_WIDTH bound to: 2 - type: integer
|
||||
@ -1148,7 +1148,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameter
|
||||
Parameter nRTP bound to: 4 - type: integer
|
||||
Parameter nRCD bound to: 6 - type: integer
|
||||
Parameter nWTP_CLKS bound to: 5 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter RANKS bound to: 1 - type: integer
|
||||
Parameter RANK_WIDTH bound to: 1 - type: integer
|
||||
Parameter RAS_TIMER_WIDTH bound to: 2 - type: integer
|
||||
@ -1173,7 +1173,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameter
|
||||
Parameter TCQ bound to: 100 - type: integer
|
||||
Parameter BM_CNT_WIDTH bound to: 2 - type: integer
|
||||
Parameter nBANK_MACHS bound to: 3 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter ID bound to: 2 - type: integer
|
||||
Parameter ZERO bound to: 0 - type: integer
|
||||
Parameter ONE bound to: 1 - type: integer
|
||||
@ -4046,7 +4046,7 @@ INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_top' [c:/Users/Ale
|
||||
Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer
|
||||
Parameter ECC bound to: OFF - type: string
|
||||
Parameter ECC_TEST bound to: OFF - type: string
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter nCK_PER_CLK bound to: 4 - type: integer
|
||||
Parameter RANKS bound to: 1 - type: integer
|
||||
Parameter REG_CTRL bound to: ON - type: string
|
||||
@ -4090,18 +4090,12 @@ INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instan
|
||||
Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer
|
||||
Parameter ECC bound to: OFF - type: string
|
||||
Parameter nCK_PER_CLK bound to: 4 - type: integer
|
||||
Parameter ORDERING bound to: NORM - type: string
|
||||
Parameter ORDERING bound to: STRICT - type: string
|
||||
Parameter RD_BUF_WIDTH bound to: 256 - type: integer
|
||||
Parameter FULL_RAM_CNT bound to: 42 - type: integer
|
||||
Parameter REMAINDER bound to: 4 - type: integer
|
||||
Parameter RAM_CNT bound to: 43 - type: integer
|
||||
Parameter RAM_WIDTH bound to: 258 - type: integer
|
||||
INFO: [Synth 8-155] case statement is not full and has no default [c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:406]
|
||||
WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_cnt_r' should be on the sensitivity list [c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403]
|
||||
WARNING: [Synth 8-567] referenced signal 'not_strict_mode.free_rd_buf' should be on the sensitivity list [c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403]
|
||||
WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_minus_one' should be on the sensitivity list [c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403]
|
||||
WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_plus_one' should be on the sensitivity list [c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403]
|
||||
WARNING: [Synth 8-567] referenced signal 'not_strict_mode.rd_data_buf_addr_r_lcl' should be on the sensitivity list [c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:432]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_rd_data' (67#1) [c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:140]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_top' (68#1) [c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_top.v:71]
|
||||
Parameter C_FAMILY bound to: virtex7 - type: string
|
||||
@ -4374,19 +4368,19 @@ INFO: [Synth 8-155] case statement is not full and has no default [c:/Users/Alek
|
||||
Parameter C_AXI_STARVE_CNT_WIDTH bound to: 8 - type: integer
|
||||
Parameter C_RD_WR_ARB_ALGORITHM bound to: RD_PRI_REG_STARVE_LIMIT - type: string
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1210.234 ; gain = 194.285
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1207.121 ; gain = 191.184
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1210.234 ; gain = 194.285
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1207.121 ; gain = 191.184
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1210.234 ; gain = 194.285
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1207.121 ; gain = 191.184
|
||||
---------------------------------------------------------------------------------
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.696 . Memory (MB): peak = 1210.234 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 213 Unisim elements for replacement
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.643 . Memory (MB): peak = 1207.121 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 169 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
@ -4403,24 +4397,24 @@ Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_mig
|
||||
INFO: [Timing 38-2] Deriving generated clocks
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1335.184 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1332.695 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 133 instances were transformed.
|
||||
A total of 89 instances were transformed.
|
||||
IOBUFDS_DIFF_OUT_INTERMDISABLE => IOBUFDS_DIFF_OUT_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 4 instances
|
||||
IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 32 instances
|
||||
OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance
|
||||
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 96 instances
|
||||
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 52 instances
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.353 . Memory (MB): peak = 1335.309 ; gain = 0.125
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.292 . Memory (MB): peak = 1332.918 ; gain = 0.223
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 1335.309 ; gain = 319.359
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 1332.918 ; gain = 316.980
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7a100tfgg484-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 1335.309 ; gain = 319.359
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 1332.918 ; gain = 316.980
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
@ -4428,7 +4422,7 @@ Start Applying 'set_property' XDC Constraints
|
||||
Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_n[0]. (constraint file c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/constraints/design_1_mig_7series_0_0.xdc, line 27).
|
||||
Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_p[0]. (constraint file c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/constraints/design_1_mig_7series_0_0.xdc, line 28).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 1335.309 ; gain = 319.359
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 1332.918 ; gain = 316.980
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-802] inferred FSM for state register 'xadc_supplied_temperature.tempmon_state_reg' in module 'mig_7series_v4_2_tempmon'
|
||||
INFO: [Synth 8-802] inferred FSM for state register 'wl_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_wrlvl'
|
||||
@ -5536,8 +5530,6 @@ INFO: [Synth 8-3898] No Re-encoding of one hot register 'tempmon_state_reg' in m
|
||||
2 unexpected non-zero reference counts
|
||||
2 unexpected non-zero reference counts
|
||||
2 unexpected non-zero reference counts
|
||||
2 unexpected non-zero reference counts
|
||||
2 unexpected non-zero reference counts
|
||||
1 unexpected non-zero reference counts
|
||||
---------------------------------------------------------------------------------------------------
|
||||
State | New Encoding | Previous Encoding
|
||||
@ -5550,7 +5542,7 @@ INFO: [Synth 8-3898] No Re-encoding of one hot register 'tempmon_state_reg' in m
|
||||
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'mig_7series_v4_2_axi_mc_r_channel'
|
||||
1 unexpected non-zero reference counts
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:46 ; elapsed = 00:00:49 . Memory (MB): peak = 1335.309 ; gain = 319.359
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 1332.918 ; gain = 316.980
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
@ -5567,7 +5559,7 @@ Detailed RTL Component Info :
|
||||
2 Input 9 Bit Adders := 5
|
||||
2 Input 8 Bit Adders := 11
|
||||
2 Input 7 Bit Adders := 6
|
||||
2 Input 6 Bit Adders := 50
|
||||
2 Input 6 Bit Adders := 49
|
||||
3 Input 6 Bit Adders := 22
|
||||
4 Input 6 Bit Adders := 1
|
||||
2 Input 5 Bit Adders := 47
|
||||
@ -5590,7 +5582,7 @@ Detailed RTL Component Info :
|
||||
2 Input 1 Bit XORs := 1
|
||||
+---Registers :
|
||||
288 Bit Registers := 1
|
||||
256 Bit Registers := 5
|
||||
256 Bit Registers := 4
|
||||
160 Bit Registers := 1
|
||||
88 Bit Registers := 1
|
||||
80 Bit Registers := 4
|
||||
@ -5608,14 +5600,14 @@ Detailed RTL Component Info :
|
||||
9 Bit Registers := 18
|
||||
8 Bit Registers := 30
|
||||
7 Bit Registers := 3
|
||||
6 Bit Registers := 125
|
||||
5 Bit Registers := 57
|
||||
6 Bit Registers := 124
|
||||
5 Bit Registers := 55
|
||||
4 Bit Registers := 89
|
||||
3 Bit Registers := 76
|
||||
2 Bit Registers := 63
|
||||
1 Bit Registers := 1896
|
||||
2 Bit Registers := 62
|
||||
1 Bit Registers := 1891
|
||||
+---Muxes :
|
||||
2 Input 256 Bit Muxes := 11
|
||||
2 Input 256 Bit Muxes := 10
|
||||
4 Input 256 Bit Muxes := 1
|
||||
2 Input 255 Bit Muxes := 1
|
||||
2 Input 80 Bit Muxes := 12
|
||||
@ -5647,15 +5639,15 @@ Detailed RTL Component Info :
|
||||
3 Input 7 Bit Muxes := 2
|
||||
4 Input 7 Bit Muxes := 1
|
||||
5 Input 7 Bit Muxes := 2
|
||||
2 Input 6 Bit Muxes := 131
|
||||
2 Input 6 Bit Muxes := 126
|
||||
4 Input 6 Bit Muxes := 19
|
||||
27 Input 6 Bit Muxes := 6
|
||||
5 Input 6 Bit Muxes := 2
|
||||
16 Input 6 Bit Muxes := 1
|
||||
24 Input 6 Bit Muxes := 5
|
||||
23 Input 6 Bit Muxes := 6
|
||||
3 Input 6 Bit Muxes := 3
|
||||
2 Input 5 Bit Muxes := 39
|
||||
3 Input 6 Bit Muxes := 1
|
||||
2 Input 5 Bit Muxes := 38
|
||||
8 Input 5 Bit Muxes := 4
|
||||
27 Input 5 Bit Muxes := 1
|
||||
58 Input 5 Bit Muxes := 1
|
||||
@ -5675,14 +5667,14 @@ Detailed RTL Component Info :
|
||||
8 Input 3 Bit Muxes := 2
|
||||
9 Input 3 Bit Muxes := 1
|
||||
10 Input 3 Bit Muxes := 1
|
||||
2 Input 2 Bit Muxes := 91
|
||||
3 Input 2 Bit Muxes := 7
|
||||
2 Input 2 Bit Muxes := 90
|
||||
3 Input 2 Bit Muxes := 6
|
||||
8 Input 2 Bit Muxes := 8
|
||||
24 Input 2 Bit Muxes := 1
|
||||
23 Input 2 Bit Muxes := 3
|
||||
4 Input 2 Bit Muxes := 3
|
||||
5 Input 2 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 774
|
||||
2 Input 1 Bit Muxes := 772
|
||||
3 Input 1 Bit Muxes := 31
|
||||
4 Input 1 Bit Muxes := 150
|
||||
8 Input 1 Bit Muxes := 8
|
||||
@ -6215,11 +6207,10 @@ Start Cross Boundary and Area Optimization
|
||||
6 unexpected non-zero reference counts
|
||||
20 unexpected non-zero reference counts
|
||||
2 unexpected non-zero reference counts
|
||||
2 unexpected non-zero reference counts
|
||||
66 unexpected non-zero reference counts
|
||||
66 unexpected non-zero reference counts
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:53 ; elapsed = 00:01:58 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:52 ; elapsed = 00:01:56 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP and Shift Register Reporting
|
||||
@ -6261,13 +6252,13 @@ Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-3321] set_false_path : Empty through list for constraint at line 509 of c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/constraints/design_1_mig_7series_0_0.xdc. [c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/constraints/design_1_mig_7series_0_0.xdc:509]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:59 ; elapsed = 00:02:05 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:58 ; elapsed = 00:02:03 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:02:02 ; elapsed = 00:02:07 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Finished Timing Optimization : Time (s): cpu = 00:02:01 ; elapsed = 00:02:05 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP and Shift Register Reporting
|
||||
@ -6298,7 +6289,7 @@ Finished ROM, RAM, DSP and Shift Register Reporting
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:02:07 ; elapsed = 00:02:13 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Finished Technology Mapping : Time (s): cpu = 00:02:06 ; elapsed = 00:02:11 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
@ -6316,37 +6307,37 @@ Start Final Netlist Cleanup
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:02:11 ; elapsed = 00:02:16 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Finished IO Insertion : Time (s): cpu = 00:02:09 ; elapsed = 00:02:14 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:02:11 ; elapsed = 00:02:16 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:02:09 ; elapsed = 00:02:14 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:13 ; elapsed = 00:02:18 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:11 ; elapsed = 00:02:16 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:02:13 ; elapsed = 00:02:18 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:02:11 ; elapsed = 00:02:16 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:02:13 ; elapsed = 00:02:18 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:02:12 ; elapsed = 00:02:16 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:02:13 ; elapsed = 00:02:19 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:02:12 ; elapsed = 00:02:16 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP and Shift Register Reporting
|
||||
@ -6408,12 +6399,12 @@ Report Cell Usage:
|
||||
|7 |IDELAYE2 | 32|
|
||||
|8 |IN_FIFO | 4|
|
||||
|9 |ISERDESE2 | 32|
|
||||
|10 |LUT1 | 458|
|
||||
|11 |LUT2 | 661|
|
||||
|12 |LUT3 | 2175|
|
||||
|13 |LUT4 | 1188|
|
||||
|14 |LUT5 | 1520|
|
||||
|15 |LUT6 | 1177|
|
||||
|10 |LUT1 | 451|
|
||||
|11 |LUT2 | 641|
|
||||
|12 |LUT3 | 1932|
|
||||
|13 |LUT4 | 1168|
|
||||
|14 |LUT5 | 1531|
|
||||
|15 |LUT6 | 1169|
|
||||
|16 |MMCME2_ADV | 1|
|
||||
|17 |MUXF7 | 2|
|
||||
|18 |ODDR | 9|
|
||||
@ -6424,14 +6415,14 @@ Report Cell Usage:
|
||||
|27 |PHASER_REF | 2|
|
||||
|28 |PHY_CONTROL | 2|
|
||||
|29 |PLLE2_ADV | 1|
|
||||
|30 |RAM32M | 222|
|
||||
|30 |RAM32M | 177|
|
||||
|31 |SRL16E | 18|
|
||||
|32 |SRLC32E | 259|
|
||||
|33 |XADC | 1|
|
||||
|34 |FDCE | 3|
|
||||
|35 |FDPE | 76|
|
||||
|36 |FDRE | 5525|
|
||||
|37 |FDSE | 260|
|
||||
|36 |FDRE | 5234|
|
||||
|37 |FDSE | 259|
|
||||
|38 |IOBUFDS_DIFF_OUT_INTERMDISABLE | 4|
|
||||
|39 |IOBUF_INTERMDISABLE | 32|
|
||||
|40 |OBUF | 25|
|
||||
@ -6439,37 +6430,37 @@ Report Cell Usage:
|
||||
|42 |OBUFT | 4|
|
||||
+------+-------------------------------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:02:13 ; elapsed = 00:02:19 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:02:12 ; elapsed = 00:02:16 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:01:46 ; elapsed = 00:02:09 . Memory (MB): peak = 1397.359 ; gain = 256.336
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:02:13 ; elapsed = 00:02:19 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:01:47 ; elapsed = 00:02:07 . Memory (MB): peak = 1396.910 ; gain = 255.176
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:02:12 ; elapsed = 00:02:16 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.554 . Memory (MB): peak = 1397.359 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 468 Unisim elements for replacement
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.463 . Memory (MB): peak = 1396.910 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 423 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 4 inverter(s) to 32 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1397.359 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1396.910 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 259 instances were transformed.
|
||||
A total of 214 instances were transformed.
|
||||
IOBUFDS_DIFF_OUT_INTERMDISABLE => IOBUFDS_DIFF_OUT_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 4 instances
|
||||
IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 32 instances
|
||||
OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance
|
||||
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 222 instances
|
||||
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 177 instances
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
245 Infos, 34 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
244 Infos, 29 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:02:22 ; elapsed = 00:02:28 . Memory (MB): peak = 1397.359 ; gain = 381.410
|
||||
synth_design: Time (s): cpu = 00:02:20 ; elapsed = 00:02:25 . Memory (MB): peak = 1396.910 ; gain = 380.973
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.runs/design_1_mig_7series_0_0_synth_1/design_1_mig_7series_0_0.dcp' has been generated.
|
||||
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP design_1_mig_7series_0_0, cache-ID = de240defa7bad4ca
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP design_1_mig_7series_0_0, cache-ID = 8abae3f1fc384d9a
|
||||
INFO: [Coretcl 2-1174] Renamed 106 cell refs.
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.runs/design_1_mig_7series_0_0_synth_1/design_1_mig_7series_0_0.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file design_1_mig_7series_0_0_utilization_synth.rpt -pb design_1_mig_7series_0_0_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue May 18 14:08:07 2021...
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed May 19 10:55:24 2021...
|
||||
|
||||
@ -2,8 +2,8 @@
|
||||
# Vivado v2020.1 (64-bit)
|
||||
# SW Build 2902540 on Wed May 27 19:54:49 MDT 2020
|
||||
# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
|
||||
# Start of session at: Tue May 18 14:05:23 2021
|
||||
# Process ID: 3096
|
||||
# Start of session at: Wed May 19 10:52:45 2021
|
||||
# Process ID: 4108
|
||||
# Current directory: C:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.runs/design_1_mig_7series_0_0_synth_1
|
||||
# Command line: vivado.exe -log design_1_mig_7series_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_mig_7series_0_0.tcl
|
||||
# Log file: C:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.runs/design_1_mig_7series_0_0_synth_1/design_1_mig_7series_0_0.vds
|
||||
|
||||
Binary file not shown.
@ -1,5 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command=".planAhead." Owner="Aleksa" Host="DESKTOP-J72MK93" Pid="1940">
|
||||
<Process Command=".planAhead." Owner="Aleksa" Host="DESKTOP-J72MK93" Pid="7892">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command=".planAhead." Owner="Aleksa" Host="DESKTOP-J72MK93" Pid="1940">
|
||||
<Process Command=".planAhead." Owner="Aleksa" Host="DESKTOP-J72MK93" Pid="7892">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command=".planAhead." Owner="Aleksa" Host="DESKTOP-J72MK93" Pid="1940">
|
||||
<Process Command=".planAhead." Owner="Aleksa" Host="DESKTOP-J72MK93" Pid="7892">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command=".planAhead." Owner="Aleksa" Host="DESKTOP-J72MK93" Pid="1940">
|
||||
<Process Command=".planAhead." Owner="Aleksa" Host="DESKTOP-J72MK93" Pid="7892">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user