mirror of
https://github.com/EEVengers/ThunderScope.git
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Merge pull request #187 from EEVengers/FW/Aleksa/dso_top
dso_top working at 1GB/s using both DDR3 chips
This commit is contained in:
Aleksa Bjelogrlic
GitHub
commit
a4cb38f518
Firmware/Artix7_PCIe/dso_top
dso_top.bindso_top.xpr
dso_top.cache/wt
dso_top.hw/hw_1
dso_top.ip_user_files
bd/design_1/ip/design_1_smartconnect_0_0
ip
clk_wiz_0
fifo_generator_0
ipstatic
mmcm_pll_drp_func_7s_mmcm.vhmmcm_pll_drp_func_7s_pll.vhmmcm_pll_drp_func_us_mmcm.vhmmcm_pll_drp_func_us_pll.vhmmcm_pll_drp_func_us_plus_mmcm.vhmmcm_pll_drp_func_us_plus_pll.vh
sim_scripts/fifo_generator_0
README.txt
activehdl
ies
modelsim
questa
README.txtcompile.doelaborate.dofifo_generator_0.shfifo_generator_0.udofile_info.txtglbl.vsimulate.dowave.do
riviera
vcs
xcelium
xsim
dso_top.srcs/sources_1
bd/design_1
design_1.bddesign_1.bxml
hdl
hw_handoff
ip
design_1_auto_cc_0
design_1_auto_cc_0.dcpdesign_1_auto_cc_0.xcidesign_1_auto_cc_0.xmldesign_1_auto_cc_0_sim_netlist.vdesign_1_auto_cc_0_sim_netlist.vhdldesign_1_auto_cc_0_stub.vdesign_1_auto_cc_0_stub.vhdl
sim
design_1_auto_cc_0.cppdesign_1_auto_cc_0.hdesign_1_auto_cc_0.vdesign_1_auto_cc_0_sc.cppdesign_1_auto_cc_0_stub.sv
synth
design_1_auto_us_df_0
design_1_auto_us_df_0.dcpdesign_1_auto_us_df_0.xcidesign_1_auto_us_df_0.xmldesign_1_auto_us_df_0_clocks.xdcdesign_1_auto_us_df_0_ooc.xdcdesign_1_auto_us_df_0_sim_netlist.vdesign_1_auto_us_df_0_sim_netlist.vhdldesign_1_auto_us_df_0_stub.vdesign_1_auto_us_df_0_stub.vhdl
sim
design_1_auto_us_df_0.cppdesign_1_auto_us_df_0.hdesign_1_auto_us_df_0.vdesign_1_auto_us_df_0_sc.cppdesign_1_auto_us_df_0_sc.hdesign_1_auto_us_df_0_stub.sv
src
synth
design_1_auto_us_df_1
design_1_auto_us_df_1.dcpdesign_1_auto_us_df_1.xcidesign_1_auto_us_df_1.xmldesign_1_auto_us_df_1_clocks.xdcdesign_1_auto_us_df_1_ooc.xdcdesign_1_auto_us_df_1_sim_netlist.vdesign_1_auto_us_df_1_sim_netlist.vhdldesign_1_auto_us_df_1_stub.vdesign_1_auto_us_df_1_stub.vhdl
sim
design_1_auto_us_df_1.cppdesign_1_auto_us_df_1.hdesign_1_auto_us_df_1.vdesign_1_auto_us_df_1_sc.cppdesign_1_auto_us_df_1_sc.hdesign_1_auto_us_df_1_stub.sv
src
synth
design_1_axi_datamover_0_0
design_1_axi_datamover_0_0.dcpdesign_1_axi_datamover_0_0.xcidesign_1_axi_datamover_0_0.xmldesign_1_axi_datamover_0_0_sim_netlist.vdesign_1_axi_datamover_0_0_sim_netlist.vhdldesign_1_axi_datamover_0_0_stub.vdesign_1_axi_datamover_0_0_stub.vhdl
sim
synth
design_1_axi_fifo_mm_s_0_0
design_1_axi_fifo_mm_s_0_0.dcpdesign_1_axi_fifo_mm_s_0_0.xmldesign_1_axi_fifo_mm_s_0_0_sim_netlist.vdesign_1_axi_fifo_mm_s_0_0_sim_netlist.vhdldesign_1_axi_fifo_mm_s_0_0_stub.vdesign_1_axi_fifo_mm_s_0_0_stub.vhdl
design_1_axi_gpio_0_1
design_1_axi_gpio_0_1.dcpdesign_1_axi_gpio_0_1.xmldesign_1_axi_gpio_0_1_sim_netlist.vdesign_1_axi_gpio_0_1_sim_netlist.vhdldesign_1_axi_gpio_0_1_stub.vdesign_1_axi_gpio_0_1_stub.vhdl
design_1_axi_gpio_1_0
design_1_axi_gpio_1_0.dcpdesign_1_axi_gpio_1_0.xmldesign_1_axi_gpio_1_0_sim_netlist.vdesign_1_axi_gpio_1_0_sim_netlist.vhdldesign_1_axi_gpio_1_0_stub.vdesign_1_axi_gpio_1_0_stub.vhdl
design_1_axi_interconnect_0_0
design_1_axis_subset_converter_0_0
design_1_axis_subset_converter_0_0.dcpdesign_1_axis_subset_converter_0_0.xcidesign_1_axis_subset_converter_0_0.xmldesign_1_axis_subset_converter_0_0_ooc.xdcdesign_1_axis_subset_converter_0_0_sim_netlist.vdesign_1_axis_subset_converter_0_0_sim_netlist.vhdldesign_1_axis_subset_converter_0_0_stub.vdesign_1_axis_subset_converter_0_0_stub.vhdl
hdl
tlast_design_1_axis_subset_converter_0_0.vtop_design_1_axis_subset_converter_0_0.vtstrb_design_1_axis_subset_converter_0_0.vtuser_design_1_axis_subset_converter_0_0.v
sim
synth
design_1_clk_wiz_0_0
design_1_clk_wiz_0_0.dcpdesign_1_clk_wiz_0_0.xmldesign_1_clk_wiz_0_0_sim_netlist.vdesign_1_clk_wiz_0_0_sim_netlist.vhdldesign_1_clk_wiz_0_0_stub.vdesign_1_clk_wiz_0_0_stub.vhdl
design_1_m00_data_fifo_0
design_1_m00_data_fifo_0.dcpdesign_1_m00_data_fifo_0.xcidesign_1_m00_data_fifo_0.xmldesign_1_m00_data_fifo_0_clocks.xdcdesign_1_m00_data_fifo_0_ooc.xdcdesign_1_m00_data_fifo_0_sim_netlist.vdesign_1_m00_data_fifo_0_sim_netlist.vhdldesign_1_m00_data_fifo_0_stub.vdesign_1_m00_data_fifo_0_stub.vhdl
sim
design_1_m00_data_fifo_0.cppdesign_1_m00_data_fifo_0.hdesign_1_m00_data_fifo_0.vdesign_1_m00_data_fifo_0_sc.cppdesign_1_m00_data_fifo_0_sc.hdesign_1_m00_data_fifo_0_stub.sv
synth
sysc
design_1_mig_7series_0_0
design_1_mig_7series_0_0.dcpdesign_1_mig_7series_0_0.veodesign_1_mig_7series_0_0.xcidesign_1_mig_7series_0_0.xml
design_1_mig_7series_0_0
design_1_mig_7series_0_0_sim_netlist.vdesign_1_mig_7series_0_0_sim_netlist.vhdldesign_1_mig_7series_0_0_stub.vdesign_1_mig_7series_0_0_stub.vhdldesign_1_mig_7series_0_0_xmdf.tclmig_a.prjmig_b.prjxil_txt.inxil_txt.outdesign_1_smartconnect_0_0
bd_0
bd_48ac.bdbd_48ac.bxml
design_1_smartconnect_0_0.dcpdesign_1_smartconnect_0_0.xmldesign_1_smartconnect_0_0_sim_netlist.vdesign_1_smartconnect_0_0_sim_netlist.vhdldesign_1_smartconnect_0_0_stub.vdesign_1_smartconnect_0_0_stub.vhdlhw_handoff
ip
ip_0
ip_1
ip_10
ip_11
ip_12
ip_13
ip_14
ip_15
ip_16
ip_17
ip_18
ip_19
ip_2
ip_20
ip_21
ip_22
ip_23
ip_24
ip_25
ip_26
ip_27
ip_28
ip_29
ip_3
ip_30
ip_31
ip_32
ip_33
ip_34
ip_35
ip_36
ip_37
ip_38
ip_39
ip_4
ip_40
ip_41
ip_42
ip_43
ip_44
ip_45
ip_46
ip_5
ip_6
ip_7
ip_8
ip_9
sim
synth
design_1_util_ds_buf_0_0
design_1_util_ds_buf_0_0.dcpdesign_1_util_ds_buf_0_0.xmldesign_1_util_ds_buf_0_0_sim_netlist.vdesign_1_util_ds_buf_0_0_sim_netlist.vhdldesign_1_util_ds_buf_0_0_stub.vdesign_1_util_ds_buf_0_0_stub.vhdl
design_1_util_vector_logic_0_0
design_1_util_vector_logic_0_0.dcpdesign_1_util_vector_logic_0_0.xmldesign_1_util_vector_logic_0_0_sim_netlist.vdesign_1_util_vector_logic_0_0_sim_netlist.vhdldesign_1_util_vector_logic_0_0_stub.vdesign_1_util_vector_logic_0_0_stub.vhdl
design_1_xbar_0
design_1_xbar_0.dcpdesign_1_xbar_0.xcidesign_1_xbar_0.xmldesign_1_xbar_0_sim_netlist.vdesign_1_xbar_0_sim_netlist.vhdldesign_1_xbar_0_stub.vdesign_1_xbar_0_stub.vhdl
sim
synth
design_1_xdma_0_0
design_1_xdma_0_0.dcpdesign_1_xdma_0_0.xcidesign_1_xdma_0_0.xmldesign_1_xdma_0_0_sim_netlist.vdesign_1_xdma_0_0_sim_netlist.vhdldesign_1_xdma_0_0_stub.vdesign_1_xdma_0_0_stub.vhdl
ip_0
ip_1
ip_2
ip_3
ip_4
sim
synth
design_1_xlconstant_0_0
design_1_xlconstant_0_2
design_1_xlconstant_0_3
ipshared
07be/hdl
128c/hdl
7da1/hdl
8713/hdl
8dfa/hdl
sim
synth
ui
imports/hdl
ip
clk_wiz_0.xcixselectio_wiz_0.xcixselectio_wiz_0_1.xcix
fifo_generator_0
doc
fifo_generator_0.dcpfifo_generator_0.veofifo_generator_0.vhofifo_generator_0.xcififo_generator_0.xmlfifo_generator_0_sim_netlist.vfifo_generator_0_sim_netlist.vhdlfifo_generator_0_stub.vfifo_generator_0_stub.vhdlhdl
sim
simulation
synth
new
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||||
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53
Firmware/Artix7_PCIe/dso_top/dso_top.cache/wt/webtalk_pa.xml
Normal file
53
Firmware/Artix7_PCIe/dso_top/dso_top.cache/wt/webtalk_pa.xml
Normal file
@ -0,0 +1,53 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<document>
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Mon Mar 22 20:43:54 2021">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="847144bab49e4468a88be2f2e5cf8d33" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||
</section>
|
||||
<section name="PlanAhead Usage" visible="true">
|
||||
<item name="Project Data">
|
||||
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
|
||||
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
|
||||
<property name="DesignMode" value="RTL" type="DesignMode"/>
|
||||
<property name="SynthesisStrategy" value="Flow_PerfOptimized_high" type="SynthesisStrategy"/>
|
||||
<property name="ImplStrategy" value="Performance_ExtraTimingOpt" type="ImplStrategy"/>
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="FileExit" value="1" type="JavaHandler"/>
|
||||
<property name="OpenHardwareManager" value="1" type="JavaHandler"/>
|
||||
<property name="ProgramCfgMem" value="1" type="JavaHandler"/>
|
||||
<property name="SaveProjectAs" value="1" type="JavaHandler"/>
|
||||
<property name="ViewTaskProjectManager" value="1" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="BaseDialog_OK" value="3" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_OK" value="1" type="GuiHandlerData"/>
|
||||
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="1" type="GuiHandlerData"/>
|
||||
<property name="HardwareTreePanel_HARDWARE_TREE_TABLE" value="1" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_CHECKPOINT" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_EXPORT" value="1" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FILE" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_IMPORT" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_IP" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_PROJECT" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_TEXT_EDITOR" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_PROGRAM_CONFIG_MEMORY" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SAVE_PROJECT_AS" value="1" type="GuiHandlerData"/>
|
||||
<property name="PAViews_PROJECT_SUMMARY" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProjectNameChooser_CHOOSE_PROJECT_LOCATION" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProjectNameChooser_PROJECT_NAME" value="1" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectAsDialog_INCLUDE_RUN_RESULTS" value="1" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="3" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="2" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
</document>
|
||||
@ -12,7 +12,7 @@
|
||||
<Properties Property="PROGRAM.CFG_PROGRAM" value="1"/>
|
||||
<Properties Property="PROGRAM.CHECKSUM" value="0"/>
|
||||
<Properties Property="PROGRAM.ERASE" value="1"/>
|
||||
<Properties Property="PROGRAM.FILES" value="$_project_name_.runs/impl_1/$_project_name_.bin"/>
|
||||
<Properties Property="PROGRAM.FILES" value="$_project_name_.runs/impl_1/dso_top.bin"/>
|
||||
<Properties Property="PROGRAM.PRM_FILE" value=""/>
|
||||
<Properties Property="PROGRAM.UNUSED_PIN_TERMINATION" value="pull-none"/>
|
||||
<Properties Property="PROGRAM.VERIFY" value="1"/>
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -135,7 +135,7 @@ M02_AXI.IS_CASCADED 0
|
||||
S00_AXI.IS_CASCADED 0
|
||||
S00_AXI.NUM_SEG 3
|
||||
S00_AXI.SEG000.BASE_ADDR 0x0000000040000000
|
||||
S00_AXI.SEG000.SIZE 12
|
||||
S00_AXI.SEG000.SIZE 16
|
||||
S00_AXI.SEG000.SUPPORTS_READ 1
|
||||
S00_AXI.SEG000.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG000.SECURE_READ 0
|
||||
@ -143,8 +143,8 @@ S00_AXI.SEG000.SECURE_WRITE 0
|
||||
S00_AXI.SEG000.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000001
|
||||
S00_AXI.SEG000.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG000.DATA_WIDTH 32
|
||||
S00_AXI.SEG001.BASE_ADDR 0x0000000040001000
|
||||
S00_AXI.SEG001.SIZE 12
|
||||
S00_AXI.SEG001.BASE_ADDR 0x0000000040010000
|
||||
S00_AXI.SEG001.SIZE 16
|
||||
S00_AXI.SEG001.SUPPORTS_READ 1
|
||||
S00_AXI.SEG001.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG001.SECURE_READ 0
|
||||
@ -152,8 +152,8 @@ S00_AXI.SEG001.SECURE_WRITE 0
|
||||
S00_AXI.SEG001.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000010
|
||||
S00_AXI.SEG001.PROTOCOL AXI4LITE
|
||||
S00_AXI.SEG001.DATA_WIDTH 32
|
||||
S00_AXI.SEG002.BASE_ADDR 0x0000000040002000
|
||||
S00_AXI.SEG002.SIZE 12
|
||||
S00_AXI.SEG002.BASE_ADDR 0x0000000040020000
|
||||
S00_AXI.SEG002.SIZE 16
|
||||
S00_AXI.SEG002.SUPPORTS_READ 1
|
||||
S00_AXI.SEG002.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG002.SECURE_READ 0
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
|
||||
// Date : Fri Mar 19 19:26:27 2021
|
||||
// Date : Mon Mar 22 18:58:31 2021
|
||||
// Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim -rename_top clk_wiz_0 -prefix
|
||||
// clk_wiz_0_ clk_wiz_0_sim_netlist.v
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// C:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3_4KB/dso_top_ddr3.runs/clk_wiz_0_synth_1/clk_wiz_0_sim_netlist.v
|
||||
// Design : clk_wiz_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
@ -39,6 +39,7 @@ module clk_wiz_0
|
||||
.clk_out3(clk_out3));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "clk_wiz_0_clk_wiz" *)
|
||||
module clk_wiz_0_clk_wiz_0_clk_wiz
|
||||
(clk_out1,
|
||||
clk_out2,
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
|
||||
-- Date : Fri Mar 19 19:26:27 2021
|
||||
-- Date : Mon Mar 22 18:58:31 2021
|
||||
-- Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim -rename_top clk_wiz_0 -prefix
|
||||
-- clk_wiz_0_ clk_wiz_0_sim_netlist.vhdl
|
||||
-- Command : write_vhdl -force -mode funcsim
|
||||
-- C:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3_4KB/dso_top_ddr3.runs/clk_wiz_0_synth_1/clk_wiz_0_sim_netlist.vhdl
|
||||
-- Design : clk_wiz_0
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
@ -22,6 +22,8 @@ entity clk_wiz_0_clk_wiz_0_clk_wiz is
|
||||
clk_in1_p : in STD_LOGIC;
|
||||
clk_in1_n : in STD_LOGIC
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of clk_wiz_0_clk_wiz_0_clk_wiz : entity is "clk_wiz_0_clk_wiz";
|
||||
end clk_wiz_0_clk_wiz_0_clk_wiz;
|
||||
|
||||
architecture STRUCTURE of clk_wiz_0_clk_wiz_0_clk_wiz is
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
|
||||
// Date : Fri Mar 19 19:26:27 2021
|
||||
// Date : Mon Mar 22 18:58:31 2021
|
||||
// Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top clk_wiz_0 -prefix
|
||||
// clk_wiz_0_ clk_wiz_0_stub.v
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// C:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3_4KB/dso_top_ddr3.runs/clk_wiz_0_synth_1/clk_wiz_0_stub.v
|
||||
// Design : clk_wiz_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7a100tfgg484-2
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
|
||||
-- Date : Fri Mar 19 19:26:27 2021
|
||||
-- Date : Mon Mar 22 18:58:31 2021
|
||||
-- Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top clk_wiz_0 -prefix
|
||||
-- clk_wiz_0_ clk_wiz_0_stub.vhdl
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- C:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3_4KB/dso_top_ddr3.runs/clk_wiz_0_synth_1/clk_wiz_0_stub.vhdl
|
||||
-- Design : clk_wiz_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7a100tfgg484-2
|
||||
|
||||
@ -1,12 +1,10 @@
|
||||
|
||||
//*****************************************************************************
|
||||
// (c) Copyright 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
@ -28,7 +26,7 @@
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
@ -42,29 +40,36 @@
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
`timescale 1ps/1ps
|
||||
// IP VLNV: xilinx.com:ip:fifo_generator:13.2
|
||||
// IP Revision: 5
|
||||
|
||||
module tdata_design_1_axis_subset_converter_0_0 #
|
||||
(
|
||||
parameter C_S_AXIS_TDATA_WIDTH = 32,
|
||||
parameter C_S_AXIS_TUSER_WIDTH = 0,
|
||||
parameter C_S_AXIS_TID_WIDTH = 0,
|
||||
parameter C_S_AXIS_TDEST_WIDTH = 0,
|
||||
parameter C_M_AXIS_TDATA_WIDTH = 32
|
||||
)
|
||||
(
|
||||
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0 ] tdata,
|
||||
input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0 ] tuser,
|
||||
input [(C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0 ] tid,
|
||||
input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0 ] tdest,
|
||||
input [(C_S_AXIS_TDATA_WIDTH/8)-1:0 ] tkeep,
|
||||
input [(C_S_AXIS_TDATA_WIDTH/8)-1:0 ] tstrb,
|
||||
input tlast,
|
||||
output [C_M_AXIS_TDATA_WIDTH-1:0] tdata_out
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
fifo_generator_0 your_instance_name (
|
||||
.rst(rst), // input wire rst
|
||||
.wr_clk(wr_clk), // input wire wr_clk
|
||||
.rd_clk(rd_clk), // input wire rd_clk
|
||||
.din(din), // input wire [63 : 0] din
|
||||
.wr_en(wr_en), // input wire wr_en
|
||||
.rd_en(rd_en), // input wire rd_en
|
||||
.dout(dout), // output wire [127 : 0] dout
|
||||
.full(full), // output wire full
|
||||
.empty(empty), // output wire empty
|
||||
.wr_rst_busy(wr_rst_busy), // output wire wr_rst_busy
|
||||
.rd_rst_busy(rd_rst_busy) // output wire rd_rst_busy
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
assign tdata_out = {tdata[127:0]};
|
||||
|
||||
endmodule
|
||||
// You must compile the wrapper file fifo_generator_0.v when simulating
|
||||
// the core, fifo_generator_0. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
@ -0,0 +1,95 @@
|
||||
-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
|
||||
-- IP Revision: 5
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT fifo_generator_0
|
||||
PORT (
|
||||
rst : IN STD_LOGIC;
|
||||
wr_clk : IN STD_LOGIC;
|
||||
rd_clk : IN STD_LOGIC;
|
||||
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
wr_en : IN STD_LOGIC;
|
||||
rd_en : IN STD_LOGIC;
|
||||
dout : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
|
||||
full : OUT STD_LOGIC;
|
||||
empty : OUT STD_LOGIC;
|
||||
wr_rst_busy : OUT STD_LOGIC;
|
||||
rd_rst_busy : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : fifo_generator_0
|
||||
PORT MAP (
|
||||
rst => rst,
|
||||
wr_clk => wr_clk,
|
||||
rd_clk => rd_clk,
|
||||
din => din,
|
||||
wr_en => wr_en,
|
||||
rd_en => rd_en,
|
||||
dout => dout,
|
||||
full => full,
|
||||
empty => empty,
|
||||
wr_rst_busy => wr_rst_busy,
|
||||
rd_rst_busy => rd_rst_busy
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file fifo_generator_0.vhd when simulating
|
||||
-- the core, fifo_generator_0. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
@ -0,0 +1,31 @@
|
||||
// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
|
||||
// Date : Mon Mar 22 18:49:47 2021
|
||||
// Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3_4KB/dso_top_ddr3.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0_stub.v
|
||||
// Design : fifo_generator_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7a100tfgg484-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "fifo_generator_v13_2_5,Vivado 2020.1" *)
|
||||
module fifo_generator_0(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
|
||||
empty, wr_rst_busy, rd_rst_busy)
|
||||
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[63:0],wr_en,rd_en,dout[127:0],full,empty,wr_rst_busy,rd_rst_busy" */;
|
||||
input rst;
|
||||
input wr_clk;
|
||||
input rd_clk;
|
||||
input [63:0]din;
|
||||
input wr_en;
|
||||
input rd_en;
|
||||
output [127:0]dout;
|
||||
output full;
|
||||
output empty;
|
||||
output wr_rst_busy;
|
||||
output rd_rst_busy;
|
||||
endmodule
|
||||
@ -0,0 +1,40 @@
|
||||
-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
|
||||
-- Date : Mon Mar 22 18:49:47 2021
|
||||
-- Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3_4KB/dso_top_ddr3.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0_stub.vhdl
|
||||
-- Design : fifo_generator_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7a100tfgg484-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity fifo_generator_0 is
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
wr_clk : in STD_LOGIC;
|
||||
rd_clk : in STD_LOGIC;
|
||||
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
wr_en : in STD_LOGIC;
|
||||
rd_en : in STD_LOGIC;
|
||||
dout : out STD_LOGIC_VECTOR ( 127 downto 0 );
|
||||
full : out STD_LOGIC;
|
||||
empty : out STD_LOGIC;
|
||||
wr_rst_busy : out STD_LOGIC;
|
||||
rd_rst_busy : out STD_LOGIC
|
||||
);
|
||||
|
||||
end fifo_generator_0;
|
||||
|
||||
architecture stub of fifo_generator_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[63:0],wr_en,rd_en,dout[127:0],full,empty,wr_rst_busy,rd_rst_busy";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.1";
|
||||
begin
|
||||
end;
|
||||
@ -1,671 +0,0 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Company: Xilinx
|
||||
// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing
|
||||
// Date: 7/30/2014
|
||||
// Design Name: MMCME2 DRP
|
||||
// Module Name: mmcme2_drp_func.h
|
||||
// Version: 1.04
|
||||
// Target Devices: 7 Series || MMCM
|
||||
// Tool versions: 2014.3
|
||||
// Description: This header provides the functions necessary to
|
||||
// calculate the DRP register values for the V6 MMCM.
|
||||
//
|
||||
// Revision Notes: 3/12 - Updating lookup_low/lookup_high (CR)
|
||||
// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807
|
||||
//
|
||||
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
|
||||
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
|
||||
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
|
||||
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
||||
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
|
||||
// APPLICATION OR STANDARD, XILINX IS MAKING NO
|
||||
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
|
||||
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
|
||||
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
|
||||
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
|
||||
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
|
||||
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
|
||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
// PURPOSE.
|
||||
//
|
||||
// (c) Copyright 2009-2010 Xilinx, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// These are user functions that should not be modified. Changes to the defines
|
||||
// or code within the functions may alter the accuracy of the calculations.
|
||||
|
||||
// Define debug to provide extra messages durring elaboration
|
||||
//`define DEBUG 1
|
||||
|
||||
// FRAC_PRECISION describes the width of the fractional portion of the fixed
|
||||
// point numbers. These should not be modified, they are for development
|
||||
// only
|
||||
`define FRAC_PRECISION 10
|
||||
// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
|
||||
// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
|
||||
// greater than 32
|
||||
`define FIXED_WIDTH 32
|
||||
|
||||
// This function takes a fixed point number and rounds it to the nearest
|
||||
// fractional precision bit.
|
||||
function [`FIXED_WIDTH:1] round_frac
|
||||
(
|
||||
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
|
||||
input [`FIXED_WIDTH:1] decimal,
|
||||
|
||||
// This describes the precision of the fraction, for example a value
|
||||
// of 1 would modify the fractional so that instead of being a .16
|
||||
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
|
||||
input [`FIXED_WIDTH:1] precision
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("round_frac - decimal: %h, precision: %h", decimal, precision);
|
||||
`endif
|
||||
// If the fractional precision bit is high then round up
|
||||
if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
|
||||
round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
|
||||
end else begin
|
||||
round_frac = decimal;
|
||||
end
|
||||
`ifdef DEBUG
|
||||
$display("round_frac: %h", round_frac);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates high_time, low_time, w_edge, and no_count
|
||||
// of a non-fractional counter based on the divide and duty cycle
|
||||
//
|
||||
// NOTE: high_time and low_time are returned as integers between 0 and 63
|
||||
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
|
||||
// ignore the overflow)
|
||||
function [13:0] mmcm_pll_divider
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] duty_cycle_fix;
|
||||
|
||||
// High/Low time is initially calculated with a wider integer to prevent a
|
||||
// calculation error when it overflows to 64.
|
||||
reg [6:0] high_time;
|
||||
reg [6:0] low_time;
|
||||
reg w_edge;
|
||||
reg no_count;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
// Duty Cycle must be between 0 and 1,000
|
||||
if(duty_cycle <=0 || duty_cycle >= 100000) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
|
||||
duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("duty_cycle_fix: %h", duty_cycle_fix);
|
||||
`endif
|
||||
|
||||
// If the divide is 1 nothing needs to be set except the no_count bit.
|
||||
// Other values are dummies
|
||||
if(divide == 7'h01) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
low_time = 7'h01;
|
||||
no_count = 1'b1;
|
||||
end else begin
|
||||
temp = round_frac(duty_cycle_fix*divide, 1);
|
||||
|
||||
// comes from above round_frac
|
||||
high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
|
||||
// If the duty cycle * divide rounded is .5 or greater then this bit
|
||||
// is set.
|
||||
w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
|
||||
|
||||
// If the high time comes out to 0, it needs to be set to at least 1
|
||||
// and w_edge set to 0
|
||||
if(high_time == 7'h00) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
end
|
||||
|
||||
if(high_time == divide) begin
|
||||
high_time = divide - 1;
|
||||
w_edge = 1'b1;
|
||||
end
|
||||
|
||||
// Calculate low_time based on the divide setting and set no_count to
|
||||
// 0 as it is only used when divide is 1.
|
||||
low_time = divide - high_time;
|
||||
no_count = 1'b0;
|
||||
end
|
||||
|
||||
// Set the return value.
|
||||
mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates mx, delay_time, and phase_mux
|
||||
// of a non-fractional counter based on the divide and phase
|
||||
//
|
||||
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
|
||||
// is used.
|
||||
function [10:0] mmcm_pll_phase
|
||||
(
|
||||
// divide must be an integer (use fractional if not)
|
||||
// assumed that divide already checked to be valid
|
||||
input [7:0] divide, // Max divide is 128
|
||||
|
||||
// Phase is given in degrees (-360,000 to 360,000)
|
||||
input signed [31:0] phase
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] phase_in_cycles;
|
||||
reg [`FIXED_WIDTH:1] phase_fixed;
|
||||
reg [1:0] mx;
|
||||
reg [5:0] delay_time;
|
||||
reg [2:0] phase_mux;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_pll_phase-divide:%d,phase:%d",
|
||||
divide, phase);
|
||||
`endif
|
||||
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// If phase is less than 0, convert it to a positive phase shift
|
||||
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
|
||||
if(phase < 0) begin
|
||||
phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
|
||||
end else begin
|
||||
phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
|
||||
end
|
||||
|
||||
// Put phase in terms of decimal number of vco clock cycles
|
||||
phase_in_cycles = ( phase_fixed * divide ) / 360;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("phase_in_cycles: %h", phase_in_cycles);
|
||||
`endif
|
||||
|
||||
|
||||
temp = round_frac(phase_in_cycles, 3);
|
||||
|
||||
// set mx to 2'b00 that the phase mux from the VCO is enabled
|
||||
mx = 2'b00;
|
||||
phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
|
||||
delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("temp: %h", temp);
|
||||
`endif
|
||||
|
||||
// Setup the return value
|
||||
mmcm_pll_phase={mx, phase_mux, delay_time};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and outputs the necessary lock values
|
||||
function [39:0] mmcm_pll_lock_lookup
|
||||
(
|
||||
input [6:0] divide // Max divide is 64
|
||||
);
|
||||
|
||||
reg [2559:0] lookup;
|
||||
|
||||
begin
|
||||
lookup = {
|
||||
// This table is composed of:
|
||||
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
|
||||
40'b00110_00110_1111101000_1111101001_0000000001,
|
||||
40'b00110_00110_1111101000_1111101001_0000000001,
|
||||
40'b01000_01000_1111101000_1111101001_0000000001,
|
||||
40'b01011_01011_1111101000_1111101001_0000000001,
|
||||
40'b01110_01110_1111101000_1111101001_0000000001,
|
||||
40'b10001_10001_1111101000_1111101001_0000000001,
|
||||
40'b10011_10011_1111101000_1111101001_0000000001,
|
||||
40'b10110_10110_1111101000_1111101001_0000000001,
|
||||
40'b11001_11001_1111101000_1111101001_0000000001,
|
||||
40'b11100_11100_1111101000_1111101001_0000000001,
|
||||
40'b11111_11111_1110000100_1111101001_0000000001,
|
||||
40'b11111_11111_1100111001_1111101001_0000000001,
|
||||
40'b11111_11111_1011101110_1111101001_0000000001,
|
||||
40'b11111_11111_1010111100_1111101001_0000000001,
|
||||
40'b11111_11111_1010001010_1111101001_0000000001,
|
||||
40'b11111_11111_1001110001_1111101001_0000000001,
|
||||
40'b11111_11111_1000111111_1111101001_0000000001,
|
||||
40'b11111_11111_1000100110_1111101001_0000000001,
|
||||
40'b11111_11111_1000001101_1111101001_0000000001,
|
||||
40'b11111_11111_0111110100_1111101001_0000000001,
|
||||
40'b11111_11111_0111011011_1111101001_0000000001,
|
||||
40'b11111_11111_0111000010_1111101001_0000000001,
|
||||
40'b11111_11111_0110101001_1111101001_0000000001,
|
||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
||||
40'b11111_11111_0101110111_1111101001_0000000001,
|
||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
|
||||
`ifdef DEBUG
|
||||
$display("lock_lookup: %b", mmcm_pll_lock_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and the bandwidth setting of the MMCM
|
||||
// and outputs the digital filter settings necessary.
|
||||
function [9:0] mmcm_pll_filter_lookup
|
||||
(
|
||||
input [6:0] divide, // Max divide is 64
|
||||
input [8*9:0] BANDWIDTH
|
||||
);
|
||||
|
||||
reg [639:0] lookup_low;
|
||||
reg [639:0] lookup_high;
|
||||
|
||||
reg [9:0] lookup_entry;
|
||||
|
||||
begin
|
||||
lookup_low = {
|
||||
// CP_RES_LFHF
|
||||
10'b0010_1111_00,
|
||||
10'b0010_1111_00,
|
||||
10'b0010_1111_00,
|
||||
10'b0010_1111_00,
|
||||
10'b0010_0111_00,
|
||||
10'b0010_1011_00,
|
||||
10'b0010_1101_00,
|
||||
10'b0010_0011_00,
|
||||
10'b0010_0101_00,
|
||||
10'b0010_0101_00,
|
||||
10'b0010_1001_00,
|
||||
10'b0010_1110_00,
|
||||
10'b0010_1110_00,
|
||||
10'b0010_1110_00,
|
||||
10'b0010_1110_00,
|
||||
10'b0010_0001_00,
|
||||
10'b0010_0001_00,
|
||||
10'b0010_0001_00,
|
||||
10'b0010_0110_00,
|
||||
10'b0010_0110_00,
|
||||
10'b0010_0110_00,
|
||||
10'b0010_0110_00,
|
||||
10'b0010_0110_00,
|
||||
10'b0010_0110_00,
|
||||
10'b0010_0110_00,
|
||||
10'b0010_1010_00,
|
||||
10'b0010_1010_00,
|
||||
10'b0010_1010_00,
|
||||
10'b0010_1010_00,
|
||||
10'b0010_1010_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00
|
||||
};
|
||||
|
||||
lookup_high = {
|
||||
// CP_RES_LFHF
|
||||
10'b0010_1111_00,
|
||||
10'b0100_1111_00,
|
||||
10'b0101_1011_00,
|
||||
10'b0111_0111_00,
|
||||
10'b1101_0111_00,
|
||||
10'b1110_1011_00,
|
||||
10'b1110_1101_00,
|
||||
10'b1111_0011_00,
|
||||
10'b1110_0101_00,
|
||||
10'b1111_0101_00,
|
||||
10'b1111_1001_00,
|
||||
10'b1101_0001_00,
|
||||
10'b1111_1001_00,
|
||||
10'b1111_1001_00,
|
||||
10'b1111_1001_00,
|
||||
10'b1111_1001_00,
|
||||
10'b1111_0101_00,
|
||||
10'b1111_0101_00,
|
||||
10'b1100_0001_00,
|
||||
10'b1100_0001_00,
|
||||
10'b1100_0001_00,
|
||||
10'b0101_1100_00,
|
||||
10'b0101_1100_00,
|
||||
10'b0101_1100_00,
|
||||
10'b0101_1100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0111_0001_00,
|
||||
10'b0111_0001_00,
|
||||
10'b0100_1100_00,
|
||||
10'b0100_1100_00,
|
||||
10'b0100_1100_00,
|
||||
10'b0100_1100_00,
|
||||
10'b0110_0001_00,
|
||||
10'b0110_0001_00,
|
||||
10'b0101_0110_00,
|
||||
10'b0101_0110_00,
|
||||
10'b0101_0110_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0100_1010_00,
|
||||
10'b0011_1100_00,
|
||||
10'b0011_1100_00
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
if(BANDWIDTH == "LOW") begin
|
||||
// Low Bandwidth
|
||||
mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
|
||||
end else begin
|
||||
// High or optimized bandwidth
|
||||
mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
|
||||
end
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("filter_lookup: %b", mmcm_pll_filter_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle
|
||||
// setting to calculate the upper and lower counter registers.
|
||||
function [37:0] mmcm_pll_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle // Multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
|
||||
div_calc = mmcm_pll_divider(divide, duty_cycle);
|
||||
// mx[10:9], pm[8:6], dt[5:0]
|
||||
phase_calc = mmcm_pll_phase(divide, phase);
|
||||
|
||||
// Return value is the upper and lower address of counter
|
||||
// Upper address is:
|
||||
// RESERVED [31:26]
|
||||
// MX [25:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
|
||||
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
|
||||
div_calc[13], div_calc[12],
|
||||
phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
|
||||
`endif
|
||||
|
||||
mmcm_pll_count_calc =
|
||||
{
|
||||
// Upper Address
|
||||
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
|
||||
// Lower Address
|
||||
phase_calc[8:6], 1'b0, div_calc[11:0]
|
||||
};
|
||||
end
|
||||
endfunction
|
||||
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle
|
||||
// setting to calculate the upper and lower counter registers.
|
||||
// for fractional multiply/divide functions.
|
||||
//
|
||||
//
|
||||
function [37:0] mmcm_frac_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle, // Multiplied by 1,000
|
||||
input [9:0] frac // Multiplied by 1000
|
||||
);
|
||||
|
||||
//Required for fractional divide calculations
|
||||
reg [7:0] lt_frac;
|
||||
reg [7:0] ht_frac;
|
||||
|
||||
reg /*[7:0]*/ wf_fall_frac;
|
||||
reg /*[7:0]*/ wf_rise_frac;
|
||||
|
||||
reg [31:0] a;
|
||||
reg [7:0] pm_rise_frac_filtered ;
|
||||
reg [7:0] pm_fall_frac_filtered ;
|
||||
reg [7:0] clkout0_divide_int;
|
||||
reg [2:0] clkout0_divide_frac;
|
||||
reg [7:0] even_part_high;
|
||||
reg [7:0] even_part_low;
|
||||
|
||||
reg [7:0] odd;
|
||||
reg [7:0] odd_and_frac;
|
||||
|
||||
reg [7:0] pm_fall;
|
||||
reg [7:0] pm_rise;
|
||||
reg [7:0] dt;
|
||||
reg [7:0] dt_int;
|
||||
reg [63:0] dt_calc;
|
||||
|
||||
reg [7:0] pm_rise_frac;
|
||||
reg [7:0] pm_fall_frac;
|
||||
|
||||
reg [31:0] a_per_in_octets;
|
||||
reg [31:0] a_phase_in_cycles;
|
||||
|
||||
parameter precision = 0.125;
|
||||
|
||||
reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
|
||||
reg [31: 0] phase_pos;
|
||||
reg [31: 0] phase_vco;
|
||||
reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
//convert phase to fixed
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
|
||||
// Return value is
|
||||
// Transfer data
|
||||
// RESERVED [37:36]
|
||||
// FRAC_TIME [35:33]
|
||||
// FRAC_WF_FALL [32]
|
||||
// Upper address is:
|
||||
// RESERVED [31:26]
|
||||
// MX [25:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
|
||||
|
||||
clkout0_divide_frac = frac / 125;
|
||||
clkout0_divide_int = divide;
|
||||
|
||||
even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
|
||||
even_part_low = even_part_high;
|
||||
|
||||
odd = clkout0_divide_int - even_part_high - even_part_low;
|
||||
odd_and_frac = (8*odd) + clkout0_divide_frac;
|
||||
|
||||
lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
|
||||
ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
|
||||
|
||||
pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
|
||||
pm_rise = 0; //0
|
||||
|
||||
wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
|
||||
wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
|
||||
|
||||
|
||||
|
||||
//Calculate phase in fractional cycles
|
||||
a_per_in_octets = (8 * divide) + (frac / 125) ;
|
||||
a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
|
||||
pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
|
||||
|
||||
dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
|
||||
dt = dt_calc[7:0];
|
||||
|
||||
pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
|
||||
|
||||
dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
|
||||
pm_fall_frac = pm_fall + pm_rise_frac;
|
||||
pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
|
||||
|
||||
div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
|
||||
phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
|
||||
|
||||
mmcm_frac_count_calc[37:0] =
|
||||
{ 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
|
||||
1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
|
||||
pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
|
||||
} ;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
|
||||
`endif
|
||||
|
||||
end
|
||||
endfunction
|
||||
|
||||
@ -1,531 +0,0 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Company: Xilinx
|
||||
// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing
|
||||
// Date: 7/30/2014
|
||||
// Design Name: PLLE2 DRP
|
||||
// Module Name: plle2_drp_func.h
|
||||
// Version: 2.00
|
||||
// Target Devices: 7 Series || PLL
|
||||
// Tool versions: 2014.3
|
||||
// Description: This header provides the functions necessary to
|
||||
// calculate the DRP register values for the V6 PLL.
|
||||
// Updated for CR663854.
|
||||
//
|
||||
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
|
||||
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
|
||||
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
|
||||
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
||||
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
|
||||
// APPLICATION OR STANDARD, XILINX IS MAKING NO
|
||||
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
|
||||
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
|
||||
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
|
||||
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
|
||||
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
|
||||
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
|
||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
// PURPOSE.
|
||||
//
|
||||
// (c) Copyright 2009-2010 Xilinx, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// These are user functions that should not be modified. Changes to the defines
|
||||
// or code within the functions may alter the accuracy of the calculations.
|
||||
|
||||
// Define debug to provide extra messages durring elaboration
|
||||
//`define DEBUG 1
|
||||
|
||||
// FRAC_PRECISION describes the width of the fractional portion of the fixed
|
||||
// point numbers. These should not be modified, they are for development
|
||||
// only
|
||||
`define FRAC_PRECISION 10
|
||||
// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
|
||||
// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
|
||||
// greater than 32
|
||||
`define FIXED_WIDTH 32
|
||||
|
||||
// This function takes a fixed point number and rounds it to the nearest
|
||||
// fractional precision bit.
|
||||
function [`FIXED_WIDTH:1] round_frac
|
||||
(
|
||||
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
|
||||
input [`FIXED_WIDTH:1] decimal,
|
||||
|
||||
// This describes the precision of the fraction, for example a value
|
||||
// of 1 would modify the fractional so that instead of being a .16
|
||||
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
|
||||
input [`FIXED_WIDTH:1] precision
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("round_frac - decimal: %h, precision: %h", decimal, precision);
|
||||
`endif
|
||||
// If the fractional precision bit is high then round up
|
||||
if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
|
||||
round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
|
||||
end else begin
|
||||
round_frac = decimal;
|
||||
end
|
||||
`ifdef DEBUG
|
||||
$display("round_frac: %h", round_frac);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates high_time, low_time, w_edge, and no_count
|
||||
// of a non-fractional counter based on the divide and duty cycle
|
||||
//
|
||||
// NOTE: high_time and low_time are returned as integers between 0 and 63
|
||||
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
|
||||
// ignore the overflow)
|
||||
function [13:0] mmcm_pll_divider
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] duty_cycle_fix;
|
||||
|
||||
// High/Low time is initially calculated with a wider integer to prevent a
|
||||
// calculation error when it overflows to 64.
|
||||
reg [6:0] high_time;
|
||||
reg [6:0] low_time;
|
||||
reg w_edge;
|
||||
reg no_count;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
// Duty Cycle must be between 0 and 1,000
|
||||
if(duty_cycle <=0 || duty_cycle >= 100000) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
|
||||
duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("duty_cycle_fix: %h", duty_cycle_fix);
|
||||
`endif
|
||||
|
||||
// If the divide is 1 nothing needs to be set except the no_count bit.
|
||||
// Other values are dummies
|
||||
if(divide == 7'h01) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
low_time = 7'h01;
|
||||
no_count = 1'b1;
|
||||
end else begin
|
||||
temp = round_frac(duty_cycle_fix*divide, 1);
|
||||
|
||||
// comes from above round_frac
|
||||
high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
|
||||
// If the duty cycle * divide rounded is .5 or greater then this bit
|
||||
// is set.
|
||||
w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
|
||||
|
||||
// If the high time comes out to 0, it needs to be set to at least 1
|
||||
// and w_edge set to 0
|
||||
if(high_time == 7'h00) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
end
|
||||
|
||||
if(high_time == divide) begin
|
||||
high_time = divide - 1;
|
||||
w_edge = 1'b1;
|
||||
end
|
||||
|
||||
// Calculate low_time based on the divide setting and set no_count to
|
||||
// 0 as it is only used when divide is 1.
|
||||
low_time = divide - high_time;
|
||||
no_count = 1'b0;
|
||||
end
|
||||
|
||||
// Set the return value.
|
||||
mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates mx, delay_time, and phase_mux
|
||||
// of a non-fractional counter based on the divide and phase
|
||||
//
|
||||
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
|
||||
// is used.
|
||||
function [10:0] mmcm_pll_phase
|
||||
(
|
||||
// divide must be an integer (use fractional if not)
|
||||
// assumed that divide already checked to be valid
|
||||
input [7:0] divide, // Max divide is 128
|
||||
|
||||
// Phase is given in degrees (-360,000 to 360,000)
|
||||
input signed [31:0] phase
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] phase_in_cycles;
|
||||
reg [`FIXED_WIDTH:1] phase_fixed;
|
||||
reg [1:0] mx;
|
||||
reg [5:0] delay_time;
|
||||
reg [2:0] phase_mux;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_pll_phase-divide:%d,phase:%d",
|
||||
divide, phase);
|
||||
`endif
|
||||
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// If phase is less than 0, convert it to a positive phase shift
|
||||
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
|
||||
if(phase < 0) begin
|
||||
phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
|
||||
end else begin
|
||||
phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
|
||||
end
|
||||
|
||||
// Put phase in terms of decimal number of vco clock cycles
|
||||
phase_in_cycles = ( phase_fixed * divide ) / 360;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("phase_in_cycles: %h", phase_in_cycles);
|
||||
`endif
|
||||
|
||||
|
||||
temp = round_frac(phase_in_cycles, 3);
|
||||
|
||||
// set mx to 2'b00 that the phase mux from the VCO is enabled
|
||||
mx = 2'b00;
|
||||
phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
|
||||
delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("temp: %h", temp);
|
||||
`endif
|
||||
|
||||
// Setup the return value
|
||||
mmcm_pll_phase={mx, phase_mux, delay_time};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and outputs the necessary lock values
|
||||
function [39:0] mmcm_pll_lock_lookup
|
||||
(
|
||||
input [6:0] divide // Max divide is 64
|
||||
);
|
||||
|
||||
reg [2559:0] lookup;
|
||||
|
||||
begin
|
||||
lookup = {
|
||||
// This table is composed of:
|
||||
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
|
||||
40'b00110_00110_1111101000_1111101001_0000000001,
|
||||
40'b00110_00110_1111101000_1111101001_0000000001,
|
||||
40'b01000_01000_1111101000_1111101001_0000000001,
|
||||
40'b01011_01011_1111101000_1111101001_0000000001,
|
||||
40'b01110_01110_1111101000_1111101001_0000000001,
|
||||
40'b10001_10001_1111101000_1111101001_0000000001,
|
||||
40'b10011_10011_1111101000_1111101001_0000000001,
|
||||
40'b10110_10110_1111101000_1111101001_0000000001,
|
||||
40'b11001_11001_1111101000_1111101001_0000000001,
|
||||
40'b11100_11100_1111101000_1111101001_0000000001,
|
||||
40'b11111_11111_1110000100_1111101001_0000000001,
|
||||
40'b11111_11111_1100111001_1111101001_0000000001,
|
||||
40'b11111_11111_1011101110_1111101001_0000000001,
|
||||
40'b11111_11111_1010111100_1111101001_0000000001,
|
||||
40'b11111_11111_1010001010_1111101001_0000000001,
|
||||
40'b11111_11111_1001110001_1111101001_0000000001,
|
||||
40'b11111_11111_1000111111_1111101001_0000000001,
|
||||
40'b11111_11111_1000100110_1111101001_0000000001,
|
||||
40'b11111_11111_1000001101_1111101001_0000000001,
|
||||
40'b11111_11111_0111110100_1111101001_0000000001,
|
||||
40'b11111_11111_0111011011_1111101001_0000000001,
|
||||
40'b11111_11111_0111000010_1111101001_0000000001,
|
||||
40'b11111_11111_0110101001_1111101001_0000000001,
|
||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
||||
40'b11111_11111_0101110111_1111101001_0000000001,
|
||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
|
||||
`ifdef DEBUG
|
||||
$display("lock_lookup: %b", mmcm_pll_lock_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and the bandwidth setting of the PLL
|
||||
// and outputs the digital filter settings necessary.
|
||||
function [9:0] mmcm_pll_filter_lookup
|
||||
(
|
||||
input [6:0] divide, // Max divide is 64
|
||||
input [8*9:0] BANDWIDTH
|
||||
);
|
||||
|
||||
reg [639:0] lookup_low;
|
||||
reg [639:0] lookup_high;
|
||||
|
||||
reg [9:0] lookup_entry;
|
||||
|
||||
begin
|
||||
lookup_low = {
|
||||
// CP_RES_LFHF
|
||||
10'b0010_1111_00,
|
||||
10'b0010_1111_00,
|
||||
10'b0010_0111_00,
|
||||
10'b0010_1101_00,
|
||||
10'b0010_0101_00,
|
||||
10'b0010_0101_00,
|
||||
10'b0010_1001_00,
|
||||
10'b0010_1110_00,
|
||||
10'b0010_1110_00,
|
||||
10'b0010_0001_00,
|
||||
10'b0010_0001_00,
|
||||
10'b0010_0110_00,
|
||||
10'b0010_0110_00,
|
||||
10'b0010_0110_00,
|
||||
10'b0010_0110_00,
|
||||
10'b0010_1010_00,
|
||||
10'b0010_1010_00,
|
||||
10'b0010_1010_00,
|
||||
10'b0010_1010_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0011_1100_00,
|
||||
10'b0011_1100_00,
|
||||
10'b0011_1100_00,
|
||||
10'b0011_1100_00,
|
||||
10'b0011_1100_00,
|
||||
10'b0011_1100_00,
|
||||
10'b0011_1100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00
|
||||
};
|
||||
|
||||
lookup_high = {
|
||||
// CP_RES_LFHF
|
||||
10'b0011_0111_00,
|
||||
10'b0011_0111_00,
|
||||
10'b0101_1111_00,
|
||||
10'b0111_1111_00,
|
||||
10'b0111_1011_00,
|
||||
10'b1101_0111_00,
|
||||
10'b1110_1011_00,
|
||||
10'b1110_1101_00,
|
||||
10'b1111_1101_00,
|
||||
10'b1111_0111_00,
|
||||
10'b1111_1011_00,
|
||||
10'b1111_1101_00,
|
||||
10'b1111_0011_00,
|
||||
10'b1110_0101_00,
|
||||
10'b1111_0101_00,
|
||||
10'b1111_0101_00,
|
||||
10'b1111_0101_00,
|
||||
10'b1111_0101_00,
|
||||
10'b0111_0110_00,
|
||||
10'b0111_0110_00,
|
||||
10'b0111_0110_00,
|
||||
10'b0111_0110_00,
|
||||
10'b0101_1100_00,
|
||||
10'b0101_1100_00,
|
||||
10'b0101_1100_00,
|
||||
10'b1100_0001_00,
|
||||
10'b1100_0001_00,
|
||||
10'b1100_0001_00,
|
||||
10'b1100_0001_00,
|
||||
10'b1100_0001_00,
|
||||
10'b1100_0001_00,
|
||||
10'b1100_0001_00,
|
||||
10'b1100_0001_00,
|
||||
10'b0100_0010_00,
|
||||
10'b0100_0010_00,
|
||||
10'b0100_0010_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0100_1100_00,
|
||||
10'b0100_1100_00,
|
||||
10'b0100_1100_00,
|
||||
10'b0100_1100_00,
|
||||
10'b0100_1100_00,
|
||||
10'b0100_1100_00,
|
||||
10'b0100_1100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
if(BANDWIDTH == "LOW") begin
|
||||
// Low Bandwidth
|
||||
mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
|
||||
end else begin
|
||||
// High or optimized bandwidth
|
||||
mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
|
||||
end
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("filter_lookup: %b", mmcm_pll_filter_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle
|
||||
// setting to calculate the upper and lower counter registers.
|
||||
function [37:0] mmcm_pll_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle // Multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
|
||||
div_calc = mmcm_pll_divider(divide, duty_cycle);
|
||||
// mx[10:9], pm[8:6], dt[5:0]
|
||||
phase_calc = mmcm_pll_phase(divide, phase);
|
||||
|
||||
// Return value is the upper and lower address of counter
|
||||
// Upper address is:
|
||||
// RESERVED [31:26]
|
||||
// MX [25:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
|
||||
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
|
||||
div_calc[13], div_calc[12],
|
||||
phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
|
||||
`endif
|
||||
|
||||
mmcm_pll_count_calc =
|
||||
{
|
||||
// Upper Address
|
||||
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
|
||||
// Lower Address
|
||||
phase_calc[8:6], 1'b0, div_calc[11:0]
|
||||
};
|
||||
end
|
||||
endfunction
|
||||
@ -1,671 +0,0 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Company: Xilinx
|
||||
// Engineer: Jim Tatsukawa
|
||||
// Date: 7/30/2014
|
||||
// Design Name: MMCME2 DRP
|
||||
// Module Name: mmcme2_drp_func.h
|
||||
// Version: 1.04
|
||||
// Target Devices: UltraScale Architecture || MMCM
|
||||
// Tool versions: 2014.3
|
||||
// Description: This header provides the functions necessary to
|
||||
// calculate the DRP register values for the V6 MMCM.
|
||||
//
|
||||
// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR)
|
||||
// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807
|
||||
//
|
||||
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
|
||||
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
|
||||
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
|
||||
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
||||
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
|
||||
// APPLICATION OR STANDARD, XILINX IS MAKING NO
|
||||
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
|
||||
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
|
||||
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
|
||||
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
|
||||
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
|
||||
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
|
||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
// PURPOSE.
|
||||
//
|
||||
// (c) Copyright 2009-2010 Xilinx, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// These are user functions that should not be modified. Changes to the defines
|
||||
// or code within the functions may alter the accuracy of the calculations.
|
||||
|
||||
// Define debug to provide extra messages durring elaboration
|
||||
//`define DEBUG 1
|
||||
|
||||
// FRAC_PRECISION describes the width of the fractional portion of the fixed
|
||||
// point numbers. These should not be modified, they are for development
|
||||
// only
|
||||
`define FRAC_PRECISION 10
|
||||
// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
|
||||
// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
|
||||
// greater than 32
|
||||
`define FIXED_WIDTH 32
|
||||
|
||||
// This function takes a fixed point number and rounds it to the nearest
|
||||
// fractional precision bit.
|
||||
function [`FIXED_WIDTH:1] round_frac
|
||||
(
|
||||
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
|
||||
input [`FIXED_WIDTH:1] decimal,
|
||||
|
||||
// This describes the precision of the fraction, for example a value
|
||||
// of 1 would modify the fractional so that instead of being a .16
|
||||
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
|
||||
input [`FIXED_WIDTH:1] precision
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("round_frac - decimal: %h, precision: %h", decimal, precision);
|
||||
`endif
|
||||
// If the fractional precision bit is high then round up
|
||||
if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
|
||||
round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
|
||||
end else begin
|
||||
round_frac = decimal;
|
||||
end
|
||||
`ifdef DEBUG
|
||||
$display("round_frac: %h", round_frac);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates high_time, low_time, w_edge, and no_count
|
||||
// of a non-fractional counter based on the divide and duty cycle
|
||||
//
|
||||
// NOTE: high_time and low_time are returned as integers between 0 and 63
|
||||
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
|
||||
// ignore the overflow)
|
||||
function [13:0] mmcm_pll_divider
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] duty_cycle_fix;
|
||||
|
||||
// High/Low time is initially calculated with a wider integer to prevent a
|
||||
// calculation error when it overflows to 64.
|
||||
reg [6:0] high_time;
|
||||
reg [6:0] low_time;
|
||||
reg w_edge;
|
||||
reg no_count;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
// Duty Cycle must be between 0 and 1,000
|
||||
if(duty_cycle <=0 || duty_cycle >= 100000) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
|
||||
duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("duty_cycle_fix: %h", duty_cycle_fix);
|
||||
`endif
|
||||
|
||||
// If the divide is 1 nothing needs to be set except the no_count bit.
|
||||
// Other values are dummies
|
||||
if(divide == 7'h01) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
low_time = 7'h01;
|
||||
no_count = 1'b1;
|
||||
end else begin
|
||||
temp = round_frac(duty_cycle_fix*divide, 1);
|
||||
|
||||
// comes from above round_frac
|
||||
high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
|
||||
// If the duty cycle * divide rounded is .5 or greater then this bit
|
||||
// is set.
|
||||
w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
|
||||
|
||||
// If the high time comes out to 0, it needs to be set to at least 1
|
||||
// and w_edge set to 0
|
||||
if(high_time == 7'h00) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
end
|
||||
|
||||
if(high_time == divide) begin
|
||||
high_time = divide - 1;
|
||||
w_edge = 1'b1;
|
||||
end
|
||||
|
||||
// Calculate low_time based on the divide setting and set no_count to
|
||||
// 0 as it is only used when divide is 1.
|
||||
low_time = divide - high_time;
|
||||
no_count = 1'b0;
|
||||
end
|
||||
|
||||
// Set the return value.
|
||||
mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates mx, delay_time, and phase_mux
|
||||
// of a non-fractional counter based on the divide and phase
|
||||
//
|
||||
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
|
||||
// is used.
|
||||
function [10:0] mmcm_pll_phase
|
||||
(
|
||||
// divide must be an integer (use fractional if not)
|
||||
// assumed that divide already checked to be valid
|
||||
input [7:0] divide, // Max divide is 128
|
||||
|
||||
// Phase is given in degrees (-360,000 to 360,000)
|
||||
input signed [31:0] phase
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] phase_in_cycles;
|
||||
reg [`FIXED_WIDTH:1] phase_fixed;
|
||||
reg [1:0] mx;
|
||||
reg [5:0] delay_time;
|
||||
reg [2:0] phase_mux;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_pll_phase-divide:%d,phase:%d",
|
||||
divide, phase);
|
||||
`endif
|
||||
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// If phase is less than 0, convert it to a positive phase shift
|
||||
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
|
||||
if(phase < 0) begin
|
||||
phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
|
||||
end else begin
|
||||
phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
|
||||
end
|
||||
|
||||
// Put phase in terms of decimal number of vco clock cycles
|
||||
phase_in_cycles = ( phase_fixed * divide ) / 360;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("phase_in_cycles: %h", phase_in_cycles);
|
||||
`endif
|
||||
|
||||
|
||||
temp = round_frac(phase_in_cycles, 3);
|
||||
|
||||
// set mx to 2'b00 that the phase mux from the VCO is enabled
|
||||
mx = 2'b00;
|
||||
phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
|
||||
delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("temp: %h", temp);
|
||||
`endif
|
||||
|
||||
// Setup the return value
|
||||
mmcm_pll_phase={mx, phase_mux, delay_time};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and outputs the necessary lock values
|
||||
function [39:0] mmcm_pll_lock_lookup
|
||||
(
|
||||
input [6:0] divide // Max divide is 64
|
||||
);
|
||||
|
||||
reg [2559:0] lookup;
|
||||
|
||||
begin
|
||||
lookup = {
|
||||
// This table is composed of:
|
||||
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
|
||||
40'b00110_00110_1111101000_1111101001_0000000001,
|
||||
40'b00110_00110_1111101000_1111101001_0000000001,
|
||||
40'b01000_01000_1111101000_1111101001_0000000001,
|
||||
40'b01011_01011_1111101000_1111101001_0000000001,
|
||||
40'b01110_01110_1111101000_1111101001_0000000001,
|
||||
40'b10001_10001_1111101000_1111101001_0000000001,
|
||||
40'b10011_10011_1111101000_1111101001_0000000001,
|
||||
40'b10110_10110_1111101000_1111101001_0000000001,
|
||||
40'b11001_11001_1111101000_1111101001_0000000001,
|
||||
40'b11100_11100_1111101000_1111101001_0000000001,
|
||||
40'b11111_11111_1110000100_1111101001_0000000001,
|
||||
40'b11111_11111_1100111001_1111101001_0000000001,
|
||||
40'b11111_11111_1011101110_1111101001_0000000001,
|
||||
40'b11111_11111_1010111100_1111101001_0000000001,
|
||||
40'b11111_11111_1010001010_1111101001_0000000001,
|
||||
40'b11111_11111_1001110001_1111101001_0000000001,
|
||||
40'b11111_11111_1000111111_1111101001_0000000001,
|
||||
40'b11111_11111_1000100110_1111101001_0000000001,
|
||||
40'b11111_11111_1000001101_1111101001_0000000001,
|
||||
40'b11111_11111_0111110100_1111101001_0000000001,
|
||||
40'b11111_11111_0111011011_1111101001_0000000001,
|
||||
40'b11111_11111_0111000010_1111101001_0000000001,
|
||||
40'b11111_11111_0110101001_1111101001_0000000001,
|
||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
||||
40'b11111_11111_0101110111_1111101001_0000000001,
|
||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
|
||||
`ifdef DEBUG
|
||||
$display("lock_lookup: %b", mmcm_pll_lock_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and the bandwidth setting of the MMCM
|
||||
// and outputs the digital filter settings necessary.
|
||||
function [9:0] mmcm_pll_filter_lookup
|
||||
(
|
||||
input [6:0] divide, // Max divide is 64
|
||||
input [8*9:0] BANDWIDTH
|
||||
);
|
||||
|
||||
reg [639:0] lookup_low;
|
||||
reg [639:0] lookup_high;
|
||||
|
||||
reg [9:0] lookup_entry;
|
||||
|
||||
begin
|
||||
lookup_low = {
|
||||
// CP_RES_LFHF
|
||||
10'b0010_1111_11,
|
||||
10'b0010_1111_11,
|
||||
10'b0010_1111_11,
|
||||
10'b0010_1111_11,
|
||||
10'b0010_1111_11,
|
||||
10'b0010_1111_11,
|
||||
10'b0010_0111_11,
|
||||
10'b0010_0111_11,
|
||||
10'b0010_0111_11,
|
||||
10'b0010_1101_11,
|
||||
10'b0010_1101_11,
|
||||
10'b0010_1101_11,
|
||||
10'b0010_0011_11,
|
||||
10'b0010_0101_11,
|
||||
10'b0010_0101_11,
|
||||
10'b0010_0101_11,
|
||||
10'b0010_1001_11,
|
||||
10'b0010_1001_11,
|
||||
10'b0010_1110_11,
|
||||
10'b0010_1110_11,
|
||||
10'b0010_1110_11,
|
||||
10'b0010_1110_11,
|
||||
10'b0010_1110_11,
|
||||
10'b0010_1110_11,
|
||||
10'b0010_0001_11,
|
||||
10'b0010_0001_11,
|
||||
10'b0010_0001_11,
|
||||
10'b0010_0001_11,
|
||||
10'b0010_0001_11,
|
||||
10'b0010_0110_11,
|
||||
10'b0010_0110_11,
|
||||
10'b0010_0110_11,
|
||||
10'b0010_0110_11,
|
||||
10'b0010_0110_11,
|
||||
10'b0010_0110_11,
|
||||
10'b0010_0110_11,
|
||||
10'b0010_0110_11,
|
||||
10'b0010_0110_11,
|
||||
10'b0010_0110_11,
|
||||
10'b0010_1010_11,
|
||||
10'b0010_1010_11,
|
||||
10'b0010_1010_11,
|
||||
10'b0010_1010_11,
|
||||
10'b0010_1010_11,
|
||||
10'b0010_1010_11,
|
||||
10'b0010_1010_11,
|
||||
10'b0010_1010_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11
|
||||
};
|
||||
|
||||
lookup_high = {
|
||||
// CP_RES_LFHF
|
||||
10'b0010_1111_11,
|
||||
10'b0010_1111_11,
|
||||
10'b0010_1011_11,
|
||||
10'b0011_1111_11,
|
||||
10'b0100_1111_11,
|
||||
10'b0100_1111_11,
|
||||
10'b0101_1111_11,
|
||||
10'b0110_1111_11,
|
||||
10'b0111_1111_11,
|
||||
10'b0111_1111_11,
|
||||
10'b1100_1111_11,
|
||||
10'b1101_1111_11,
|
||||
10'b1110_1111_11,
|
||||
10'b1111_1111_11,
|
||||
10'b1111_1111_11,
|
||||
10'b1110_0111_11,
|
||||
10'b1110_1011_11,
|
||||
10'b1111_0111_11,
|
||||
10'b1111_1011_11,
|
||||
10'b1111_1011_11,
|
||||
10'b1110_1101_11,
|
||||
10'b1111_1101_11,
|
||||
10'b1111_1101_11,
|
||||
10'b1111_0011_11,
|
||||
10'b1111_0011_11,
|
||||
10'b1111_0011_11,
|
||||
10'b1110_0101_11,
|
||||
10'b1110_0101_11,
|
||||
10'b1110_0101_11,
|
||||
10'b1111_0101_11,
|
||||
10'b1111_0101_11,
|
||||
10'b1111_0101_11,
|
||||
10'b1111_1001_11,
|
||||
10'b1111_1001_11,
|
||||
10'b1111_1001_11,
|
||||
10'b1111_1001_11,
|
||||
10'b1111_1001_11,
|
||||
10'b1110_1110_11,
|
||||
10'b1110_1110_11,
|
||||
10'b1110_1110_11,
|
||||
10'b1110_1110_11,
|
||||
10'b1111_1110_11,
|
||||
10'b1111_1110_11,
|
||||
10'b1111_1110_11,
|
||||
10'b1111_1110_11,
|
||||
10'b1111_1110_11,
|
||||
10'b1111_1110_11,
|
||||
10'b1111_1110_11,
|
||||
10'b1110_0001_11,
|
||||
10'b1110_0001_11,
|
||||
10'b1110_0001_11,
|
||||
10'b1110_0001_11,
|
||||
10'b1110_0001_11,
|
||||
10'b1100_0110_11,
|
||||
10'b1100_0110_11,
|
||||
10'b1100_0110_11,
|
||||
10'b1100_0110_11,
|
||||
10'b1100_0110_11,
|
||||
10'b1100_0110_11,
|
||||
10'b1100_0110_11,
|
||||
10'b1100_1010_11,
|
||||
10'b1100_1010_11,
|
||||
10'b1100_1010_11,
|
||||
10'b1100_1010_11
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
if(BANDWIDTH == "LOW") begin
|
||||
// Low Bandwidth
|
||||
mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
|
||||
end else begin
|
||||
// High or optimized bandwidth
|
||||
mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
|
||||
end
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("filter_lookup: %b", mmcm_pll_filter_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle
|
||||
// setting to calculate the upper and lower counter registers.
|
||||
function [37:0] mmcm_pll_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle // Multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
|
||||
div_calc = mmcm_pll_divider(divide, duty_cycle);
|
||||
// mx[10:9], pm[8:6], dt[5:0]
|
||||
phase_calc = mmcm_pll_phase(divide, phase);
|
||||
|
||||
// Return value is the upper and lower address of counter
|
||||
// Upper address is:
|
||||
// RESERVED [31:26]
|
||||
// MX [25:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
|
||||
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
|
||||
div_calc[13], div_calc[12],
|
||||
phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
|
||||
`endif
|
||||
|
||||
mmcm_pll_count_calc =
|
||||
{
|
||||
// Upper Address
|
||||
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
|
||||
// Lower Address
|
||||
phase_calc[8:6], 1'b0, div_calc[11:0]
|
||||
};
|
||||
end
|
||||
endfunction
|
||||
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle
|
||||
// setting to calculate the upper and lower counter registers.
|
||||
// for fractional multiply/divide functions.
|
||||
//
|
||||
//
|
||||
function [37:0] mmcm_frac_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle, // Multiplied by 1,000
|
||||
input [9:0] frac // Multiplied by 1000
|
||||
);
|
||||
|
||||
//Required for fractional divide calculations
|
||||
reg [7:0] lt_frac;
|
||||
reg [7:0] ht_frac;
|
||||
|
||||
reg /*[7:0]*/ wf_fall_frac;
|
||||
reg /*[7:0]*/ wf_rise_frac;
|
||||
|
||||
reg [31:0] a;
|
||||
reg [7:0] pm_rise_frac_filtered ;
|
||||
reg [7:0] pm_fall_frac_filtered ;
|
||||
reg [7:0] clkout0_divide_int;
|
||||
reg [2:0] clkout0_divide_frac;
|
||||
reg [7:0] even_part_high;
|
||||
reg [7:0] even_part_low;
|
||||
|
||||
reg [7:0] odd;
|
||||
reg [7:0] odd_and_frac;
|
||||
|
||||
reg [7:0] pm_fall;
|
||||
reg [7:0] pm_rise;
|
||||
reg [7:0] dt;
|
||||
reg [7:0] dt_int;
|
||||
reg [63:0] dt_calc;
|
||||
|
||||
reg [7:0] pm_rise_frac;
|
||||
reg [7:0] pm_fall_frac;
|
||||
|
||||
reg [31:0] a_per_in_octets;
|
||||
reg [31:0] a_phase_in_cycles;
|
||||
|
||||
parameter precision = 0.125;
|
||||
|
||||
reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
|
||||
reg [31: 0] phase_pos;
|
||||
reg [31: 0] phase_vco;
|
||||
reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
//convert phase to fixed
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
|
||||
// Return value is
|
||||
// Transfer data
|
||||
// RESERVED [37:36]
|
||||
// FRAC_TIME [35:33]
|
||||
// FRAC_WF_FALL [32]
|
||||
// Upper address is:
|
||||
// RESERVED [31:26]
|
||||
// MX [25:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
|
||||
|
||||
clkout0_divide_frac = frac / 125;
|
||||
clkout0_divide_int = divide;
|
||||
|
||||
even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
|
||||
even_part_low = even_part_high;
|
||||
|
||||
odd = clkout0_divide_int - even_part_high - even_part_low;
|
||||
odd_and_frac = (8*odd) + clkout0_divide_frac;
|
||||
|
||||
lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
|
||||
ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
|
||||
|
||||
pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
|
||||
pm_rise = 0; //0
|
||||
|
||||
wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
|
||||
wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
|
||||
|
||||
|
||||
|
||||
//Calculate phase in fractional cycles
|
||||
a_per_in_octets = (8 * divide) + (frac / 125) ;
|
||||
a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
|
||||
pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
|
||||
|
||||
dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
|
||||
dt = dt_calc[7:0];
|
||||
|
||||
pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
|
||||
|
||||
dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
|
||||
pm_fall_frac = pm_fall + pm_rise_frac;
|
||||
pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
|
||||
|
||||
div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
|
||||
phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
|
||||
|
||||
mmcm_frac_count_calc[37:0] =
|
||||
{ 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
|
||||
1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
|
||||
pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
|
||||
} ;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
|
||||
`endif
|
||||
|
||||
end
|
||||
endfunction
|
||||
|
||||
@ -1,530 +0,0 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Company: Xilinx
|
||||
// Engineer: Jim Tatsukawa
|
||||
// Date: 6/15/2015
|
||||
// Design Name: PLLE3 DRP
|
||||
// Module Name: plle3_drp_func.h
|
||||
// Version: 1.10
|
||||
// Target Devices: UltraScale Architecture
|
||||
// Tool versions: 2015.1
|
||||
// Description: This header provides the functions necessary to
|
||||
// calculate the DRP register values for the V6 PLL.
|
||||
//
|
||||
// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419
|
||||
// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19
|
||||
// PM_Rise bits have been removed for PLLE3
|
||||
//
|
||||
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
|
||||
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
|
||||
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
|
||||
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
||||
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
|
||||
// APPLICATION OR STANDARD, XILINX IS MAKING NO
|
||||
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
|
||||
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
|
||||
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
|
||||
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
|
||||
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
|
||||
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
|
||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
// PURPOSE.
|
||||
//
|
||||
// (c) Copyright 2009-2010 Xilinx, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// These are user functions that should not be modified. Changes to the defines
|
||||
// or code within the functions may alter the accuracy of the calculations.
|
||||
|
||||
// Define debug to provide extra messages durring elaboration
|
||||
//`define DEBUG 1
|
||||
|
||||
// FRAC_PRECISION describes the width of the fractional portion of the fixed
|
||||
// point numbers. These should not be modified, they are for development
|
||||
// only
|
||||
`define FRAC_PRECISION 10
|
||||
// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
|
||||
// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
|
||||
// greater than 32
|
||||
`define FIXED_WIDTH 32
|
||||
|
||||
// This function takes a fixed point number and rounds it to the nearest
|
||||
// fractional precision bit.
|
||||
function [`FIXED_WIDTH:1] round_frac
|
||||
(
|
||||
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
|
||||
input [`FIXED_WIDTH:1] decimal,
|
||||
|
||||
// This describes the precision of the fraction, for example a value
|
||||
// of 1 would modify the fractional so that instead of being a .16
|
||||
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
|
||||
input [`FIXED_WIDTH:1] precision
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("round_frac - decimal: %h, precision: %h", decimal, precision);
|
||||
`endif
|
||||
// If the fractional precision bit is high then round up
|
||||
if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
|
||||
round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
|
||||
end else begin
|
||||
round_frac = decimal;
|
||||
end
|
||||
`ifdef DEBUG
|
||||
$display("round_frac: %h", round_frac);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates high_time, low_time, w_edge, and no_count
|
||||
// of a non-fractional counter based on the divide and duty cycle
|
||||
//
|
||||
// NOTE: high_time and low_time are returned as integers between 0 and 63
|
||||
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
|
||||
// ignore the overflow)
|
||||
function [13:0] mmcm_pll_divider
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] duty_cycle_fix;
|
||||
|
||||
// High/Low time is initially calculated with a wider integer to prevent a
|
||||
// calculation error when it overflows to 64.
|
||||
reg [6:0] high_time;
|
||||
reg [6:0] low_time;
|
||||
reg w_edge;
|
||||
reg no_count;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
// Duty Cycle must be between 0 and 1,000
|
||||
if(duty_cycle <=0 || duty_cycle >= 100000) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
|
||||
duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("duty_cycle_fix: %h", duty_cycle_fix);
|
||||
`endif
|
||||
|
||||
// If the divide is 1 nothing needs to be set except the no_count bit.
|
||||
// Other values are dummies
|
||||
if(divide == 7'h01) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
low_time = 7'h01;
|
||||
no_count = 1'b1;
|
||||
end else begin
|
||||
temp = round_frac(duty_cycle_fix*divide, 1);
|
||||
|
||||
// comes from above round_frac
|
||||
high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
|
||||
// If the duty cycle * divide rounded is .5 or greater then this bit
|
||||
// is set.
|
||||
w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
|
||||
|
||||
// If the high time comes out to 0, it needs to be set to at least 1
|
||||
// and w_edge set to 0
|
||||
if(high_time == 7'h00) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
end
|
||||
|
||||
if(high_time == divide) begin
|
||||
high_time = divide - 1;
|
||||
w_edge = 1'b1;
|
||||
end
|
||||
|
||||
// Calculate low_time based on the divide setting and set no_count to
|
||||
// 0 as it is only used when divide is 1.
|
||||
low_time = divide - high_time;
|
||||
no_count = 1'b0;
|
||||
end
|
||||
|
||||
// Set the return value.
|
||||
mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates mx, delay_time, and phase_mux
|
||||
// of a non-fractional counter based on the divide and phase
|
||||
//
|
||||
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
|
||||
// is used.
|
||||
function [10:0] mmcm_pll_phase
|
||||
(
|
||||
// divide must be an integer (use fractional if not)
|
||||
// assumed that divide already checked to be valid
|
||||
input [7:0] divide, // Max divide is 128
|
||||
|
||||
// Phase is given in degrees (-360,000 to 360,000)
|
||||
input signed [31:0] phase
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] phase_in_cycles;
|
||||
reg [`FIXED_WIDTH:1] phase_fixed;
|
||||
reg [1:0] mx;
|
||||
reg [5:0] delay_time;
|
||||
reg [2:0] phase_mux;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_pll_phase-divide:%d,phase:%d",
|
||||
divide, phase);
|
||||
`endif
|
||||
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// If phase is less than 0, convert it to a positive phase shift
|
||||
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
|
||||
if(phase < 0) begin
|
||||
phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
|
||||
end else begin
|
||||
phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
|
||||
end
|
||||
|
||||
// Put phase in terms of decimal number of vco clock cycles
|
||||
phase_in_cycles = ( phase_fixed * divide ) / 360;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("phase_in_cycles: %h", phase_in_cycles);
|
||||
`endif
|
||||
|
||||
|
||||
temp = round_frac(phase_in_cycles, 3);
|
||||
|
||||
// set mx to 2'b00 that the phase mux from the VCO is enabled
|
||||
mx = 2'b00;
|
||||
phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
|
||||
delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("temp: %h", temp);
|
||||
`endif
|
||||
|
||||
// Setup the return value
|
||||
mmcm_pll_phase={mx, phase_mux, delay_time};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and outputs the necessary lock values
|
||||
function [39:0] mmcm_pll_lock_lookup
|
||||
(
|
||||
input [6:0] divide // Max divide is 64
|
||||
);
|
||||
|
||||
reg [759:0] lookup;
|
||||
|
||||
begin
|
||||
lookup = {
|
||||
// This table is composed of:
|
||||
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
|
||||
40'b00110_00110_1111101000_1111101001_0000000001, //1
|
||||
40'b00110_00110_1111101000_1111101001_0000000001, //2
|
||||
40'b01000_01000_1111101000_1111101001_0000000001, //3
|
||||
40'b01011_01011_1111101000_1111101001_0000000001, //4
|
||||
40'b01110_01110_1111101000_1111101001_0000000001, //5
|
||||
40'b10001_10001_1111101000_1111101001_0000000001, //6
|
||||
40'b10011_10011_1111101000_1111101001_0000000001, //7
|
||||
40'b10110_10110_1111101000_1111101001_0000000001, //8
|
||||
40'b11001_11001_1111101000_1111101001_0000000001, //9
|
||||
40'b11100_11100_1111101000_1111101001_0000000001, //10
|
||||
40'b11111_11111_1110000100_1111101001_0000000001, //11
|
||||
40'b11111_11111_1100111001_1111101001_0000000001, //12
|
||||
40'b11111_11111_1011101110_1111101001_0000000001, //13
|
||||
40'b11111_11111_1010111100_1111101001_0000000001, //14
|
||||
40'b11111_11111_1010001010_1111101001_0000000001, //15
|
||||
40'b11111_11111_1001110001_1111101001_0000000001, //16
|
||||
40'b11111_11111_1000111111_1111101001_0000000001, //17
|
||||
40'b11111_11111_1000100110_1111101001_0000000001, //18
|
||||
40'b11111_11111_1000001101_1111101001_0000000001 //19
|
||||
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40];
|
||||
`ifdef DEBUG
|
||||
$display("lock_lookup: %b", mmcm_pll_lock_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and the bandwidth setting of the PLL
|
||||
// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
|
||||
function [9:0] mmcm_pll_filter_lookup
|
||||
(
|
||||
input [6:0] divide // Max divide is 19
|
||||
);
|
||||
|
||||
reg [639:0] lookup;
|
||||
reg [9:0] lookup_entry;
|
||||
|
||||
begin
|
||||
|
||||
lookup = {
|
||||
// CP_RES_LFHF
|
||||
10'b0010_1111_01, //1
|
||||
10'b0010_0011_11, //2
|
||||
10'b0011_0011_11, //3
|
||||
10'b0010_0001_11, //4
|
||||
10'b0010_0110_11, //5
|
||||
10'b0010_1010_11, //6
|
||||
10'b0010_1010_11, //7
|
||||
10'b0011_0110_11, //8
|
||||
10'b0010_1100_11, //9
|
||||
10'b0010_1100_11, //10
|
||||
10'b0010_1100_11, //11
|
||||
10'b0010_0010_11, //12
|
||||
10'b0011_1100_11, //13
|
||||
10'b0011_1100_11, //14
|
||||
10'b0011_1100_11, //15
|
||||
10'b0011_1100_11, //16
|
||||
10'b0011_0010_11, //17
|
||||
10'b0011_0010_11, //18
|
||||
10'b0011_0010_11 //19
|
||||
};
|
||||
|
||||
mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10];
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("filter_lookup: %b", mmcm_pll_filter_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function set the CLKOUTPHY divide settings to match
|
||||
// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
|
||||
// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
|
||||
// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10
|
||||
function [9:0] mmcm_pll_clkoutphy_calc
|
||||
(
|
||||
input [8*9:0] CLKOUTPHY_MODE
|
||||
);
|
||||
|
||||
if(CLKOUTPHY_MODE == "VCO_X2") begin
|
||||
mmcm_pll_clkoutphy_calc= 2'b00;
|
||||
end else if(CLKOUTPHY_MODE == "VCO") begin
|
||||
mmcm_pll_clkoutphy_calc= 2'b01;
|
||||
end else if(CLKOUTPHY_MODE == "CLKIN") begin
|
||||
mmcm_pll_clkoutphy_calc= 2'b11;
|
||||
end else begin // Assume "VCO_HALF"
|
||||
mmcm_pll_clkoutphy_calc= 2'b10;
|
||||
end
|
||||
|
||||
endfunction
|
||||
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle
|
||||
// setting to calculate the upper and lower counter registers.
|
||||
function [37:0] mmcm_pll_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle // Multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
|
||||
div_calc = mmcm_pll_divider(divide, duty_cycle);
|
||||
// mx[10:9], pm[8:6], dt[5:0]
|
||||
phase_calc = mmcm_pll_phase(divide, phase);
|
||||
|
||||
// Return value is the upper and lower address of counter
|
||||
// Upper address is:
|
||||
// RESERVED [31:26]
|
||||
// MX [25:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
|
||||
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
|
||||
div_calc[13], div_calc[12],
|
||||
phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits
|
||||
`endif
|
||||
|
||||
mmcm_pll_count_calc =
|
||||
{
|
||||
// Upper Address
|
||||
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
|
||||
// Lower Address
|
||||
phase_calc[8:6], 1'b0, div_calc[11:0]
|
||||
};
|
||||
end
|
||||
endfunction
|
||||
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle
|
||||
// setting to calculate the upper and lower counter registers.
|
||||
// for fractional multiply/divide functions.
|
||||
//
|
||||
//
|
||||
function [37:0] mmcm_pll_frac_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle, // Multiplied by 1,000
|
||||
input [9:0] frac // Multiplied by 1000
|
||||
);
|
||||
|
||||
//Required for fractional divide calculations
|
||||
reg [7:0] lt_frac;
|
||||
reg [7:0] ht_frac;
|
||||
|
||||
reg /*[7:0]*/ wf_fall_frac;
|
||||
reg /*[7:0]*/ wf_rise_frac;
|
||||
|
||||
reg [31:0] a;
|
||||
reg [7:0] pm_rise_frac_filtered ;
|
||||
reg [7:0] pm_fall_frac_filtered ;
|
||||
reg [7:0] clkout0_divide_int;
|
||||
reg [2:0] clkout0_divide_frac;
|
||||
reg [7:0] even_part_high;
|
||||
reg [7:0] even_part_low;
|
||||
|
||||
reg [7:0] odd;
|
||||
reg [7:0] odd_and_frac;
|
||||
|
||||
reg [7:0] pm_fall;
|
||||
reg [7:0] pm_rise;
|
||||
reg [7:0] dt;
|
||||
reg [7:0] dt_int;
|
||||
reg [63:0] dt_calc;
|
||||
|
||||
reg [7:0] pm_rise_frac;
|
||||
reg [7:0] pm_fall_frac;
|
||||
|
||||
reg [31:0] a_per_in_octets;
|
||||
reg [31:0] a_phase_in_cycles;
|
||||
|
||||
parameter precision = 0.125;
|
||||
|
||||
reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
|
||||
reg [31: 0] phase_pos;
|
||||
reg [31: 0] phase_vco;
|
||||
reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
//convert phase to fixed
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
|
||||
// Return value is
|
||||
// Transfer data
|
||||
// RESERVED [37:36]
|
||||
// FRAC_TIME [35:33]
|
||||
// FRAC_WF_FALL [32]
|
||||
// Upper address is:
|
||||
// RESERVED [31:26]
|
||||
// MX [25:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
|
||||
|
||||
clkout0_divide_frac = frac / 125;
|
||||
clkout0_divide_int = divide;
|
||||
|
||||
even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
|
||||
even_part_low = even_part_high;
|
||||
|
||||
odd = clkout0_divide_int - even_part_high - even_part_low;
|
||||
odd_and_frac = (8*odd) + clkout0_divide_frac;
|
||||
|
||||
lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
|
||||
ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
|
||||
|
||||
pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
|
||||
pm_rise = 0; //0
|
||||
|
||||
wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
|
||||
wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
|
||||
|
||||
|
||||
|
||||
//Calculate phase in fractional cycles
|
||||
a_per_in_octets = (8 * divide) + (frac / 125) ;
|
||||
a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
|
||||
pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
|
||||
|
||||
dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
|
||||
dt = dt_calc[7:0];
|
||||
|
||||
pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
|
||||
|
||||
dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
|
||||
pm_fall_frac = pm_fall + pm_rise_frac;
|
||||
pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
|
||||
|
||||
div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
|
||||
phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
|
||||
|
||||
mmcm_pll_frac_count_calc[37:0] =
|
||||
{ 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
|
||||
1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
|
||||
3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
|
||||
// pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
|
||||
} ;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
|
||||
`endif
|
||||
|
||||
end
|
||||
endfunction
|
||||
|
||||
|
||||
@ -1,861 +0,0 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Company: Xilinx
|
||||
// Engineer: Jim Tatsukawa. Updated by Ralf Krueger
|
||||
// Date: 7/30/2014
|
||||
// Design Name: MMCME4 DRP
|
||||
// Module Name: mmcme4_drp_func.h
|
||||
// Version: 1.31
|
||||
// Target Devices: UltraScale Plus Architecture
|
||||
// Tool versions: 2017.1
|
||||
// Description: This header provides the functions necessary to
|
||||
// calculate the DRP register values for UltraScal+ MMCM.
|
||||
//
|
||||
// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR)
|
||||
// 4/13 - Fractional divide function in mmcm_frac_count_calc function
|
||||
// 2/28/17 - Updated for Ultrascale Plus
|
||||
//
|
||||
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
|
||||
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
|
||||
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
|
||||
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
||||
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
|
||||
// APPLICATION OR STANDARD, XILINX IS MAKING NO
|
||||
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
|
||||
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
|
||||
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
|
||||
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
|
||||
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
|
||||
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
|
||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
// PURPOSE.
|
||||
//
|
||||
// (c) Copyright 2009-2017 Xilinx, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// These are user functions that should not be modified. Changes to the defines
|
||||
// or code within the functions may alter the accuracy of the calculations.
|
||||
|
||||
// Define debug to provide extra messages during elaboration
|
||||
//`define DEBUG 1
|
||||
|
||||
// FRAC_PRECISION describes the width of the fractional portion of the fixed
|
||||
// point numbers. These should not be modified, they are for development only
|
||||
`define FRAC_PRECISION 10
|
||||
// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
|
||||
// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
|
||||
// greater than 32
|
||||
`define FIXED_WIDTH 32
|
||||
|
||||
// This function takes a fixed point number and rounds it to the nearest
|
||||
// fractional precision bit.
|
||||
function [`FIXED_WIDTH:1] round_frac
|
||||
(
|
||||
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
|
||||
input [`FIXED_WIDTH:1] decimal,
|
||||
|
||||
// This describes the precision of the fraction, for example a value
|
||||
// of 1 would modify the fractional so that instead of being a .16
|
||||
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
|
||||
input [`FIXED_WIDTH:1] precision
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("round_frac - decimal: %h, precision: %h", decimal, precision);
|
||||
`endif
|
||||
// If the fractional precision bit is high then round up
|
||||
if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
|
||||
round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
|
||||
end else begin
|
||||
round_frac = decimal;
|
||||
end
|
||||
`ifdef DEBUG
|
||||
$display("round_frac: %h", round_frac);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates high_time, low_time, w_edge, and no_count
|
||||
// of a non-fractional counter based on the divide and duty cycle
|
||||
//
|
||||
// NOTE: high_time and low_time are returned as integers between 0 and 63
|
||||
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
|
||||
// ignore the overflow)
|
||||
function [13:0] mmcm_pll_divider
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] duty_cycle_fix;
|
||||
|
||||
// High/Low time is initially calculated with a wider integer to prevent a
|
||||
// calculation error when it overflows to 64.
|
||||
reg [6:0] high_time;
|
||||
reg [6:0] low_time;
|
||||
reg w_edge;
|
||||
reg no_count;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
// Duty Cycle must be between 0 and 1,000
|
||||
if(duty_cycle <=0 || duty_cycle >= 100000) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
|
||||
duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("duty_cycle_fix: %h", duty_cycle_fix);
|
||||
`endif
|
||||
|
||||
// If the divide is 1 nothing needs to be set except the no_count bit.
|
||||
// Other values are dummies
|
||||
if(divide == 7'h01) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
low_time = 7'h01;
|
||||
no_count = 1'b1;
|
||||
end else begin
|
||||
temp = round_frac(duty_cycle_fix*divide, 1);
|
||||
|
||||
// comes from above round_frac
|
||||
high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
|
||||
// If the duty cycle * divide rounded is .5 or greater then this bit
|
||||
// is set.
|
||||
w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
|
||||
|
||||
// If the high time comes out to 0, it needs to be set to at least 1
|
||||
// and w_edge set to 0
|
||||
if(high_time == 7'h00) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
end
|
||||
|
||||
if(high_time == divide) begin
|
||||
high_time = divide - 1;
|
||||
w_edge = 1'b1;
|
||||
end
|
||||
|
||||
// Calculate low_time based on the divide setting and set no_count to
|
||||
// 0 as it is only used when divide is 1.
|
||||
low_time = divide - high_time;
|
||||
no_count = 1'b0;
|
||||
end
|
||||
|
||||
// Set the return value.
|
||||
mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates mx, delay_time, and phase_mux
|
||||
// of a non-fractional counter based on the divide and phase
|
||||
//
|
||||
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
|
||||
// is used.
|
||||
function [10:0] mmcm_pll_phase
|
||||
(
|
||||
// divide must be an integer (use fractional if not)
|
||||
// assumed that divide already checked to be valid
|
||||
input [7:0] divide, // Max divide is 128
|
||||
|
||||
// Phase is given in degrees (-360,000 to 360,000)
|
||||
input signed [31:0] phase
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] phase_in_cycles;
|
||||
reg [`FIXED_WIDTH:1] phase_fixed;
|
||||
reg [1:0] mx;
|
||||
reg [5:0] delay_time;
|
||||
reg [2:0] phase_mux;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_phase-divide:%d,phase:%d", divide, phase);
|
||||
`endif
|
||||
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// If phase is less than 0, convert it to a positive phase shift
|
||||
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
|
||||
if(phase < 0) begin
|
||||
phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
|
||||
end else begin
|
||||
phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
|
||||
end
|
||||
|
||||
// Put phase in terms of decimal number of vco clock cycles
|
||||
phase_in_cycles = ( phase_fixed * divide ) / 360;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("phase_in_cycles: %h", phase_in_cycles);
|
||||
`endif
|
||||
|
||||
temp = round_frac(phase_in_cycles, 3);
|
||||
|
||||
// set mx to 2'b00 that the phase mux from the VCO is enabled
|
||||
mx = 2'b00;
|
||||
phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
|
||||
delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("temp: %h", temp);
|
||||
`endif
|
||||
|
||||
// Setup the return value
|
||||
mmcm_pll_phase={mx, phase_mux, delay_time};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and outputs the necessary lock values
|
||||
function [39:0] mmcm_pll_lock_lookup
|
||||
(
|
||||
input [7:0] divide // Max M divide is 128 in UltrascalePlus
|
||||
);
|
||||
|
||||
reg [5119:0] lookup;
|
||||
|
||||
begin
|
||||
lookup = {
|
||||
// This table is composed of:
|
||||
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
|
||||
40'b00110_00110_1111101000_1111101001_0000000001, // M=1 (not allowed)
|
||||
40'b00110_00110_1111101000_1111101001_0000000001, // M=2
|
||||
40'b01000_01000_1111101000_1111101001_0000000001, // M=3
|
||||
40'b01011_01011_1111101000_1111101001_0000000001, // M=4
|
||||
40'b01110_01110_1111101000_1111101001_0000000001, // M=5
|
||||
40'b10001_10001_1111101000_1111101001_0000000001, // M=6
|
||||
40'b10011_10011_1111101000_1111101001_0000000001, // M=7
|
||||
40'b10110_10110_1111101000_1111101001_0000000001,
|
||||
40'b11001_11001_1111101000_1111101001_0000000001,
|
||||
40'b11100_11100_1111101000_1111101001_0000000001,
|
||||
40'b11111_11111_1110000100_1111101001_0000000001,
|
||||
40'b11111_11111_1100111001_1111101001_0000000001,
|
||||
40'b11111_11111_1011101110_1111101001_0000000001,
|
||||
40'b11111_11111_1010111100_1111101001_0000000001,
|
||||
40'b11111_11111_1010001010_1111101001_0000000001,
|
||||
40'b11111_11111_1001110001_1111101001_0000000001,
|
||||
40'b11111_11111_1000111111_1111101001_0000000001,
|
||||
40'b11111_11111_1000100110_1111101001_0000000001,
|
||||
40'b11111_11111_1000001101_1111101001_0000000001,
|
||||
40'b11111_11111_0111110100_1111101001_0000000001,
|
||||
40'b11111_11111_0111011011_1111101001_0000000001,
|
||||
40'b11111_11111_0111000010_1111101001_0000000001,
|
||||
40'b11111_11111_0110101001_1111101001_0000000001,
|
||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
||||
40'b11111_11111_0101110111_1111101001_0000000001,
|
||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001, // M=127
|
||||
40'b11111_11111_0011111010_1111101001_0000000001 // M=128
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40];
|
||||
`ifdef DEBUG
|
||||
$display("lock_lookup: %b", mmcm_pll_lock_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and the bandwidth setting of the MMCM
|
||||
// and outputs the digital filter settings necessary.
|
||||
function [9:0] mmcm_pll_filter_lookup
|
||||
(
|
||||
input [7:0] divide, // input [7:0] divide // Max M divide is 128 in UltraScalePlus
|
||||
input [8*9:0] BANDWIDTH
|
||||
);
|
||||
|
||||
reg [1279:0] lookup_low;
|
||||
reg [1279:0] lookup_high;
|
||||
|
||||
reg [9:0] lookup_entry;
|
||||
|
||||
begin
|
||||
lookup_low = {
|
||||
// CP_RES_LFHF
|
||||
10'b0011_1111_11, // M=1 - not legal
|
||||
10'b0011_1111_11, // M=2
|
||||
10'b0011_1101_11, // M=3
|
||||
10'b0011_0101_11, // M=4
|
||||
10'b0011_1001_11, // M=5
|
||||
10'b0011_1110_11, // M=6
|
||||
10'b0011_1110_11, // M=7
|
||||
10'b0011_0001_11,
|
||||
10'b0011_0110_11,
|
||||
10'b0011_0110_11,
|
||||
10'b0011_0110_11,
|
||||
10'b0011_1010_11,
|
||||
10'b0011_1010_11,
|
||||
10'b0011_1010_11,
|
||||
10'b0100_0110_11,
|
||||
10'b0011_1100_11,
|
||||
10'b1110_0110_11,
|
||||
10'b1111_0110_11,
|
||||
10'b1110_1010_11,
|
||||
10'b1110_1010_11,
|
||||
10'b1111_1010_11,
|
||||
10'b1111_1010_11,
|
||||
10'b1111_1010_11,
|
||||
10'b1111_1010_11,
|
||||
10'b1111_1010_11,
|
||||
10'b1101_1100_11,
|
||||
10'b1101_1100_11,
|
||||
10'b1101_1100_11,
|
||||
10'b1110_1100_11,
|
||||
10'b1110_1100_11,
|
||||
10'b1110_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1110_0010_11,
|
||||
10'b1110_0010_11,
|
||||
10'b1110_0010_11,
|
||||
10'b1110_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11, // M=127
|
||||
10'b1101_1000_11 // M=128
|
||||
};
|
||||
|
||||
lookup_high = {
|
||||
// CP_RES_LFHF
|
||||
10'b0111_1111_11, // M=1 - not legal
|
||||
10'b0111_1111_11, // M=2
|
||||
10'b1110_1111_11, // M=3
|
||||
10'b1111_1111_11, // M=4
|
||||
10'b1111_1011_11, // M=5
|
||||
10'b1111_1101_11, // M=6
|
||||
10'b1111_0011_11, // M=7
|
||||
10'b1110_0101_11,
|
||||
10'b1111_1001_11,
|
||||
10'b1111_1001_11,
|
||||
10'b1110_1110_11,
|
||||
10'b1111_1110_11,
|
||||
10'b1111_0001_11,
|
||||
10'b1111_0001_11,
|
||||
10'b1111_0001_11,
|
||||
10'b1110_0110_11,
|
||||
10'b1110_0110_11,
|
||||
10'b1111_0110_11,
|
||||
10'b1110_1010_11,
|
||||
10'b1110_1010_11,
|
||||
10'b1111_1010_11,
|
||||
10'b1111_1010_11,
|
||||
10'b1111_1010_11,
|
||||
10'b1111_1010_11,
|
||||
10'b1111_1010_11,
|
||||
10'b1101_1100_11,
|
||||
10'b1101_1100_11,
|
||||
10'b1101_1100_11,
|
||||
10'b1110_1100_11,
|
||||
10'b1110_1100_11,
|
||||
10'b1110_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1110_0010_11,
|
||||
10'b1110_0010_11,
|
||||
10'b1110_0010_11,
|
||||
10'b1110_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11 // M=128
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
if(BANDWIDTH == "LOW") begin
|
||||
// Low Bandwidth
|
||||
mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10];
|
||||
end else begin
|
||||
// High or optimized bandwidth
|
||||
mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10];
|
||||
end
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("filter_lookup: %b", mmcm_pll_filter_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle
|
||||
// setting to calculate the upper and lower counter registers.
|
||||
function [37:0] mmcm_pll_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle // Multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
|
||||
div_calc = mmcm_pll_divider(divide, duty_cycle);
|
||||
// mx[10:9], pm[8:6], dt[5:0]
|
||||
phase_calc = mmcm_pll_phase(divide, phase);
|
||||
|
||||
// Return value is the upper and lower address of counter
|
||||
// Upper address is:
|
||||
// RESERVED [31:26]
|
||||
// MX [25:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
|
||||
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
|
||||
div_calc[13], div_calc[12],
|
||||
phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
|
||||
`endif
|
||||
|
||||
mmcm_pll_count_calc =
|
||||
{
|
||||
// Upper Address
|
||||
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
|
||||
// Lower Address
|
||||
phase_calc[8:6], 1'b0, div_calc[11:0]
|
||||
};
|
||||
end
|
||||
endfunction
|
||||
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle
|
||||
// setting to calculate the upper and lower counter registers.
|
||||
// for fractional multiply/divide functions.
|
||||
//
|
||||
//
|
||||
function [37:0] mmcm_frac_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional
|
||||
input [9:0] frac // Multiplied by 1000
|
||||
);
|
||||
|
||||
//Required for fractional divide calculations
|
||||
reg [7:0] lt_frac;
|
||||
reg [7:0] ht_frac;
|
||||
|
||||
reg /*[7:0]*/ wf_fall_frac;
|
||||
reg /*[7:0]*/ wf_rise_frac;
|
||||
|
||||
reg [31:0] a;
|
||||
reg [7:0] pm_rise_frac_filtered ;
|
||||
reg [7:0] pm_fall_frac_filtered ;
|
||||
reg [7:0] clkout0_divide_int;
|
||||
reg [2:0] clkout0_divide_frac;
|
||||
reg [7:0] even_part_high;
|
||||
reg [7:0] even_part_low;
|
||||
|
||||
reg [7:0] odd;
|
||||
reg [7:0] odd_and_frac;
|
||||
|
||||
reg [7:0] pm_fall;
|
||||
reg [7:0] pm_rise;
|
||||
reg [7:0] dt;
|
||||
reg [7:0] dt_int;
|
||||
reg [63:0] dt_calc;
|
||||
|
||||
reg [7:0] pm_rise_frac;
|
||||
reg [7:0] pm_fall_frac;
|
||||
|
||||
reg [31:0] a_per_in_octets;
|
||||
reg [31:0] a_phase_in_cycles;
|
||||
|
||||
parameter precision = 0.125;
|
||||
|
||||
reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
|
||||
reg [31: 0] phase_pos;
|
||||
reg [31: 0] phase_vco;
|
||||
reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
//convert phase to fixed
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
|
||||
// Return value is
|
||||
// Transfer data
|
||||
// RESERVED [37:36]
|
||||
// FRAC_TIME [35:33]
|
||||
// FRAC_WF_FALL [32]
|
||||
// Upper address is:
|
||||
// RESERVED [31:26]
|
||||
// MX [25:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
|
||||
|
||||
clkout0_divide_frac = frac / 125;
|
||||
clkout0_divide_int = divide;
|
||||
|
||||
even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
|
||||
even_part_low = even_part_high;
|
||||
|
||||
odd = clkout0_divide_int - even_part_high - even_part_low;
|
||||
odd_and_frac = (8*odd) + clkout0_divide_frac;
|
||||
|
||||
lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
|
||||
ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
|
||||
|
||||
pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
|
||||
pm_rise = 0; //0
|
||||
|
||||
wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1); //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
|
||||
wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8); //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
|
||||
|
||||
|
||||
|
||||
//Calculate phase in fractional cycles
|
||||
a_per_in_octets = (8 * divide) + (frac / 125) ;
|
||||
a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
|
||||
pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
|
||||
|
||||
dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
|
||||
dt = dt_calc[7:0];
|
||||
|
||||
pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
|
||||
|
||||
dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
|
||||
pm_fall_frac = pm_fall + pm_rise_frac;
|
||||
pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
|
||||
|
||||
div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
|
||||
phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
|
||||
|
||||
mmcm_frac_count_calc[37:0] =
|
||||
{ 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
|
||||
1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0],
|
||||
pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
|
||||
} ;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
|
||||
`endif
|
||||
|
||||
end
|
||||
endfunction
|
||||
|
||||
@ -1,536 +0,0 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Company: Xilinx
|
||||
// Engineer: Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+
|
||||
// Date: 6/15/2015
|
||||
// Design Name: PLLE4 DRP
|
||||
// Module Name: plle4_drp_func.h
|
||||
// Version: 2.0
|
||||
// Target Devices: UltraScale+ Architecture
|
||||
// Tool versions: 2017.1
|
||||
// Description: This header provides the functions necessary to
|
||||
// calculate the DRP register values for the V6 PLL.
|
||||
//
|
||||
// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419
|
||||
// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19
|
||||
// M_Rise bits have been removed for PLLE3
|
||||
// Revision Notes: 2/28/17 - pll_filter_lookup and CPRES updated for
|
||||
// Ultrascale+ and for max M of 21
|
||||
//
|
||||
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
|
||||
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
|
||||
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
|
||||
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
||||
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
|
||||
// APPLICATION OR STANDARD, XILINX IS MAKING NO
|
||||
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
|
||||
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
|
||||
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
|
||||
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
|
||||
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
|
||||
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
|
||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
// PURPOSE.
|
||||
//
|
||||
// (c) Copyright 2009-2017 Xilinx, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// These are user functions that should not be modified. Changes to the defines
|
||||
// or code within the functions may alter the accuracy of the calculations.
|
||||
|
||||
// Define debug to provide extra messages durring elaboration
|
||||
//`define DEBUG 1
|
||||
|
||||
// FRAC_PRECISION describes the width of the fractional portion of the fixed
|
||||
// point numbers. These should not be modified, they are for development
|
||||
// only
|
||||
`define FRAC_PRECISION 10
|
||||
// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
|
||||
// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
|
||||
// greater than 32
|
||||
`define FIXED_WIDTH 32
|
||||
|
||||
// This function takes a fixed point number and rounds it to the nearest
|
||||
// fractional precision bit.
|
||||
function [`FIXED_WIDTH:1] round_frac
|
||||
(
|
||||
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
|
||||
input [`FIXED_WIDTH:1] decimal,
|
||||
|
||||
// This describes the precision of the fraction, for example a value
|
||||
// of 1 would modify the fractional so that instead of being a .16
|
||||
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
|
||||
input [`FIXED_WIDTH:1] precision
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("round_frac - decimal: %h, precision: %h", decimal, precision);
|
||||
`endif
|
||||
// If the fractional precision bit is high then round up
|
||||
if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
|
||||
round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
|
||||
end else begin
|
||||
round_frac = decimal;
|
||||
end
|
||||
`ifdef DEBUG
|
||||
$display("round_frac: %h", round_frac);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates high_time, low_time, w_edge, and no_count
|
||||
// of a non-fractional counter based on the divide and duty cycle
|
||||
//
|
||||
// NOTE: high_time and low_time are returned as integers between 0 and 63
|
||||
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
|
||||
// ignore the overflow)
|
||||
function [13:0] mmcm_pll_divider
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] duty_cycle_fix;
|
||||
|
||||
// High/Low time is initially calculated with a wider integer to prevent a
|
||||
// calculation error when it overflows to 64.
|
||||
reg [6:0] high_time;
|
||||
reg [6:0] low_time;
|
||||
reg w_edge;
|
||||
reg no_count;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
// Duty Cycle must be between 0 and 1,000
|
||||
if(duty_cycle <=0 || duty_cycle >= 100000) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
|
||||
duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("duty_cycle_fix: %h", duty_cycle_fix);
|
||||
`endif
|
||||
|
||||
// If the divide is 1 nothing needs to be set except the no_count bit.
|
||||
// Other values are dummies
|
||||
if(divide == 7'h01) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
low_time = 7'h01;
|
||||
no_count = 1'b1;
|
||||
end else begin
|
||||
temp = round_frac(duty_cycle_fix*divide, 1);
|
||||
|
||||
// comes from above round_frac
|
||||
high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
|
||||
// If the duty cycle * divide rounded is .5 or greater then this bit
|
||||
// is set.
|
||||
w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
|
||||
|
||||
// If the high time comes out to 0, it needs to be set to at least 1
|
||||
// and w_edge set to 0
|
||||
if(high_time == 7'h00) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
end
|
||||
|
||||
if(high_time == divide) begin
|
||||
high_time = divide - 1;
|
||||
w_edge = 1'b1;
|
||||
end
|
||||
|
||||
// Calculate low_time based on the divide setting and set no_count to
|
||||
// 0 as it is only used when divide is 1.
|
||||
low_time = divide - high_time;
|
||||
no_count = 1'b0;
|
||||
end
|
||||
|
||||
// Set the return value.
|
||||
mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates mx, delay_time, and phase_mux
|
||||
// of a non-fractional counter based on the divide and phase
|
||||
//
|
||||
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
|
||||
// is used.
|
||||
function [10:0] mmcm_pll_phase
|
||||
(
|
||||
// divide must be an integer (use fractional if not)
|
||||
// assumed that divide already checked to be valid
|
||||
input [7:0] divide, // Max divide is 128
|
||||
|
||||
// Phase is given in degrees (-360,000 to 360,000)
|
||||
input signed [31:0] phase
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] phase_in_cycles;
|
||||
reg [`FIXED_WIDTH:1] phase_fixed;
|
||||
reg [1:0] mx;
|
||||
reg [5:0] delay_time;
|
||||
reg [2:0] phase_mux;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("pll_phase-divide:%d,phase:%d",
|
||||
divide, phase);
|
||||
`endif
|
||||
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// If phase is less than 0, convert it to a positive phase shift
|
||||
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
|
||||
if(phase < 0) begin
|
||||
phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
|
||||
end else begin
|
||||
phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
|
||||
end
|
||||
|
||||
// Put phase in terms of decimal number of vco clock cycles
|
||||
phase_in_cycles = ( phase_fixed * divide ) / 360;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("phase_in_cycles: %h", phase_in_cycles);
|
||||
`endif
|
||||
|
||||
|
||||
temp = round_frac(phase_in_cycles, 3);
|
||||
|
||||
// set mx to 2'b00 that the phase mux from the VCO is enabled
|
||||
mx = 2'b00;
|
||||
phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
|
||||
delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("temp: %h", temp);
|
||||
`endif
|
||||
|
||||
// Setup the return value
|
||||
mmcm_pll_phase={mx, phase_mux, delay_time};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and outputs the necessary lock values
|
||||
function [39:0] mmcm_pll_lock_lookup
|
||||
(
|
||||
input [6:0] divide // Max divide is 21
|
||||
);
|
||||
|
||||
reg [839:0] lookup;
|
||||
|
||||
begin
|
||||
lookup = {
|
||||
// This table is composed of:
|
||||
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
|
||||
40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+
|
||||
40'b00110_00110_1111101000_1111101001_0000000001, //2
|
||||
40'b01000_01000_1111101000_1111101001_0000000001, //3
|
||||
40'b01011_01011_1111101000_1111101001_0000000001, //4
|
||||
40'b01110_01110_1111101000_1111101001_0000000001, //5
|
||||
40'b10001_10001_1111101000_1111101001_0000000001, //6
|
||||
40'b10011_10011_1111101000_1111101001_0000000001, //7
|
||||
40'b10110_10110_1111101000_1111101001_0000000001, //8
|
||||
40'b11001_11001_1111101000_1111101001_0000000001, //9
|
||||
40'b11100_11100_1111101000_1111101001_0000000001, //10
|
||||
40'b11111_11111_1110000100_1111101001_0000000001, //11
|
||||
40'b11111_11111_1100111001_1111101001_0000000001, //12
|
||||
40'b11111_11111_1011101110_1111101001_0000000001, //13
|
||||
40'b11111_11111_1010111100_1111101001_0000000001, //14
|
||||
40'b11111_11111_1010001010_1111101001_0000000001, //15
|
||||
40'b11111_11111_1001110001_1111101001_0000000001, //16
|
||||
40'b11111_11111_1000111111_1111101001_0000000001, //17
|
||||
40'b11111_11111_1000100110_1111101001_0000000001, //18
|
||||
40'b11111_11111_1000001101_1111101001_0000000001, //19
|
||||
40'b11111_11111_0111110100_1111101001_0000000001, //20
|
||||
40'b11111_11111_0111011011_1111101001_0000000001 //21
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40];
|
||||
`ifdef DEBUG
|
||||
$display("lock_lookup: %b", pll_lock_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and the bandwidth setting of the PLL
|
||||
// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
|
||||
function [9:0] mmcm_pll_filter_lookup
|
||||
(
|
||||
input [6:0] divide // Max divide is 21
|
||||
);
|
||||
|
||||
reg [209:0] lookup;
|
||||
reg [9:0] lookup_entry;
|
||||
|
||||
begin
|
||||
|
||||
lookup = {
|
||||
// CP_RES_LFHF
|
||||
10'b0011_0111_11, //1 not legal in Ultrascale+
|
||||
10'b0011_0111_11, //2
|
||||
10'b0011_0011_11, //3
|
||||
10'b0011_1001_11, //4
|
||||
10'b0011_0001_11, //5
|
||||
10'b0100_1110_11, //6
|
||||
10'b0011_0110_11, //7
|
||||
10'b0011_1010_11, //8
|
||||
10'b0111_1001_11, //9
|
||||
10'b0111_1001_11, //10
|
||||
10'b0101_0110_11, //11
|
||||
10'b1100_0101_11, //12
|
||||
10'b0101_1010_11, //13
|
||||
10'b0110_0110_11, //14
|
||||
10'b0110_1010_11, //15
|
||||
10'b0111_0110_11, //16
|
||||
10'b1111_0101_11, //17
|
||||
10'b1100_0110_11, //18
|
||||
10'b1110_0001_11, //19
|
||||
10'b1101_0110_11, //20
|
||||
10'b1111_0001_11 //21
|
||||
};
|
||||
|
||||
mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10];
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("filter_lookup: %b", pll_filter_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function set the CLKOUTPHY divide settings to match
|
||||
// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
|
||||
// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
|
||||
// doubled and 2'b00 will represent divide by 1. Similarly "VCO"
|
||||
// will need to divide the doubled clock VCO clock frequency by
|
||||
// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will
|
||||
// need to divide the doubled VCO by 4, therefore 2'b10
|
||||
function [9:0] mmcm_pll_clkoutphy_calc
|
||||
(
|
||||
input [8*9:0] CLKOUTPHY_MODE
|
||||
);
|
||||
|
||||
if(CLKOUTPHY_MODE == "VCO_X2") begin
|
||||
mmcm_pll_clkoutphy_calc= 2'b00;
|
||||
end else if(CLKOUTPHY_MODE == "VCO") begin
|
||||
mmcm_pll_clkoutphy_calc= 2'b01;
|
||||
end else if(CLKOUTPHY_MODE == "CLKIN") begin
|
||||
mmcm_pll_clkoutphy_calc= 2'b11;
|
||||
end else begin // Assume "VCO_HALF"
|
||||
mmcm_pll_clkoutphy_calc= 2'b10;
|
||||
end
|
||||
|
||||
endfunction
|
||||
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle
|
||||
// setting to calculate the upper and lower counter registers.
|
||||
function [37:0] mmcm_pll_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle // Multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
|
||||
div_calc = mmcm_pll_divider(divide, duty_cycle);
|
||||
// mx[10:9], pm[8:6], dt[5:0]
|
||||
phase_calc = mmcm_pll_phase(divide, phase);
|
||||
|
||||
// Return value is the upper and lower address of counter
|
||||
// Upper address is:
|
||||
// RESERVED [31:26]
|
||||
// MX [25:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
|
||||
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
|
||||
div_calc[13], div_calc[12],
|
||||
phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits
|
||||
`endif
|
||||
|
||||
mmcm_pll_count_calc =
|
||||
{
|
||||
// Upper Address
|
||||
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
|
||||
// Lower Address
|
||||
phase_calc[8:6], 1'b0, div_calc[11:0]
|
||||
};
|
||||
end
|
||||
endfunction
|
||||
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle
|
||||
// setting to calculate the upper and lower counter registers.
|
||||
// for fractional multiply/divide functions.
|
||||
//
|
||||
//
|
||||
function [37:0] mmcm_pll_frac_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle, // Multiplied by 1,000
|
||||
input [9:0] frac // Multiplied by 1000
|
||||
);
|
||||
|
||||
//Required for fractional divide calculations
|
||||
reg [7:0] lt_frac;
|
||||
reg [7:0] ht_frac;
|
||||
|
||||
reg /*[7:0]*/ wf_fall_frac;
|
||||
reg /*[7:0]*/ wf_rise_frac;
|
||||
|
||||
reg [31:0] a;
|
||||
reg [7:0] pm_rise_frac_filtered ;
|
||||
reg [7:0] pm_fall_frac_filtered ;
|
||||
reg [7:0] clkout0_divide_int;
|
||||
reg [2:0] clkout0_divide_frac;
|
||||
reg [7:0] even_part_high;
|
||||
reg [7:0] even_part_low;
|
||||
|
||||
reg [7:0] odd;
|
||||
reg [7:0] odd_and_frac;
|
||||
|
||||
reg [7:0] pm_fall;
|
||||
reg [7:0] pm_rise;
|
||||
reg [7:0] dt;
|
||||
reg [7:0] dt_int;
|
||||
reg [63:0] dt_calc;
|
||||
|
||||
reg [7:0] pm_rise_frac;
|
||||
reg [7:0] pm_fall_frac;
|
||||
|
||||
reg [31:0] a_per_in_octets;
|
||||
reg [31:0] a_phase_in_cycles;
|
||||
|
||||
parameter precision = 0.125;
|
||||
|
||||
reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
|
||||
reg [31: 0] phase_pos;
|
||||
reg [31: 0] phase_vco;
|
||||
reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
//convert phase to fixed
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
|
||||
// Return value is
|
||||
// Transfer data
|
||||
// RESERVED [37:36]
|
||||
// FRAC_TIME [35:33]
|
||||
// FRAC_WF_FALL [32]
|
||||
// Upper address is:
|
||||
// RESERVED [31:26]
|
||||
// MX [25:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
|
||||
|
||||
clkout0_divide_frac = frac / 125;
|
||||
clkout0_divide_int = divide;
|
||||
|
||||
even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
|
||||
even_part_low = even_part_high;
|
||||
|
||||
odd = clkout0_divide_int - even_part_high - even_part_low;
|
||||
odd_and_frac = (8*odd) + clkout0_divide_frac;
|
||||
|
||||
lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
|
||||
ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
|
||||
|
||||
pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
|
||||
pm_rise = 0; //0
|
||||
|
||||
wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
|
||||
wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
|
||||
|
||||
|
||||
|
||||
//Calculate phase in fractional cycles
|
||||
a_per_in_octets = (8 * divide) + (frac / 125) ;
|
||||
a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
|
||||
pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
|
||||
|
||||
dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
|
||||
dt = dt_calc[7:0];
|
||||
|
||||
pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
|
||||
|
||||
dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
|
||||
pm_fall_frac = pm_fall + pm_rise_frac;
|
||||
pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
|
||||
|
||||
div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
|
||||
phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
|
||||
|
||||
mmcm_pll_frac_count_calc[37:0] =
|
||||
{ 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
|
||||
1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
|
||||
3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
|
||||
} ;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
|
||||
`endif
|
||||
|
||||
end
|
||||
endfunction
|
||||
|
||||
@ -0,0 +1,83 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2020.1 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required
|
||||
# to simulate the design for a simulator, the directory structure
|
||||
# and the generated exported files.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. Simulate Design
|
||||
|
||||
To simulate design, cd to the simulator directory and execute the script.
|
||||
|
||||
For example:-
|
||||
|
||||
% cd questa
|
||||
% ./top.sh
|
||||
|
||||
The export simulation flow requires the Xilinx pre-compiled simulation library
|
||||
components for the target simulator. These components are referred using the
|
||||
'-lib_map_path' switch. If this switch is specified, then the export simulation
|
||||
will automatically set this library path in the generated script and update,
|
||||
copy the simulator setup file(s) in the exported directory.
|
||||
|
||||
If '-lib_map_path' is not specified, then the pre-compiled simulation library
|
||||
information will not be included in the exported scripts and that may cause
|
||||
simulation errors when running this script. Alternatively, you can provide the
|
||||
library information using this switch while executing the generated script.
|
||||
|
||||
For example:-
|
||||
|
||||
% ./top.sh -lib_map_path /design/questa/clibs
|
||||
|
||||
Please refer to the generated script header 'Prerequisite' section for more details.
|
||||
|
||||
2. Directory Structure
|
||||
|
||||
By default, if the -directory switch is not specified, export_simulation will
|
||||
create the following directory structure:-
|
||||
|
||||
<current_working_directory>/export_sim/<simulator>
|
||||
|
||||
For example, if the current working directory is /tmp/test, export_simulation
|
||||
will create the following directory path:-
|
||||
|
||||
/tmp/test/export_sim/questa
|
||||
|
||||
If -directory switch is specified, export_simulation will create a simulator
|
||||
sub-directory under the specified directory path.
|
||||
|
||||
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
|
||||
command will create the following directory:-
|
||||
|
||||
/tmp/test/my_test_area/func_sim/questa
|
||||
|
||||
By default, if -simulator is not specified, export_simulation will create a
|
||||
simulator sub-directory for each simulator and export the files for each simulator
|
||||
in this sub-directory respectively.
|
||||
|
||||
IMPORTANT: Please note that the simulation library path must be specified manually
|
||||
in the generated script for the respective simulator. Please refer to the generated
|
||||
script header 'Prerequisite' section for more details.
|
||||
|
||||
3. Exported script and files
|
||||
|
||||
Export simulation will create the driver shell script, setup files and copy the
|
||||
design sources in the output directory path.
|
||||
|
||||
By default, when the -script_name switch is not specified, export_simulation will
|
||||
create the following script name:-
|
||||
|
||||
<simulation_top>.sh (Unix)
|
||||
When exporting the files for an IP using the -of_objects switch, export_simulation
|
||||
will create the following script name:-
|
||||
|
||||
<ip-name>.sh (Unix)
|
||||
Export simulation will create the setup files for the target simulator specified
|
||||
with the -simulator switch.
|
||||
|
||||
For example, if the target simulator is "ies", export_simulation will create the
|
||||
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
|
||||
file.
|
||||
|
||||
@ -0,0 +1,49 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2020.1 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Mon Mar 22 18:48:49 -0400 2021
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./fifo_generator_0.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './fifo_generator_0.sh' script.
|
||||
|
||||
./fifo_generator_0.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./fifo_generator_0.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './fifo_generator_0.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
@ -0,0 +1,47 @@
|
||||
vlib work
|
||||
vlib activehdl
|
||||
|
||||
vlib activehdl/xilinx_vip
|
||||
vlib activehdl/xpm
|
||||
vlib activehdl/fifo_generator_v13_2_5
|
||||
vlib activehdl/xil_defaultlib
|
||||
|
||||
vmap xilinx_vip activehdl/xilinx_vip
|
||||
vmap xpm activehdl/xpm
|
||||
vmap fifo_generator_v13_2_5 activehdl/fifo_generator_v13_2_5
|
||||
vmap xil_defaultlib activehdl/xil_defaultlib
|
||||
|
||||
vlog -work xilinx_vip -sv2k12 "+incdir+C:/Xilinx/Vivado/2020.1/data/xilinx_vip/include" \
|
||||
"C:/Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
|
||||
"C:/Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
|
||||
"C:/Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
|
||||
"C:/Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
|
||||
"C:/Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
|
||||
"C:/Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
|
||||
"C:/Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi_vip_if.sv" \
|
||||
"C:/Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/clk_vip_if.sv" \
|
||||
"C:/Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/rst_vip_if.sv" \
|
||||
|
||||
vlog -work xpm -sv2k12 "+incdir+C:/Xilinx/Vivado/2020.1/data/xilinx_vip/include" \
|
||||
"C:/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"C:/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
|
||||
"C:/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"C:/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work fifo_generator_v13_2_5 -v2k5 "+incdir+C:/Xilinx/Vivado/2020.1/data/xilinx_vip/include" \
|
||||
"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
|
||||
|
||||
vcom -work fifo_generator_v13_2_5 -93 \
|
||||
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
|
||||
|
||||
vlog -work fifo_generator_v13_2_5 -v2k5 "+incdir+C:/Xilinx/Vivado/2020.1/data/xilinx_vip/include" \
|
||||
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
|
||||
|
||||
vlog -work xil_defaultlib -v2k5 "+incdir+C:/Xilinx/Vivado/2020.1/data/xilinx_vip/include" \
|
||||
"../../../../dso_top_ddr3.srcs/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.v" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
@ -0,0 +1,153 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2020.1 (64-bit)
|
||||
#
|
||||
# Filename : fifo_generator_0.sh
|
||||
# Simulator : Aldec Active-HDL Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Mon Mar 22 18:48:49 -0400 2021
|
||||
# SW Build 2902540 on Wed May 27 19:54:49 MDT 2020
|
||||
#
|
||||
# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: fifo_generator_0.sh [-help]
|
||||
# usage: fifo_generator_0.sh [-lib_map_path]
|
||||
# usage: fifo_generator_0.sh [-noclean_files]
|
||||
# usage: fifo_generator_0.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'fifo_generator_0.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
|
||||
# Script info
|
||||
echo -e "fifo_generator_0.sh - Script generated by export_simulation (Vivado v2020.1 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
source compile.do 2>&1 | tee -a compile.log
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
runvsimsa -l simulate.log -do "do {simulate.do}"
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_generator_0.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
map_setup_file $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
map_setup_file $2
|
||||
esac
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Map library.cfg file
|
||||
map_setup_file()
|
||||
{
|
||||
file="library.cfg"
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
lib_map_path="C:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3_4KB/dso_top_ddr3.cache/compile_simlib/activehdl"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
if [[ -e $src_file ]]; then
|
||||
vmap -link $lib_map_path
|
||||
fi
|
||||
fi
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_generator_0.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: fifo_generator_0.sh [-help]\n\
|
||||
Usage: fifo_generator_0.sh [-lib_map_path]\n\
|
||||
Usage: fifo_generator_0.sh [-reset_run]\n\
|
||||
Usage: fifo_generator_0.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user