AllSpiceMirrors/ThunderScope
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Added channel mux

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This commit is contained in:
Aleksa 2021-03-23 13:35:11 -04:00
parent 5321ef0e44
commit a64aa505fe
115 changed files with 4858 additions and 4273 deletions
Firmware/Artix7_PCIe/dso_top
dso_top.bin
dso_top.cache/wt
gui_handlers.wdfjava_command_handlers.wdfwebtalk_pa.xml
dso_top.srcs/sources_1
bd/design_1
design_1.bddesign_1.bxml
hdl
design_1_wrapper.v
hw_handoff
design_1.hwhdesign_1_bd.tcl
ip
design_1_auto_cc_0
design_1_auto_cc_0.dcpdesign_1_auto_cc_0.xmldesign_1_auto_cc_0_sim_netlist.vdesign_1_auto_cc_0_sim_netlist.vhdldesign_1_auto_cc_0_stub.vdesign_1_auto_cc_0_stub.vhdl
design_1_auto_us_df_0
design_1_auto_us_df_0.dcpdesign_1_auto_us_df_0.xmldesign_1_auto_us_df_0_sim_netlist.vdesign_1_auto_us_df_0_sim_netlist.vhdldesign_1_auto_us_df_0_stub.vdesign_1_auto_us_df_0_stub.vhdl
design_1_auto_us_df_1
design_1_auto_us_df_1.dcpdesign_1_auto_us_df_1.xmldesign_1_auto_us_df_1_sim_netlist.vdesign_1_auto_us_df_1_sim_netlist.vhdldesign_1_auto_us_df_1_stub.vdesign_1_auto_us_df_1_stub.vhdl
design_1_axi_gpio_0_1
design_1_axi_gpio_0_1.dcpdesign_1_axi_gpio_0_1.xcidesign_1_axi_gpio_0_1.xmldesign_1_axi_gpio_0_1_sim_netlist.vdesign_1_axi_gpio_0_1_sim_netlist.vhdldesign_1_axi_gpio_0_1_stub.vdesign_1_axi_gpio_0_1_stub.vhdl
sim
design_1_axi_gpio_0_1.vhd
synth
design_1_axi_gpio_0_1.vhd
design_1_m00_data_fifo_0
design_1_m00_data_fifo_0.dcpdesign_1_m00_data_fifo_0.xmldesign_1_m00_data_fifo_0_sim_netlist.vdesign_1_m00_data_fifo_0_sim_netlist.vhdldesign_1_m00_data_fifo_0_stub.vdesign_1_m00_data_fifo_0_stub.vhdl
design_1_mig_7series_0_0
design_1_mig_7series_0_0.dcpdesign_1_mig_7series_0_0.xml
design_1_mig_7series_0_0/user_design/constraints
design_1_mig_7series_0_0.xdcdesign_1_mig_7series_0_0_ooc.xdc
design_1_mig_7series_0_0_sim_netlist.vdesign_1_mig_7series_0_0_sim_netlist.vhdldesign_1_mig_7series_0_0_stub.vdesign_1_mig_7series_0_0_stub.vhdl
design_1_smartconnect_0_0
bd_0
bd_48ac.bdbd_48ac.bxml
hw_handoff
design_1_smartconnect_0_0.hwh
ip
ip_0
bd_48ac_one_0.xml
ip_1
bd_48ac_psr_aclk_0.xml
ip_10
bd_48ac_woutsw_0.xml
ip_11
bd_48ac_boutsw_0.xml
ip_12
bd_48ac_arni_0.xml
ip_13
bd_48ac_rni_0.xml
ip_14
bd_48ac_awni_0.xml
ip_15
bd_48ac_wni_0.xml
ip_16
bd_48ac_bni_0.xml
ip_17
bd_48ac_s00mmu_0.xml
ip_18
bd_48ac_s00tr_0.xml
ip_19
bd_48ac_s00sic_0.xml
ip_2
bd_48ac_arinsw_0.xml
ip_20
bd_48ac_s00a2s_0.xml
ip_21
bd_48ac_sarn_0.xml
ip_22
bd_48ac_srn_0.xml
ip_23
bd_48ac_sawn_0.xml
ip_24
bd_48ac_swn_0.xml
ip_25
bd_48ac_sbn_0.xml
ip_26
bd_48ac_m00s2a_0.xml
ip_27
bd_48ac_m00arn_0.xml
ip_28
bd_48ac_m00rn_0.xml
ip_29
bd_48ac_m00awn_0.xml
ip_3
bd_48ac_rinsw_0.xml
ip_30
bd_48ac_m00wn_0.xml
ip_31
bd_48ac_m00bn_0.xml
ip_32
bd_48ac_m00e_0.xml
ip_33
bd_48ac_m01s2a_0.xml
ip_34
bd_48ac_m01arn_0.xml
ip_35
bd_48ac_m01rn_0.xml
ip_36
bd_48ac_m01awn_0.xml
ip_37
bd_48ac_m01wn_0.xml
ip_38
bd_48ac_m01bn_0.xml
ip_39
bd_48ac_m01e_0.xml
ip_4
bd_48ac_awinsw_0.xml
ip_40
bd_48ac_m02s2a_0.xml
ip_41
bd_48ac_m02arn_0.xml
ip_42
bd_48ac_m02rn_0.xml
ip_43
bd_48ac_m02awn_0.xml
ip_44
bd_48ac_m02wn_0.xml
ip_45
bd_48ac_m02bn_0.xml
ip_46
bd_48ac_m02e_0.xml
ip_5
bd_48ac_winsw_0.xml
ip_6
bd_48ac_binsw_0.xml
ip_7
bd_48ac_aroutsw_0.xml
ip_8
bd_48ac_routsw_0.xml
ip_9
bd_48ac_awoutsw_0.xml
synth
design_1_smartconnect_0_0.hwdef
design_1_smartconnect_0_0.dcpdesign_1_smartconnect_0_0.xmldesign_1_smartconnect_0_0_sim_netlist.vdesign_1_smartconnect_0_0_sim_netlist.vhdldesign_1_smartconnect_0_0_stub.vdesign_1_smartconnect_0_0_stub.vhdl
sim
design_1.v
synth
design_1.hwdefdesign_1.v
ui
bd_1f5defd0.uibd_77ae6ffa.ui
imports/hdl
dso_top.v
new
adc_to_datamover.v
dso_top.xpr

BIN
Firmware/Artix7_PCIe/dso_top/dso_top.bin
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Firmware/Artix7_PCIe/dso_top/dso_top.cache/wt/gui_handlers.wdf
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@ -1,20 +0,0 @@
version:1
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Firmware/Artix7_PCIe/dso_top/dso_top.cache/wt/java_command_handlers.wdf
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@ -1,7 +0,0 @@
version:1
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70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766570726f6a6563746173:31:00:00
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eof:2258742317

53
Firmware/Artix7_PCIe/dso_top/dso_top.cache/wt/webtalk_pa.xml
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@ -1,53 +0,0 @@
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Mon Mar 22 20:43:54 2021">
<section name="Project Information" visible="false">
<property name="ProjectID" value="847144bab49e4468a88be2f2e5cf8d33" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
<property name="DesignMode" value="RTL" type="DesignMode"/>
<property name="SynthesisStrategy" value="Flow_PerfOptimized_high" type="SynthesisStrategy"/>
<property name="ImplStrategy" value="Performance_ExtraTimingOpt" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="FileExit" value="1" type="JavaHandler"/>
<property name="OpenHardwareManager" value="1" type="JavaHandler"/>
<property name="ProgramCfgMem" value="1" type="JavaHandler"/>
<property name="SaveProjectAs" value="1" type="JavaHandler"/>
<property name="ViewTaskProjectManager" value="1" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="BaseDialog_OK" value="3" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="1" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="1" type="GuiHandlerData"/>
<property name="HardwareTreePanel_HARDWARE_TREE_TABLE" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_CHECKPOINT" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_EXPORT" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_IMPORT" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_IP" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_TEXT_EDITOR" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_PROGRAM_CONFIG_MEMORY" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SAVE_PROJECT_AS" value="1" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="1" type="GuiHandlerData"/>
<property name="ProjectNameChooser_CHOOSE_PROJECT_LOCATION" value="1" type="GuiHandlerData"/>
<property name="ProjectNameChooser_PROJECT_NAME" value="1" type="GuiHandlerData"/>
<property name="SaveProjectAsDialog_INCLUDE_RUN_RESULTS" value="1" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="3" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="2" type="TclMode"/>
</item>
</section>
</application>
</document>

198
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/design_1.bd
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@ -1,7 +1,7 @@
{
"design": {
"design_info": {
"boundary_crc": "0x28BCC63C417EBD47",
"boundary_crc": "0xC908F89A0EB69255",
"device": "xc7a100tfgg484-2",
"name": "design_1",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
@ -309,11 +309,6 @@
}
}
},
"gpio_io_o_0": {
"direction": "O",
"left": "1",
"right": "0"
},
"s2mm_halt": {
"direction": "I"
},
@ -352,6 +347,11 @@
"direction": "I",
"left": "31",
"right": "0"
},
"gpio_io_o_0": {
"direction": "O",
"left": "31",
"right": "0"
}
},
"components": {
@ -502,12 +502,6 @@
"xdma_0/pcie_mgt"
]
},
"CLK_IN_D_0_1": {
"interface_ports": [
"pcie",
"util_ds_buf_0/CLK_IN_D"
]
},
"Conn1": {
"interface_ports": [
"M_AXI_LITE",
@ -519,6 +513,12 @@
"M_AXI",
"xdma_0/M_AXI"
]
},
"CLK_IN_D_0_1": {
"interface_ports": [
"pcie",
"util_ds_buf_0/CLK_IN_D"
]
}
},
"nets": {
@ -905,17 +905,17 @@
}
},
"interface_nets": {
"auto_us_df_to_s00_couplers": {
"interface_ports": [
"M_AXI",
"auto_us_df/M_AXI"
]
},
"s00_couplers_to_auto_us_df": {
"interface_ports": [
"S_AXI",
"auto_us_df/S_AXI"
]
},
"auto_us_df_to_s00_couplers": {
"interface_ports": [
"M_AXI",
"auto_us_df/M_AXI"
]
}
},
"nets": {
@ -1016,17 +1016,17 @@
}
},
"interface_nets": {
"auto_us_df_to_s01_couplers": {
"interface_ports": [
"M_AXI",
"auto_us_df/M_AXI"
]
},
"s01_couplers_to_auto_us_df": {
"interface_ports": [
"S_AXI",
"auto_us_df/S_AXI"
]
},
"auto_us_df_to_s01_couplers": {
"interface_ports": [
"M_AXI",
"auto_us_df/M_AXI"
]
}
},
"nets": {
@ -1130,10 +1130,10 @@
}
},
"interface_nets": {
"m00_couplers_to_m00_data_fifo": {
"auto_cc_to_m00_couplers": {
"interface_ports": [
"S_AXI",
"m00_data_fifo/S_AXI"
"M_AXI",
"auto_cc/M_AXI"
]
},
"m00_data_fifo_to_auto_cc": {
@ -1142,10 +1142,10 @@
"auto_cc/S_AXI"
]
},
"auto_cc_to_m00_couplers": {
"m00_couplers_to_m00_data_fifo": {
"interface_ports": [
"M_AXI",
"auto_cc/M_AXI"
"S_AXI",
"m00_data_fifo/S_AXI"
]
}
},
@ -1180,18 +1180,6 @@
}
},
"interface_nets": {
"axi_interconnect_0_to_s01_couplers": {
"interface_ports": [
"S01_AXI",
"s01_couplers/S_AXI"
]
},
"s01_couplers_to_xbar": {
"interface_ports": [
"s01_couplers/M_AXI",
"xbar/S01_AXI"
]
},
"axi_interconnect_0_to_s00_couplers": {
"interface_ports": [
"S00_AXI",
@ -1215,6 +1203,18 @@
"M00_AXI",
"m00_couplers/M_AXI"
]
},
"axi_interconnect_0_to_s01_couplers": {
"interface_ports": [
"S01_AXI",
"s01_couplers/S_AXI"
]
},
"s01_couplers_to_xbar": {
"interface_ports": [
"s01_couplers/M_AXI",
"xbar/S01_AXI"
]
}
},
"nets": {
@ -1276,18 +1276,6 @@
}
},
"interface_nets": {
"xdma_0_M_AXI": {
"interface_ports": [
"S00_AXI",
"axi_interconnect_0/S00_AXI"
]
},
"Conn1": {
"interface_ports": [
"S01_AXI",
"axi_interconnect_0/S01_AXI"
]
},
"axi_interconnect_0_M00_AXI": {
"interface_ports": [
"axi_interconnect_0/M00_AXI",
@ -1299,6 +1287,18 @@
"DDR3",
"mig_7series_0/DDR3"
]
},
"Conn1": {
"interface_ports": [
"S01_AXI",
"axi_interconnect_0/S01_AXI"
]
},
"xdma_0_M_AXI": {
"interface_ports": [
"S00_AXI",
"axi_interconnect_0/S00_AXI"
]
}
},
"nets": {
@ -1518,11 +1518,6 @@
}
},
"ports": {
"gpio_io_o_0": {
"direction": "O",
"left": "1",
"right": "0"
},
"gpio2_io_i": {
"direction": "I",
"left": "31",
@ -1545,6 +1540,11 @@
"axi_resetn": {
"type": "rst",
"direction": "I"
},
"gpio_io_o_0": {
"direction": "O",
"left": "31",
"right": "0"
}
},
"components": {
@ -1559,7 +1559,7 @@
"value": "1"
},
"C_GPIO_WIDTH": {
"value": "2"
"value": "32"
},
"C_IS_DUAL": {
"value": "1"
@ -1713,6 +1713,12 @@
}
},
"interface_nets": {
"Conn1": {
"interface_ports": [
"AXI_STR_TXD_0",
"axi_fifo_mm_s_0/AXI_STR_TXD"
]
},
"S00_AXI_1": {
"interface_ports": [
"S00_AXI",
@ -1736,21 +1742,9 @@
"smartconnect_0/M02_AXI",
"axi_gpio_1/S_AXI"
]
},
"Conn1": {
"interface_ports": [
"AXI_STR_TXD_0",
"axi_fifo_mm_s_0/AXI_STR_TXD"
]
}
},
"nets": {
"axi_gpio_0_gpio_io_o": {
"ports": [
"axi_gpio_0/gpio_io_o",
"gpio_io_o_0"
]
},
"gpio2_io_i_1": {
"ports": [
"gpio2_io_i",
@ -1786,33 +1780,27 @@
"axi_gpio_0/s_axi_aresetn",
"axi_gpio_1/s_axi_aresetn"
]
},
"axi_gpio_0_gpio_io_o": {
"ports": [
"axi_gpio_0/gpio_io_o",
"gpio_io_o_0"
]
}
}
}
},
"interface_nets": {
"PCIe_M_AXI_LITE": {
"interface_ports": [
"PCIe/M_AXI_LITE",
"AXI_LITE_IO/S00_AXI"
]
},
"S_AXIS_S2MM_1": {
"interface_ports": [
"S_AXIS_S2MM",
"Datamover/S_AXIS_S2MM"
]
},
"S_AXIS_S2MM_CMD_0_1": {
"PCIe_M_AXI_LITE": {
"interface_ports": [
"S_AXIS_S2MM_CMD",
"Datamover/S_AXIS_S2MM_CMD"
]
},
"AXI_LITE_IO_AXI_STR_TXD_0": {
"interface_ports": [
"AXI_STR_TXD_0",
"AXI_LITE_IO/AXI_STR_TXD_0"
"PCIe/M_AXI_LITE",
"AXI_LITE_IO/S00_AXI"
]
},
"CLK_IN_D_0_1": {
@ -1827,10 +1815,22 @@
"Memory/DDR3"
]
},
"xdma_0_M_AXI": {
"S_AXIS_S2MM_CMD_0_1": {
"interface_ports": [
"PCIe/M_AXI",
"Memory/S00_AXI"
"S_AXIS_S2MM_CMD",
"Datamover/S_AXIS_S2MM_CMD"
]
},
"AXI_LITE_IO_AXI_STR_TXD_0": {
"interface_ports": [
"AXI_STR_TXD_0",
"AXI_LITE_IO/AXI_STR_TXD_0"
]
},
"xdma_0_pcie_mgt": {
"interface_ports": [
"pcie_mgt",
"PCIe/pcie_mgt"
]
},
"Datamover_M_AXI_S2MM": {
@ -1839,10 +1839,10 @@
"Memory/S01_AXI"
]
},
"xdma_0_pcie_mgt": {
"xdma_0_M_AXI": {
"interface_ports": [
"pcie_mgt",
"PCIe/pcie_mgt"
"PCIe/M_AXI",
"Memory/S00_AXI"
]
}
},
@ -1895,12 +1895,6 @@
"Datamover/axi_aresetn"
]
},
"axi_gpio_0_gpio_io_o": {
"ports": [
"AXI_LITE_IO/gpio_io_o_0",
"gpio_io_o_0"
]
},
"s2mm_halt_0_1": {
"ports": [
"s2mm_halt",
@ -1918,6 +1912,12 @@
"gpio2_io_i_0",
"AXI_LITE_IO/gpio2_io_i_0"
]
},
"AXI_LITE_IO_gpio_io_o_0": {
"ports": [
"AXI_LITE_IO/gpio_io_o_0",
"gpio_io_o_0"
]
}
},
"addressing": {

30
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/design_1.bxml
View File

@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="39">
<CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1616453866"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1616453866"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1616453866"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1616453866"/>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1616516030"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1616516030"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1616516030"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1616516030"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="ip\design_1_xdma_0_0\design_1_xdma_0_0.xci" Type="IP">
<Instance HierarchyPath="PCIe/xdma_0"/>
@ -127,6 +127,17 @@
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="synth\design_1.v" Type="Verilog">
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
</File>
<File Name="sim\design_1.v" Type="Verilog">
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip\design_1_auto_us_df_0\design_1_auto_us_df_0.xci" Type="IP">
<Instance HierarchyPath="Memory/axi_interconnect_0/s00_couplers/auto_us_df"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
@ -159,17 +170,6 @@
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="synth\design_1.v" Type="Verilog">
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
</File>
<File Name="sim\design_1.v" Type="Verilog">
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="design_1_ooc.xdc" Type="XDC">
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>

6
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
View File

@ -1,7 +1,7 @@
//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
//Date : Mon Mar 22 18:57:01 2021
//Date : Tue Mar 23 12:13:14 2021
//Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
@ -86,7 +86,7 @@ module design_1_wrapper
output axi_aresetn;
input [31:0]gpio2_io_i;
input [31:0]gpio2_io_i_0;
output [1:0]gpio_io_o_0;
output [31:0]gpio_io_o_0;
output [31:0]gpio_io_o_1;
input [0:0]pcie_clk_n;
input [0:0]pcie_clk_p;
@ -131,7 +131,7 @@ module design_1_wrapper
wire axi_aresetn;
wire [31:0]gpio2_io_i;
wire [31:0]gpio2_io_i_0;
wire [1:0]gpio_io_o_0;
wire [31:0]gpio_io_o_0;
wire [31:0]gpio_io_o_1;
wire [0:0]pcie_clk_n;
wire [0:0]pcie_clk_p;

156
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh
View File

@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Mon Mar 22 18:57:46 2021" VIVADOVERSION="2020.1">
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Tue Mar 23 12:13:50 2021" VIVADOVERSION="2020.1">
<SYSTEMINFO ARCH="artix7" DEVICE="7a100t" NAME="design_1" PACKAGE="fgg484" SPEEDGRADE="-2"/>
@ -36,11 +36,6 @@
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="m_axis_s2mm_cmdsts_aresetn"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="gpio_io_o_0" RIGHT="0" SIGIS="undef" SIGNAME="AXI_LITE_IO_axi_gpio_0_gpio_io_o">
<CONNECTIONS>
<CONNECTION INSTANCE="AXI_LITE_IO_axi_gpio_0" PORT="gpio_io_o"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s2mm_halt" SIGIS="undef" SIGNAME="External_Ports_s2mm_halt">
<CONNECTIONS>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s2mm_halt"/>
@ -61,24 +56,74 @@
<CONNECTION INSTANCE="AXI_LITE_IO_axi_gpio_1" PORT="gpio2_io_i"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="pcie_mgt_rxn" RIGHT="0" SIGIS="undef" SIGNAME="PCIe_xdma_0_pci_exp_rxn">
<PORT DIR="I" LEFT="127" NAME="S_AXIS_S2MM_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_s_axis_s2mm_tdata">
<CONNECTIONS>
<CONNECTION INSTANCE="PCIe_xdma_0" PORT="pci_exp_rxn"/>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_tdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="pcie_mgt_rxp" RIGHT="0" SIGIS="undef" SIGNAME="PCIe_xdma_0_pci_exp_rxp">
<PORT DIR="I" LEFT="15" NAME="S_AXIS_S2MM_tkeep" RIGHT="0" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_s_axis_s2mm_tkeep">
<CONNECTIONS>
<CONNECTION INSTANCE="PCIe_xdma_0" PORT="pci_exp_rxp"/>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_tkeep"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="pcie_mgt_txn" RIGHT="0" SIGIS="undef" SIGNAME="PCIe_xdma_0_pci_exp_txn">
<PORT DIR="I" NAME="S_AXIS_S2MM_tlast" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_s_axis_s2mm_tlast">
<CONNECTIONS>
<CONNECTION INSTANCE="PCIe_xdma_0" PORT="pci_exp_txn"/>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_tlast"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="pcie_mgt_txp" RIGHT="0" SIGIS="undef" SIGNAME="PCIe_xdma_0_pci_exp_txp">
<PORT DIR="O" NAME="S_AXIS_S2MM_tready" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_s_axis_s2mm_tready">
<CONNECTIONS>
<CONNECTION INSTANCE="PCIe_xdma_0" PORT="pci_exp_txp"/>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_tready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXIS_S2MM_tvalid" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_s_axis_s2mm_tvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_tvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="71" NAME="S_AXIS_S2MM_CMD_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_s_axis_s2mm_cmd_tdata">
<CONNECTIONS>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_cmd_tdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXIS_S2MM_CMD_tready" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_s_axis_s2mm_cmd_tready">
<CONNECTIONS>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_cmd_tready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXIS_S2MM_CMD_tvalid" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_s_axis_s2mm_cmd_tvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_cmd_tvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="31" NAME="AXI_STR_TXD_0_tdata" RIGHT="0" SIGIS="undef" SIGNAME="AXI_LITE_IO_axi_fifo_mm_s_0_axi_str_txd_tdata">
<CONNECTIONS>
<CONNECTION INSTANCE="AXI_LITE_IO_axi_fifo_mm_s_0" PORT="axi_str_txd_tdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="AXI_STR_TXD_0_tlast" SIGIS="undef" SIGNAME="AXI_LITE_IO_axi_fifo_mm_s_0_axi_str_txd_tlast">
<CONNECTIONS>
<CONNECTION INSTANCE="AXI_LITE_IO_axi_fifo_mm_s_0" PORT="axi_str_txd_tlast"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="AXI_STR_TXD_0_tready" SIGIS="undef" SIGNAME="AXI_LITE_IO_axi_fifo_mm_s_0_axi_str_txd_tready">
<CONNECTIONS>
<CONNECTION INSTANCE="AXI_LITE_IO_axi_fifo_mm_s_0" PORT="axi_str_txd_tready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="AXI_STR_TXD_0_tvalid" SIGIS="undef" SIGNAME="AXI_LITE_IO_axi_fifo_mm_s_0_axi_str_txd_tvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="AXI_LITE_IO_axi_fifo_mm_s_0" PORT="axi_str_txd_tvalid"/>
</CONNECTIONS>
</PORT>
<PORT CLKFREQUENCY="100000000" DIR="I" LEFT="0" NAME="pcie_clk_p" RIGHT="0" SIGIS="clk" SIGNAME="PCIe_util_ds_buf_0_IBUF_DS_P">
<CONNECTIONS>
<CONNECTION INSTANCE="PCIe_util_ds_buf_0" PORT="IBUF_DS_P"/>
</CONNECTIONS>
</PORT>
<PORT CLKFREQUENCY="100000000" DIR="I" LEFT="0" NAME="pcie_clk_n" RIGHT="0" SIGIS="clk" SIGNAME="PCIe_util_ds_buf_0_IBUF_DS_N">
<CONNECTIONS>
<CONNECTION INSTANCE="PCIe_util_ds_buf_0" PORT="IBUF_DS_N"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" LEFT="31" NAME="DDR3_dq" RIGHT="0" SIGIS="undef" SIGNAME="Memory_mig_7series_0_ddr3_dq">
@ -156,74 +201,29 @@
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="ddr3_odt"/>
</CONNECTIONS>
</PORT>
<PORT CLKFREQUENCY="100000000" DIR="I" LEFT="0" NAME="pcie_clk_p" RIGHT="0" SIGIS="clk" SIGNAME="PCIe_util_ds_buf_0_IBUF_DS_P">
<PORT DIR="I" LEFT="3" NAME="pcie_mgt_rxn" RIGHT="0" SIGIS="undef" SIGNAME="PCIe_xdma_0_pci_exp_rxn">
<CONNECTIONS>
<CONNECTION INSTANCE="PCIe_util_ds_buf_0" PORT="IBUF_DS_P"/>
<CONNECTION INSTANCE="PCIe_xdma_0" PORT="pci_exp_rxn"/>
</CONNECTIONS>
</PORT>
<PORT CLKFREQUENCY="100000000" DIR="I" LEFT="0" NAME="pcie_clk_n" RIGHT="0" SIGIS="clk" SIGNAME="PCIe_util_ds_buf_0_IBUF_DS_N">
<PORT DIR="I" LEFT="3" NAME="pcie_mgt_rxp" RIGHT="0" SIGIS="undef" SIGNAME="PCIe_xdma_0_pci_exp_rxp">
<CONNECTIONS>
<CONNECTION INSTANCE="PCIe_util_ds_buf_0" PORT="IBUF_DS_N"/>
<CONNECTION INSTANCE="PCIe_xdma_0" PORT="pci_exp_rxp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="31" NAME="AXI_STR_TXD_0_tdata" RIGHT="0" SIGIS="undef" SIGNAME="AXI_LITE_IO_axi_fifo_mm_s_0_axi_str_txd_tdata">
<PORT DIR="O" LEFT="3" NAME="pcie_mgt_txn" RIGHT="0" SIGIS="undef" SIGNAME="PCIe_xdma_0_pci_exp_txn">
<CONNECTIONS>
<CONNECTION INSTANCE="AXI_LITE_IO_axi_fifo_mm_s_0" PORT="axi_str_txd_tdata"/>
<CONNECTION INSTANCE="PCIe_xdma_0" PORT="pci_exp_txn"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="AXI_STR_TXD_0_tlast" SIGIS="undef" SIGNAME="AXI_LITE_IO_axi_fifo_mm_s_0_axi_str_txd_tlast">
<PORT DIR="O" LEFT="3" NAME="pcie_mgt_txp" RIGHT="0" SIGIS="undef" SIGNAME="PCIe_xdma_0_pci_exp_txp">
<CONNECTIONS>
<CONNECTION INSTANCE="AXI_LITE_IO_axi_fifo_mm_s_0" PORT="axi_str_txd_tlast"/>
<CONNECTION INSTANCE="PCIe_xdma_0" PORT="pci_exp_txp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="AXI_STR_TXD_0_tready" SIGIS="undef" SIGNAME="AXI_LITE_IO_axi_fifo_mm_s_0_axi_str_txd_tready">
<PORT DIR="O" LEFT="31" NAME="gpio_io_o_0" RIGHT="0" SIGIS="undef" SIGNAME="AXI_LITE_IO_axi_gpio_0_gpio_io_o">
<CONNECTIONS>
<CONNECTION INSTANCE="AXI_LITE_IO_axi_fifo_mm_s_0" PORT="axi_str_txd_tready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="AXI_STR_TXD_0_tvalid" SIGIS="undef" SIGNAME="AXI_LITE_IO_axi_fifo_mm_s_0_axi_str_txd_tvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="AXI_LITE_IO_axi_fifo_mm_s_0" PORT="axi_str_txd_tvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="71" NAME="S_AXIS_S2MM_CMD_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_s_axis_s2mm_cmd_tdata">
<CONNECTIONS>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_cmd_tdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXIS_S2MM_CMD_tready" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_s_axis_s2mm_cmd_tready">
<CONNECTIONS>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_cmd_tready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXIS_S2MM_CMD_tvalid" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_s_axis_s2mm_cmd_tvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_cmd_tvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="127" NAME="S_AXIS_S2MM_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_s_axis_s2mm_tdata">
<CONNECTIONS>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_tdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="15" NAME="S_AXIS_S2MM_tkeep" RIGHT="0" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_s_axis_s2mm_tkeep">
<CONNECTIONS>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_tkeep"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXIS_S2MM_tlast" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_s_axis_s2mm_tlast">
<CONNECTIONS>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_tlast"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXIS_S2MM_tready" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_s_axis_s2mm_tready">
<CONNECTIONS>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_tready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXIS_S2MM_tvalid" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_s_axis_s2mm_tvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="s_axis_s2mm_tvalid"/>
<CONNECTION INSTANCE="AXI_LITE_IO_axi_gpio_0" PORT="gpio_io_o"/>
</CONNECTIONS>
</PORT>
</EXTERNALPORTS>
@ -594,7 +594,7 @@
<PARAMETER NAME="C_FAMILY" VALUE="artix7"/>
<PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="9"/>
<PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
<PARAMETER NAME="C_GPIO_WIDTH" VALUE="2"/>
<PARAMETER NAME="C_GPIO_WIDTH" VALUE="32"/>
<PARAMETER NAME="C_GPIO2_WIDTH" VALUE="32"/>
<PARAMETER NAME="C_ALL_INPUTS" VALUE="0"/>
<PARAMETER NAME="C_ALL_INPUTS_2" VALUE="1"/>
@ -710,7 +710,7 @@
<CONNECTION INSTANCE="AXI_LITE_IO_smartconnect_0" PORT="M01_AXI_rready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="gpio_io_o" RIGHT="0" SIGIS="undef" SIGNAME="AXI_LITE_IO_axi_gpio_0_gpio_io_o">
<PORT DIR="O" LEFT="31" NAME="gpio_io_o" RIGHT="0" SIGIS="undef" SIGNAME="AXI_LITE_IO_axi_gpio_0_gpio_io_o">
<CONNECTIONS>
<CONNECTION INSTANCE="External_Ports" PORT="gpio_io_o_0"/>
</CONNECTIONS>
@ -1770,11 +1770,7 @@
<CONNECTION INSTANCE="Memory_axi_interconnect_0" PORT="S01_AXI_awcache"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="m_axi_s2mm_awuser" RIGHT="0" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_m_axi_s2mm_awuser">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_axi_interconnect_0" PORT="S01_AXI_awuser"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="m_axi_s2mm_awuser" RIGHT="0" SIGIS="undef"/>
<PORT DIR="O" NAME="m_axi_s2mm_awvalid" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_m_axi_s2mm_awvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_axi_interconnect_0" PORT="S01_AXI_awvalid"/>
@ -2397,11 +2393,6 @@
</PORT>
<PORT DIR="I" NAME="S01_AXI_awregion" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_awqos" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_awuser" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_m_axi_s2mm_awuser">
<CONNECTIONS>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="m_axi_s2mm_awuser"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S01_AXI_awvalid" SIGIS="undef" SIGNAME="Datamover_axi_datamover_0_m_axi_s2mm_awvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="Datamover_axi_datamover_0" PORT="m_axi_s2mm_awvalid"/>
@ -2678,7 +2669,6 @@
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awqos"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M00_AXI_awuser" SIGIS="undef"/>
<PORT DIR="O" NAME="M00_AXI_awvalid" SIGIS="undef" SIGNAME="Memory_axi_interconnect_0_M00_AXI_awvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="Memory_mig_7series_0" PORT="s_axi_awvalid"/>
@ -2877,7 +2867,6 @@
<PORTMAP LOGICAL="AWPROT" PHYSICAL="M00_AXI_awprot"/>
<PORTMAP LOGICAL="AWREGION" PHYSICAL="M00_AXI_awregion"/>
<PORTMAP LOGICAL="AWQOS" PHYSICAL="M00_AXI_awqos"/>
<PORTMAP LOGICAL="AWUSER" PHYSICAL="M00_AXI_awuser"/>
<PORTMAP LOGICAL="AWVALID" PHYSICAL="M00_AXI_awvalid"/>
<PORTMAP LOGICAL="AWREADY" PHYSICAL="M00_AXI_awready"/>
<PORTMAP LOGICAL="WDATA" PHYSICAL="M00_AXI_wdata"/>
@ -2921,7 +2910,6 @@
<PORTMAP LOGICAL="AWPROT" PHYSICAL="S01_AXI_awprot"/>
<PORTMAP LOGICAL="AWREGION" PHYSICAL="S01_AXI_awregion"/>
<PORTMAP LOGICAL="AWQOS" PHYSICAL="S01_AXI_awqos"/>
<PORTMAP LOGICAL="AWUSER" PHYSICAL="S01_AXI_awuser"/>
<PORTMAP LOGICAL="AWVALID" PHYSICAL="S01_AXI_awvalid"/>
<PORTMAP LOGICAL="AWREADY" PHYSICAL="S01_AXI_awready"/>
<PORTMAP LOGICAL="WDATA" PHYSICAL="S01_AXI_wdata"/>

8
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl
View File

@ -662,7 +662,7 @@ proc create_hier_cell_AXI_LITE_IO { parentCell nameHier } {
create_bd_pin -dir I -type rst axi_resetn
create_bd_pin -dir I -from 31 -to 0 gpio2_io_i
create_bd_pin -dir I -from 31 -to 0 gpio2_io_i_0
create_bd_pin -dir O -from 1 -to 0 gpio_io_o_0
create_bd_pin -dir O -from 31 -to 0 gpio_io_o_0
create_bd_pin -dir O -from 31 -to 0 gpio_io_o_1
# Create instance: axi_fifo_mm_s_0, and set properties
@ -677,7 +677,7 @@ proc create_hier_cell_AXI_LITE_IO { parentCell nameHier } {
set_property -dict [ list \
CONFIG.C_ALL_INPUTS_2 {1} \
CONFIG.C_ALL_OUTPUTS {1} \
CONFIG.C_GPIO_WIDTH {2} \
CONFIG.C_GPIO_WIDTH {32} \
CONFIG.C_IS_DUAL {1} \
] $axi_gpio_0
@ -796,7 +796,7 @@ proc create_root_design { parentCell } {
set axi_aresetn [ create_bd_port -dir O axi_aresetn ]
set gpio2_io_i [ create_bd_port -dir I -from 31 -to 0 gpio2_io_i ]
set gpio2_io_i_0 [ create_bd_port -dir I -from 31 -to 0 gpio2_io_i_0 ]
set gpio_io_o_0 [ create_bd_port -dir O -from 1 -to 0 gpio_io_o_0 ]
set gpio_io_o_0 [ create_bd_port -dir O -from 31 -to 0 gpio_io_o_0 ]
set gpio_io_o_1 [ create_bd_port -dir O -from 31 -to 0 gpio_io_o_1 ]
set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ]
set s2mm_err [ create_bd_port -dir O s2mm_err ]
@ -827,12 +827,12 @@ proc create_root_design { parentCell } {
connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pcie_mgt] [get_bd_intf_pins PCIe/pcie_mgt]
# Create port connections
connect_bd_net -net AXI_LITE_IO_gpio_io_o_0 [get_bd_ports gpio_io_o_0] [get_bd_pins AXI_LITE_IO/gpio_io_o_0]
connect_bd_net -net AXI_LITE_IO_gpio_io_o_1 [get_bd_ports gpio_io_o_1] [get_bd_pins AXI_LITE_IO/gpio_io_o_1]
connect_bd_net -net Datamover_s2mm_err_0 [get_bd_ports s2mm_err] [get_bd_pins Datamover/s2mm_err]
connect_bd_net -net Datamover_s2mm_wr_xfer_cmplt_0 [get_bd_ports s2mm_wr_xfer_cmplt] [get_bd_pins Datamover/s2mm_wr_xfer_cmplt]
connect_bd_net -net PCIe_axi_aresetn [get_bd_ports axi_aresetn] [get_bd_pins AXI_LITE_IO/axi_resetn] [get_bd_pins Memory/S00_ARESETN] [get_bd_pins PCIe/axi_aresetn]
connect_bd_net -net S01_ARESETN_0_1 [get_bd_ports S01_ARESETN] [get_bd_pins Datamover/axi_aresetn] [get_bd_pins Memory/S01_ARESETN]
connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_ports gpio_io_o_0] [get_bd_pins AXI_LITE_IO/gpio_io_o_0]
connect_bd_net -net gpio2_io_i_0_1 [get_bd_ports gpio2_io_i] [get_bd_pins AXI_LITE_IO/gpio2_io_i]
connect_bd_net -net gpio2_io_i_0_2 [get_bd_ports gpio2_io_i_0] [get_bd_pins AXI_LITE_IO/gpio2_io_i_0]
connect_bd_net -net s2mm_halt_0_1 [get_bd_ports s2mm_halt] [get_bd_pins Datamover/s2mm_halt]

BIN
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_auto_cc_0/design_1_auto_cc_0.dcp
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18
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_auto_cc_0/design_1_auto_cc_0.xml
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@ -1627,7 +1627,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:49 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1645,7 +1645,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:50 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1665,7 +1665,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:50 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1691,7 +1691,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:49 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1711,7 +1711,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:50 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1739,7 +1739,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:50 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1759,7 +1759,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:50 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1782,7 +1782,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:50 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1800,7 +1800,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:59:28 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:14:44 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>

4
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_auto_cc_0/design_1_auto_cc_0_sim_netlist.v
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@ -1,10 +1,10 @@
// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
// Date : Mon Mar 22 18:59:27 2021
// Date : Tue Mar 23 12:14:43 2021
// Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3_4KB/dso_top_ddr3.srcs/sources_1/bd/design_1/ip/design_1_auto_cc_0/design_1_auto_cc_0_sim_netlist.v
// c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3/dso_top_ddr3.srcs/sources_1/bd/design_1/ip/design_1_auto_cc_0/design_1_auto_cc_0_sim_netlist.v
// Design : design_1_auto_cc_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.

4
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_auto_cc_0/design_1_auto_cc_0_sim_netlist.vhdl
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@ -1,10 +1,10 @@
-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
-- Date : Mon Mar 22 18:59:28 2021
-- Date : Tue Mar 23 12:14:43 2021
-- Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3_4KB/dso_top_ddr3.srcs/sources_1/bd/design_1/ip/design_1_auto_cc_0/design_1_auto_cc_0_sim_netlist.vhdl
-- c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3/dso_top_ddr3.srcs/sources_1/bd/design_1/ip/design_1_auto_cc_0/design_1_auto_cc_0_sim_netlist.vhdl
-- Design : design_1_auto_cc_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.

4
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_auto_cc_0/design_1_auto_cc_0_stub.v
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@ -1,10 +1,10 @@
// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
// Date : Mon Mar 22 18:59:27 2021
// Date : Tue Mar 23 12:14:43 2021
// Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3_4KB/dso_top_ddr3.srcs/sources_1/bd/design_1/ip/design_1_auto_cc_0/design_1_auto_cc_0_stub.v
// c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3/dso_top_ddr3.srcs/sources_1/bd/design_1/ip/design_1_auto_cc_0/design_1_auto_cc_0_stub.v
// Design : design_1_auto_cc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tfgg484-2

4
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_auto_cc_0/design_1_auto_cc_0_stub.vhdl
View File

@ -1,10 +1,10 @@
-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
-- Date : Mon Mar 22 18:59:27 2021
-- Date : Tue Mar 23 12:14:43 2021
-- Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3_4KB/dso_top_ddr3.srcs/sources_1/bd/design_1/ip/design_1_auto_cc_0/design_1_auto_cc_0_stub.vhdl
-- c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3/dso_top_ddr3.srcs/sources_1/bd/design_1/ip/design_1_auto_cc_0/design_1_auto_cc_0_stub.vhdl
-- Design : design_1_auto_cc_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a100tfgg484-2

BIN
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_auto_us_df_0/design_1_auto_us_df_0.dcp
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18
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_auto_us_df_0/design_1_auto_us_df_0.xml
View File

@ -1519,7 +1519,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:49 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1537,7 +1537,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:49 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1557,7 +1557,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:49 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1601,7 +1601,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:49 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1621,7 +1621,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:49 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1649,7 +1649,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:49 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1669,7 +1669,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:49 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1692,7 +1692,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:49 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1710,7 +1710,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:59:59 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:15:11 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>

4
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_auto_us_df_0/design_1_auto_us_df_0_sim_netlist.v
View File

@ -1,10 +1,10 @@
// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
// Date : Mon Mar 22 18:59:58 2021
// Date : Tue Mar 23 12:15:10 2021
// Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3_4KB/dso_top_ddr3.srcs/sources_1/bd/design_1/ip/design_1_auto_us_df_0/design_1_auto_us_df_0_sim_netlist.v
// c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3/dso_top_ddr3.srcs/sources_1/bd/design_1/ip/design_1_auto_us_df_0/design_1_auto_us_df_0_sim_netlist.v
// Design : design_1_auto_us_df_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.

4
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_auto_us_df_0/design_1_auto_us_df_0_sim_netlist.vhdl
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@ -1,10 +1,10 @@
-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
-- Date : Mon Mar 22 18:59:59 2021
-- Date : Tue Mar 23 12:15:11 2021
-- Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3_4KB/dso_top_ddr3.srcs/sources_1/bd/design_1/ip/design_1_auto_us_df_0/design_1_auto_us_df_0_sim_netlist.vhdl
-- c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3/dso_top_ddr3.srcs/sources_1/bd/design_1/ip/design_1_auto_us_df_0/design_1_auto_us_df_0_sim_netlist.vhdl
-- Design : design_1_auto_us_df_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.

4
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_auto_us_df_0/design_1_auto_us_df_0_stub.v
View File

@ -1,10 +1,10 @@
// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
// Date : Mon Mar 22 18:59:58 2021
// Date : Tue Mar 23 12:15:10 2021
// Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3_4KB/dso_top_ddr3.srcs/sources_1/bd/design_1/ip/design_1_auto_us_df_0/design_1_auto_us_df_0_stub.v
// c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3/dso_top_ddr3.srcs/sources_1/bd/design_1/ip/design_1_auto_us_df_0/design_1_auto_us_df_0_stub.v
// Design : design_1_auto_us_df_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tfgg484-2

4
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_auto_us_df_0/design_1_auto_us_df_0_stub.vhdl
View File

@ -1,10 +1,10 @@
-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
-- Date : Mon Mar 22 18:59:58 2021
-- Date : Tue Mar 23 12:15:10 2021
-- Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3_4KB/dso_top_ddr3.srcs/sources_1/bd/design_1/ip/design_1_auto_us_df_0/design_1_auto_us_df_0_stub.vhdl
-- c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3/dso_top_ddr3.srcs/sources_1/bd/design_1/ip/design_1_auto_us_df_0/design_1_auto_us_df_0_stub.vhdl
-- Design : design_1_auto_us_df_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a100tfgg484-2

BIN
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_auto_us_df_1/design_1_auto_us_df_1.dcp
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18
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_auto_us_df_1/design_1_auto_us_df_1.xml
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@ -1519,7 +1519,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:49 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1537,7 +1537,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:49 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1557,7 +1557,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:49 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1601,7 +1601,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:49 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1621,7 +1621,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:49 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1649,7 +1649,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:49 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1669,7 +1669,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:49 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1692,7 +1692,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:57:45 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:13:49 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@ -1710,7 +1710,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Mar 22 22:59:51 UTC 2021</spirit:value>
<spirit:value>Tue Mar 23 16:15:03 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>

4
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_auto_us_df_1/design_1_auto_us_df_1_sim_netlist.v
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@ -1,10 +1,10 @@
// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
// Date : Mon Mar 22 18:59:51 2021
// Date : Tue Mar 23 12:15:03 2021
// Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3_4KB/dso_top_ddr3.srcs/sources_1/bd/design_1/ip/design_1_auto_us_df_1/design_1_auto_us_df_1_sim_netlist.v
// c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3/dso_top_ddr3.srcs/sources_1/bd/design_1/ip/design_1_auto_us_df_1/design_1_auto_us_df_1_sim_netlist.v
// Design : design_1_auto_us_df_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.

4
Firmware/Artix7_PCIe/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_auto_us_df_1/design_1_auto_us_df_1_sim_netlist.vhdl
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@ -1,10 +1,10 @@
-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
-- Date : Mon Mar 22 18:59:51 2021
-- Date : Tue Mar 23 12:15:03 2021
-- Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3_4KB/dso_top_ddr3.srcs/sources_1/bd/design_1/ip/design_1_auto_us_df_1/design_1_auto_us_df_1_sim_netlist.vhdl
-- c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/dso_top_ddr3/dso_top_ddr3.srcs/sources_1/bd/design_1/ip/design_1_auto_us_df_1/design_1_auto_us_df_1_sim_netlist.vhdl
-- Design : design_1_auto_us_df_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.

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