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Added flash utily to HW for firmware updates

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This commit is contained in:
Andrew E Wilson 2024-01-30 12:11:40 -07:00
parent e1e293eab0
commit c99683304b
9 changed files with 469 additions and 30 deletions

9
Firmware/XDMA/README.md
View File

@ -12,4 +12,11 @@ Then run `src ./xdma_gen.tcl <target> <threads>`
* Threads (Default is 6) If threads is used, target must be used
* `1`
* `...`
* `16`
* `16`
## TODO:
* Check SPI clk for Flash write.
* Update MCS file decode.
* look at quad writes and reads for frimware updates.

44
Firmware/XDMA/bd/top_bd.tcl
View File

@ -138,6 +138,7 @@ xilinx.com:ip:axi_clock_converter:2.1\
xilinx.com:ip:axi_datamover:5.1\
xilinx.com:ip:axi_gpio:2.0\
xilinx.com:ip:axi_fifo_mm_s:4.3\
xilinx.com:ip:axi_quad_spi:3.2\
xilinx.com:ip:util_ds_buf:2.2\
xilinx.com:ip:axi_dwidth_converter:2.1\
xilinx.com:ip:xdma:4.1\
@ -184,7 +185,7 @@ proc write_mig_file_design_1_mig_7series_0_0 { str_mig_prj_filepath } {
puts $mig_prj_file { <dci_inputs>1</dci_inputs>}
puts $mig_prj_file { <Debug_En>OFF</Debug_En>}
puts $mig_prj_file { <DataDepth_En>1024</DataDepth_En>}
puts $mig_prj_file { <LowPower_En>ON</LowPower_En>}
puts $mig_prj_file { <LowPower_En>OFF</LowPower_En>}
puts $mig_prj_file { <XADC_En>Enabled</XADC_En>}
puts $mig_prj_file { <TargetFPGA>xc7a100t-fgg484/-2</TargetFPGA>}
puts $mig_prj_file { <Version>4.2</Version>}
@ -195,12 +196,6 @@ proc write_mig_file_design_1_mig_7series_0_0 { str_mig_prj_filepath } {
puts $mig_prj_file { <InternalVref>0</InternalVref>}
puts $mig_prj_file { <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>}
puts $mig_prj_file { <dci_cascade>0</dci_cascade>}
puts $mig_prj_file { <FPGADevice>}
puts $mig_prj_file { <selected>7a/xc7a35t-fgg484</selected>}
puts $mig_prj_file { <selected>7a/xc7a50t-fgg484</selected>}
puts $mig_prj_file { <selected>7a/xc7a75t-fgg484</selected>}
puts $mig_prj_file { <selected>7a/xc7a15t-fgg484</selected>}
puts $mig_prj_file { </FPGADevice>}
puts $mig_prj_file { <Controller number="0">}
puts $mig_prj_file { <MemoryDevice>DDR3_SDRAM/Components/MT41K256M16XX-125</MemoryDevice>}
puts $mig_prj_file { <TimePeriod>2500</TimePeriod>}
@ -218,8 +213,8 @@ proc write_mig_file_design_1_mig_7series_0_0 { str_mig_prj_filepath } {
puts $mig_prj_file { <DeepMemory>1</DeepMemory>}
puts $mig_prj_file { <DataMask>1</DataMask>}
puts $mig_prj_file { <ECC>Disabled</ECC>}
puts $mig_prj_file { <Ordering>Strict</Ordering>}
puts $mig_prj_file { <BankMachineCnt>3</BankMachineCnt>}
puts $mig_prj_file { <Ordering>Normal</Ordering>}
puts $mig_prj_file { <BankMachineCnt>8</BankMachineCnt>}
puts $mig_prj_file { <CustomPart>FALSE</CustomPart>}
puts $mig_prj_file { <NewPartName/>}
puts $mig_prj_file { <RowAddress>15</RowAddress>}
@ -507,12 +502,15 @@ proc create_hier_cell_AXI_LITE_IO { parentCell nameHier } {
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 AXI_STR_TXD_0
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:spi_rtl:1.0 SPI_0_0
# Create pins
create_bd_pin -dir I -from 31 -to 0 gpio2_io_i
create_bd_pin -dir I -type clk axi_aclk
create_bd_pin -dir I -type rst axi_resetn
create_bd_pin -dir O -from 31 -to 0 gpio_io_o_0
create_bd_pin -dir O -from 0 -to 0 ss_o_0
# Create instance: axi_gpio_0, and set properties
set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
@ -565,8 +563,6 @@ proc create_hier_cell_AXI_LITE_IO { parentCell nameHier } {
CONFIG.M01_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A00_ADDR_WIDTH {0} \
CONFIG.M02_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A03_BASE_ADDR {0xffffffffffffffff} \
@ -582,8 +578,6 @@ proc create_hier_cell_AXI_LITE_IO { parentCell nameHier } {
CONFIG.M02_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_READ_ISSUING {1} \
CONFIG.M02_WRITE_ISSUING {1} \
CONFIG.M03_A00_ADDR_WIDTH {0} \
CONFIG.M03_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A01_BASE_ADDR {0xffffffffffffffff} \
@ -831,7 +825,7 @@ proc create_hier_cell_AXI_LITE_IO { parentCell nameHier } {
CONFIG.M15_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_READ_ISSUING {1} \
CONFIG.M15_WRITE_ISSUING {1} \
CONFIG.NUM_MI {2} \
CONFIG.NUM_MI {3} \
CONFIG.S01_READ_ACCEPTANCE {1} \
CONFIG.S01_WRITE_ACCEPTANCE {1} \
CONFIG.S02_READ_ACCEPTANCE {1} \
@ -866,16 +860,28 @@ proc create_hier_cell_AXI_LITE_IO { parentCell nameHier } {
] $axi_crossbar_0
# Create instance: axi_quad_spi_0, and set properties
set axi_quad_spi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_quad_spi_0 ]
set_property -dict [list \
CONFIG.C_FIFO_DEPTH {256} \
CONFIG.C_SPI_MEMORY {2} \
CONFIG.C_SPI_MODE {2} \
] $axi_quad_spi_0
# Create interface connections
connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins AXI_STR_TXD_0] [get_bd_intf_pins axi_fifo_mm_s_0/AXI_STR_TXD]
connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins axi_quad_spi_0/SPI_0] [get_bd_intf_pins SPI_0_0]
connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins S00_AXI] [get_bd_intf_pins axi_crossbar_0/S00_AXI]
connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI [get_bd_intf_pins axi_crossbar_0/M00_AXI] [get_bd_intf_pins axi_fifo_mm_s_0/S_AXI]
connect_bd_intf_net -intf_net axi_crossbar_0_M01_AXI [get_bd_intf_pins axi_crossbar_0/M01_AXI] [get_bd_intf_pins axi_gpio_0/S_AXI]
connect_bd_intf_net -intf_net axi_crossbar_0_M02_AXI [get_bd_intf_pins axi_quad_spi_0/AXI_LITE] [get_bd_intf_pins axi_crossbar_0/M02_AXI]
# Create port connections
connect_bd_net -net axi_aclk_1 [get_bd_pins axi_aclk] [get_bd_pins axi_crossbar_0/aclk] [get_bd_pins axi_fifo_mm_s_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk]
connect_bd_net -net axi_aclk_1 [get_bd_pins axi_aclk] [get_bd_pins axi_crossbar_0/aclk] [get_bd_pins axi_fifo_mm_s_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_quad_spi_0/ext_spi_clk] [get_bd_pins axi_quad_spi_0/s_axi_aclk]
connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins gpio_io_o_0]
connect_bd_net -net axi_resetn_1 [get_bd_pins axi_resetn] [get_bd_pins axi_crossbar_0/aresetn] [get_bd_pins axi_fifo_mm_s_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn]
connect_bd_net -net axi_quad_spi_0_ss_o [get_bd_pins axi_quad_spi_0/ss_o] [get_bd_pins ss_o_0]
connect_bd_net -net axi_resetn_1 [get_bd_pins axi_resetn] [get_bd_pins axi_crossbar_0/aresetn] [get_bd_pins axi_fifo_mm_s_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_quad_spi_0/s_axi_aresetn]
connect_bd_net -net gpio2_io_i_1 [get_bd_pins gpio2_io_i] [get_bd_pins axi_gpio_0/gpio2_io_i]
# Restore current instance
@ -1449,6 +1455,8 @@ proc create_root_design { parentCell } {
CONFIG.TUSER_WIDTH {0} \
] $S_AXIS_S2MM
set SPI_0_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:spi_rtl:1.0 SPI_0_0 ]
# Create ports
set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ]
@ -1460,6 +1468,7 @@ proc create_root_design { parentCell } {
set s2mm_halt [ create_bd_port -dir I s2mm_halt ]
set axi_aclk [ create_bd_port -dir O -type clk axi_aclk ]
set gpio_io_o_0 [ create_bd_port -dir O -from 31 -to 0 gpio_io_o_0 ]
set ss_o_0 [ create_bd_port -dir O -from 0 -to 0 ss_o_0 ]
# Create instance: Memory
create_hier_cell_Memory [current_bd_instance .] Memory
@ -1475,6 +1484,7 @@ proc create_root_design { parentCell } {
# Create interface connections
connect_bd_intf_net -intf_net AXI_LITE_IO_AXI_STR_TXD_0 [get_bd_intf_ports AXI_STR_TXD_0] [get_bd_intf_pins AXI_LITE_IO/AXI_STR_TXD_0]
connect_bd_intf_net -intf_net AXI_LITE_IO_SPI_0_0 [get_bd_intf_ports SPI_0_0] [get_bd_intf_pins AXI_LITE_IO/SPI_0_0]
connect_bd_intf_net -intf_net CLK_IN_D_0_1 [get_bd_intf_ports pcie] [get_bd_intf_pins PCIe/pcie]
connect_bd_intf_net -intf_net Datamover_M_AXI_S2MM [get_bd_intf_pins Datamover/M_AXI_S2MM] [get_bd_intf_pins Memory/S01_AXI]
connect_bd_intf_net -intf_net PCIe_M_AXI_LITE [get_bd_intf_pins PCIe/M_AXI_LITE] [get_bd_intf_pins AXI_LITE_IO/S00_AXI]
@ -1486,6 +1496,7 @@ proc create_root_design { parentCell } {
# Create port connections
connect_bd_net -net AXI_LITE_IO_gpio_io_o_0 [get_bd_pins AXI_LITE_IO/gpio_io_o_0] [get_bd_ports gpio_io_o_0]
connect_bd_net -net AXI_LITE_IO_ss_o_0 [get_bd_pins AXI_LITE_IO/ss_o_0] [get_bd_ports ss_o_0]
connect_bd_net -net Datamover_s2mm_err_0 [get_bd_pins Datamover/s2mm_err] [get_bd_ports s2mm_err]
connect_bd_net -net Datamover_s2mm_wr_xfer_cmplt_0 [get_bd_pins Datamover/s2mm_wr_xfer_cmplt] [get_bd_ports s2mm_wr_xfer_cmplt]
connect_bd_net -net PCIe_axi_aresetn [get_bd_pins PCIe/axi_aresetn] [get_bd_pins Memory/S00_ARESETN] [get_bd_ports axi_aresetn] [get_bd_pins AXI_LITE_IO/axi_resetn]
@ -1500,6 +1511,7 @@ proc create_root_design { parentCell } {
assign_bd_address -offset 0x00000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces PCIe/xdma_0/M_AXI] [get_bd_addr_segs Memory/mig_7series_0/memmap/memaddr] -force
assign_bd_address -offset 0x40020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces PCIe/xdma_0/M_AXI_LITE] [get_bd_addr_segs AXI_LITE_IO/axi_fifo_mm_s_0/S_AXI/Mem0] -force
assign_bd_address -offset 0x40000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces PCIe/xdma_0/M_AXI_LITE] [get_bd_addr_segs AXI_LITE_IO/axi_gpio_0/S_AXI/Reg] -force
assign_bd_address -offset 0x40040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces PCIe/xdma_0/M_AXI_LITE] [get_bd_addr_segs AXI_LITE_IO/axi_quad_spi_0/AXI_LITE/Reg] -force
# Restore current instance

68
Firmware/XDMA/hdl/100t_200t/dso_top.v
View File

@ -39,11 +39,16 @@ module dso_top
output fe_en,
output probe_comp,
input adc_lclk_p,
input adc_lclk_n,
input adc_fclk_p,
input adc_fclk_n,
input[7:0] adc_data_p,
input[7:0] adc_data_n
input adc_lclk_n,
input adc_fclk_p,
input adc_fclk_n,
input[7:0] adc_data_p,
input[7:0] adc_data_n,
inout qspi_d0,
inout qspi_d1,
inout qspi_d2,
inout qspi_d3,
output qspi_cs
);
wire [31:0]AXI_STR_TXD_0_tdata;
@ -79,6 +84,23 @@ module dso_top
reg[63:0] adc_data;
wire serdes_ready;
wire spi_rtl_0_io0_i;
wire spi_rtl_0_io0_io;
wire spi_rtl_0_io0_o;
wire spi_rtl_0_io0_t;
wire spi_rtl_0_io1_i;
wire spi_rtl_0_io1_io;
wire spi_rtl_0_io1_o;
wire spi_rtl_0_io1_t;
wire spi_rtl_0_io2_i;
wire spi_rtl_0_io2_io;
wire spi_rtl_0_io2_o;
wire spi_rtl_0_io2_t;
wire spi_rtl_0_io3_i;
wire spi_rtl_0_io3_io;
wire spi_rtl_0_io3_o;
wire spi_rtl_0_io3_t;
assign term = gpio_io_o_0[15:12];
assign atten = gpio_io_o_0[19:16];
assign dc_cpl = gpio_io_o_0[23:20];
@ -266,7 +288,41 @@ module dso_top
.pcie_perstn(pcie_perstn),
.s2mm_err(s2mm_err),
.s2mm_halt(s2mm_halt),
.s2mm_wr_xfer_cmplt(s2mm_wr_xfer_cmplt)
.s2mm_wr_xfer_cmplt(s2mm_wr_xfer_cmplt),
.SPI_0_0_io0_i(spi_rtl_0_io0_i),
.SPI_0_0_io0_o(spi_rtl_0_io0_o),
.SPI_0_0_io0_t(spi_rtl_0_io0_t),
.SPI_0_0_io1_i(spi_rtl_0_io1_i),
.SPI_0_0_io1_o(spi_rtl_0_io1_o),
.SPI_0_0_io1_t(spi_rtl_0_io1_t),
.SPI_0_0_io2_i(spi_rtl_0_io2_i),
.SPI_0_0_io2_o(spi_rtl_0_io2_o),
.SPI_0_0_io2_t(spi_rtl_0_io2_t),
.SPI_0_0_io3_i(spi_rtl_0_io3_i),
.SPI_0_0_io3_o(spi_rtl_0_io3_o),
.SPI_0_0_io3_t(spi_rtl_0_io3_t),
.SPI_0_0_ss_t(1'b0),
.ss_o_0(qspi_cs)
);
IOBUF spi_rtl_0_io0_iobuf
(.I(spi_rtl_0_io0_o),
.IO(qspi_d0),
.O(spi_rtl_0_io0_i),
.T(spi_rtl_0_io0_t));
IOBUF spi_rtl_0_io1_iobuf
(.I(spi_rtl_0_io1_o),
.IO(qspi_d1),
.O(spi_rtl_0_io1_i),
.T(spi_rtl_0_io1_t));
IOBUF spi_rtl_0_io2_iobuf
(.I(spi_rtl_0_io2_o),
.IO(qspi_d2),
.O(spi_rtl_0_io2_i),
.T(spi_rtl_0_io2_t));
IOBUF spi_rtl_0_io3_iobuf
(.I(spi_rtl_0_io3_o),
.IO(qspi_d3),
.O(spi_rtl_0_io3_i),
.T(spi_rtl_0_io3_t));
endmodule

69
Firmware/XDMA/hdl/35t_50t/dso_top.v
View File

@ -39,11 +39,16 @@ module dso_top
output fe_en,
output probe_comp,
input adc_lclk_p,
input adc_lclk_n,
input adc_fclk_p,
input adc_fclk_n,
input[7:0] adc_data_p,
input[7:0] adc_data_n
input adc_lclk_n,
input adc_fclk_p,
input adc_fclk_n,
input[7:0] adc_data_p,
input[7:0] adc_data_n,
inout qspi_d0,
inout qspi_d1,
inout qspi_d2,
inout qspi_d3,
output qspi_cs
);
wire [31:0]AXI_STR_TXD_0_tdata;
@ -79,6 +84,23 @@ module dso_top
reg[63:0] adc_data;
wire serdes_ready;
wire spi_rtl_0_io0_i;
wire spi_rtl_0_io0_io;
wire spi_rtl_0_io0_o;
wire spi_rtl_0_io0_t;
wire spi_rtl_0_io1_i;
wire spi_rtl_0_io1_io;
wire spi_rtl_0_io1_o;
wire spi_rtl_0_io1_t;
wire spi_rtl_0_io2_i;
wire spi_rtl_0_io2_io;
wire spi_rtl_0_io2_o;
wire spi_rtl_0_io2_t;
wire spi_rtl_0_io3_i;
wire spi_rtl_0_io3_io;
wire spi_rtl_0_io3_o;
wire spi_rtl_0_io3_t;
assign term = gpio_io_o_0[15:12];
assign atten = gpio_io_o_0[19:16];
assign dc_cpl = gpio_io_o_0[23:20];
@ -266,7 +288,42 @@ module dso_top
.pcie_perstn(pcie_perstn),
.s2mm_err(s2mm_err),
.s2mm_halt(s2mm_halt),
.s2mm_wr_xfer_cmplt(s2mm_wr_xfer_cmplt)
.s2mm_wr_xfer_cmplt(s2mm_wr_xfer_cmplt),
.SPI_0_0_io0_i(spi_rtl_0_io0_i),
.SPI_0_0_io0_o(spi_rtl_0_io0_o),
.SPI_0_0_io0_t(spi_rtl_0_io0_t),
.SPI_0_0_io1_i(spi_rtl_0_io1_i),
.SPI_0_0_io1_o(spi_rtl_0_io1_o),
.SPI_0_0_io1_t(spi_rtl_0_io1_t),
.SPI_0_0_io2_i(spi_rtl_0_io2_i),
.SPI_0_0_io2_o(spi_rtl_0_io2_o),
.SPI_0_0_io2_t(spi_rtl_0_io2_t),
.SPI_0_0_io3_i(spi_rtl_0_io3_i),
.SPI_0_0_io3_o(spi_rtl_0_io3_o),
.SPI_0_0_io3_t(spi_rtl_0_io3_t),
.SPI_0_0_ss_t(1'b0),
.ss_o_0(qspi_cs)
);
IOBUF spi_rtl_0_io0_iobuf
(.I(spi_rtl_0_io0_o),
.IO(qspi_d0),
.O(spi_rtl_0_io0_i),
.T(spi_rtl_0_io0_t));
IOBUF spi_rtl_0_io1_iobuf
(.I(spi_rtl_0_io1_o),
.IO(qspi_d1),
.O(spi_rtl_0_io1_i),
.T(spi_rtl_0_io1_t));
IOBUF spi_rtl_0_io2_iobuf
(.I(spi_rtl_0_io2_o),
.IO(qspi_d2),
.O(spi_rtl_0_io2_i),
.T(spi_rtl_0_io2_t));
IOBUF spi_rtl_0_io3_iobuf
(.I(spi_rtl_0_io3_o),
.IO(qspi_d3),
.O(spi_rtl_0_io3_i),
.T(spi_rtl_0_io3_t));
endmodule

28
Firmware/XDMA/utils/pcie_mem_util.py Normal file
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@ -0,0 +1,28 @@
import os
import mmap
import numpy as np
class pcie_mem:
def __init__(self,offset,size=0x10000):
self.offset = offset
self.size = size
mmap_file = os.open('/dev/mem', os.O_RDWR | os.O_SYNC)
mem = mmap.mmap(mmap_file, self.size,
mmap.MAP_SHARED,
mmap.PROT_READ | mmap.PROT_WRITE,
offset=self.offset)
os.close(mmap_file)
self.array = np.frombuffer(mem, np.uint32, self.size >> 2)
def wread(self,address):
idx = address >> 2
#print(hex(self.offset+address))
return_val = int(self.array[idx])
return return_val
def wwrite(self,address,data):
idx = address >> 2
#print(hex(self.offset+address))
self.array[idx] = np.uint32(data)

244
Firmware/XDMA/utils/qspi.py Normal file
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@ -0,0 +1,244 @@
from pcie_mem_util import *
import re
class QSPI:
#REGS
REG_RST = 0x40
REG_CR = 0x60
REG_SR = 0x64
REG_DTR = 0x68
REG_DRR = 0x6C
REG_SSR = 0x70
REG_DTO = 0x74
REG_DRO = 0x78
#MASK
REG_RST_MASK = 0xA
REG_CR_OFF = 0x186
REG_CR_ON = 0x086
REG_SR_RXE = 0x00000001
REG_SR_RXF = 0x00000002
REG_SR_TXE = 0x00000004
REG_SR_TXF = 0x00000008
REG_SSR_CEN = 0xFFFFFFFE
REG_SSR_CEF = 0xFFFFFFFF
#FLASH CMDS
CMD_READ_ID = 0x90
CMD_RDID = 0x9F
CMD_READ = 0x13
CMD_SECTOR_ERASE = 0xDC
CMD_STATUSREG_CLEAR = 0x30
CMD_STATUSREG_READ = 0x05
CMD_PAGEPROGRAM_WRITE = 0x12
SR_IS_READY_MASK = 0x01
CMD_WRITE_ENABLE = 0x06
def __init__ (self,device_offset,base_offset):
self.device_offset = device_offset
self.base_offset = base_offset
self.reset()
#Dummy read
self.read_id()
self.flash_id = self.read_id()
self.falsh_info = self.device_info_read()
print(hex(self.flash_id))
n2ps = self.falsh_info[0x20]
if (n2ps == 0x8):
self.page_size = 0x100
else:
self.page_size = 0x200
n2ss = self.falsh_info[0x21]
if (n2ss == 0x8):
self.sector_size = 64*1024
else:
self.sector_size = 256*1024
print(hex(self.sector_size))
print(hex(self.random_read(0x0)[0x23]))
print(self.is_busy())
self.status_clear()
#if (self.load_mcs("page.mcs",verify_only=True)):
# self.load_mcs("page.mcs")
print(hex(self.random_read(0x0)[0x23]))
#read_arry = self.random_read(0x0)
#for i in range(len(read_arry)):
# print(hex(i),hex(read_arry[i]))
def reset(self):
mem = pcie_mem(self.device_offset+self.base_offset)
mem.wwrite(self.REG_RST,self.REG_RST_MASK)
mem.wwrite(self.REG_SSR,self.REG_SSR_CEF)
mem.wwrite(self.REG_CR,self.REG_CR_OFF)
def issue_cmd(self,cmd,readback = 0):
#get pcie memory
mem = pcie_mem(self.device_offset+self.base_offset)
#write cmd section
#enable CE
mem.wwrite(self.REG_SSR,self.REG_SSR_CEN)
#write cmd sequence until full or end of sequence, issue and start again
cmd_idx = 0
while(cmd_idx<len(cmd)):
while(cmd_idx<len(cmd) and (mem.wread(self.REG_SR)&self.REG_SR_TXF)!=self.REG_SR_TXF):
mem.wwrite(self.REG_DTR,cmd[cmd_idx])
#print(hex(cmd[cmd_idx]))
cmd_idx += 1
#start
mem.wwrite(self.REG_CR,self.REG_CR_ON)
#go until empty
while((mem.wread(self.REG_SR)&self.REG_SR_TXE)!=self.REG_SR_TXE):
pass
#stop
mem.wwrite(self.REG_CR,self.REG_CR_OFF)
#empty RX (all garabge data during cmd issue
while((mem.wread(self.REG_SR)&self.REG_SR_RXE)!=self.REG_SR_RXE):
mem.wread(self.REG_DRR)
#read
read_idx = 0
return_val = []
while(read_idx<readback):
while(read_idx<readback and (mem.wread(self.REG_SR)&self.REG_SR_TXF)!=self.REG_SR_TXF):
mem.wwrite(self.REG_DTR,0x0)
read_idx += 1
#start
mem.wwrite(self.REG_CR,self.REG_CR_ON)
#go until empty
while((mem.wread(self.REG_SR)&self.REG_SR_TXE)!=self.REG_SR_TXE):
pass
#stop
mem.wwrite(self.REG_CR,self.REG_CR_OFF)
#read RX
while((mem.wread(self.REG_SR)&self.REG_SR_RXE)!=self.REG_SR_RXE):
return_val.append(mem.wread(self.REG_DRR))
#print(hex(return_val[-1]))
#turn off CE
mem.wwrite(self.REG_SSR,self.REG_SSR_CEF)
return return_val
def read_id(self):
cmd = [self.CMD_READ_ID,0,0,0]
return_val = self.issue_cmd(cmd,2)[1]
return return_val
def device_info_read(self):
cmd = [self.CMD_RDID]
return_val = self.issue_cmd(cmd,0x51)
return return_val
def random_read(self,addr,length=256):
cmd = [self.CMD_READ]
addr = int.to_bytes(addr,4,'big')
for addr8 in addr:
cmd.append(addr8)
return_val = self.issue_cmd(cmd,length)
return return_val
def is_busy(self):
cmd = [self.CMD_STATUSREG_READ]
if ((self.issue_cmd(cmd,1)[0]&self.SR_IS_READY_MASK)==self.SR_IS_READY_MASK):
return True
else:
return False
def status_clear(self):
cmd = [self.CMD_STATUSREG_CLEAR]
self.issue_cmd(cmd)
def write_en(self):
cmd = [self.CMD_WRITE_ENABLE]
self.issue_cmd(cmd)
def erase_sector(self,addr):
self.status_clear()
self.write_en()
#make sure nothing is happening
while(self.is_busy()):
pass
cmd = [self.CMD_SECTOR_ERASE]
addr = int.to_bytes(addr,4,'big')
for addr8 in addr:
cmd.append(addr8)
self.issue_cmd(cmd,0)
#wait until done
while(self.is_busy()):
pass
self.status_clear()
def random_write(self,addr,data):
self.status_clear()
self.write_en()
#make sure nothing is happening
while(self.is_busy()):
pass
cmd = [self.CMD_PAGEPROGRAM_WRITE]
addr = int.to_bytes(addr,4,'big')
for addr8 in addr:
cmd.append(addr8)
cmd.extend(data)
self.issue_cmd(cmd,0)
#wait until done
while(self.is_busy()):
pass
self.status_clear()
def write_sector(self,addr,data):
self.erase_sector(addr)
stride = self.page_size
#print(data[0:0x80])
for i in range(0,len(data),stride):
#print(i)
self.random_write(addr+i,data[0+i:stride+i])
def verify_sector (self,addr,data):
read_data = self.random_read(addr,self.sector_size)
for rbyte,dbyte in zip(read_data,data):
if(rbyte != dbyte):
print (addr,rbyte,dbyte)
print("BAD VERIFY")
return 1
print("GOOD VERIFY")
return 0
def write_flash(self,addr,data,verify_only=False):
for i in range(0,len(data),self.sector_size):
print((i*100.0)/len(data))
print(hex(addr+i))
if(i<len(data)):
if(not verify_only):
self.write_sector(addr+i,data[0+i:self.sector_size+i])
if(self.verify_sector(addr+i,data[0+i:self.sector_size+i])==1):
return 1
else:
if(not verify_only):
self.write_sector(addr+i,data[0+i:])
if(self.verify_sector(addr+i,data[0+i:])==1):
return 1
return 0
# NEEDS MORE Features to support full MCS files
def load_mcs(self,path,verify_only=False):
key = ":([0-9A-F]{2})([0-9A-F]{4})([0-9A-F]{2})([0-9A-F]+)?([0-9A-F]{2})"
file_b = bytearray()
count = 0
with open(path, 'r') as file_t:
lines = file_t.readlines()
for line in lines:
m = re.search(key,line)
if m:
num_bytes = int(m.group(1),16)
addr = int(m.group(2),16)
mcs_type = int(m.group(3),16)
if mcs_type == 1:
break
if mcs_type == 4:
continue
data_b = int.to_bytes(int(m.group(4),16),num_bytes,'big')
file_b.extend(data_b)
print(file_b[0:100])
return self.write_flash(0,file_b,verify_only)

18
Firmware/XDMA/xdc/35t_50t/module_io.xdc
View File

@ -37,6 +37,24 @@ set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS33} [get_ports i2c_scl]
set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports adc_cs]
###############################################################################
# SPI
###############################################################################
set_property PACKAGE_PIN K16 [get_ports qspi_d0]
set_property PACKAGE_PIN L17 [get_ports qspi_d1]
set_property PACKAGE_PIN J15 [get_ports qspi_d2]
set_property PACKAGE_PIN J16 [get_ports qspi_d3]
set_property IOSTANDARD SSTL135 [get_ports qspi_d0]
set_property IOSTANDARD SSTL135 [get_ports qspi_d1]
set_property IOSTANDARD SSTL135 [get_ports qspi_d2]
set_property IOSTANDARD SSTL135 [get_ports qspi_d3]
set_property PACKAGE_PIN L15 [get_ports qspi_cs]
set_property IOSTANDARD SSTL135 [get_ports qspi_cs]
set_property INTERNAL_VREF 0.675 [get_iobanks 14]
#############################################################################################################
##ADC Differential I/O
#############################################################################################################

16
Firmware/XDMA/xdc/module_io.xdc
View File

@ -37,6 +37,22 @@ set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports i2c_scl]
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports adc_cs]
###############################################################################
# SPI
###############################################################################
set_property PACKAGE_PIN P22 [get_ports qspi_d0]
set_property PACKAGE_PIN R22 [get_ports qspi_d1]
set_property PACKAGE_PIN P21 [get_ports qspi_d2]
set_property PACKAGE_PIN R21 [get_ports qspi_d3]
set_property IOSTANDARD LVCMOS33 [get_ports qspi_d0]
set_property IOSTANDARD LVCMOS33 [get_ports qspi_d1]
set_property IOSTANDARD LVCMOS33 [get_ports qspi_d2]
set_property IOSTANDARD LVCMOS33 [get_ports qspi_d3]
set_property PACKAGE_PIN T19 [get_ports qspi_cs]
set_property IOSTANDARD LVCMOS33 [get_ports qspi_cs]
#############################################################################################################
##ADC Differential I/O
#############################################################################################################

3
Firmware/XDMA/xdma_gen.tcl
View File

@ -233,6 +233,7 @@ open_run impl_1
write_bitstream -force -bin_file $origin_dir/output/${_xil_proj_name_}.bit
set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x0097FC00 [current_design]
write_bitstream -force -bin_file $origin_dir/output/${_xil_proj_name_}_gold.bit
write_cfgmem -force -format mcs -size 32 -interface SPIx4 -loadbit "up 0x00000000 $origin_dir/output/${_xil_proj_name_}_gold.bit up 0x00980000 $origin_dir/output/${_xil_proj_name_}.bit" -loaddata "up 0x0097FC00 ./cfg/timer1.bin up 0x01300000 ./cfg/timer2.bin" $origin_dir/output/${_xil_proj_name_}_backup.mcs
write_cfgmem -force -format mcs -size 32 -interface SPIx4 -loadbit "up 0x00000000 $origin_dir/output/${_xil_proj_name_}_gold.bit up 0x00980000 $origin_dir/output/${_xil_proj_name_}.bit" -loaddata "up 0x0097FC00 ./cfg/timer1.bin up 0x01300000 ./cfg/timer2.bin" $origin_dir/output/${_xil_proj_name_}_full.mcs
write_cfgmem -force -format mcs -size 32 -interface SPIx4 -loadbit "up 0x00980000 $origin_dir/output/${_xil_proj_name_}.bit" $origin_dir/output/${_xil_proj_name_}_update.mcs
close_project