mirror of
https://github.com/EEVengers/ThunderScope.git
synced 2025-04-11 23:19:16 +00:00
Misc WIP
Changed ADC decoupling, improved acq reg placement, etc.
This commit is contained in:
Aleksa Bjelogrlic
parent
24bbcac181
commit
d03db415d6
Hardware/KiCad/Thunderscope_Rev5
LOADING design file
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@ -4,20 +4,50 @@
|
||||
"active_layer_preset": "",
|
||||
"auto_track_width": true,
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||||
"hidden_netclasses": [
|
||||
"FE_100Z_Diff",
|
||||
"FE_50Z",
|
||||
"LVDS",
|
||||
"LVDS_ADC",
|
||||
"LVDS_SYNC",
|
||||
"LVDS_USRIO",
|
||||
"PCIe",
|
||||
"PWR"
|
||||
],
|
||||
"hidden_nets": [
|
||||
"/ADC/+1V8A",
|
||||
"/ADC/+1V8D",
|
||||
"/VCM",
|
||||
"/FPGA/MGT_TX0_N",
|
||||
"/FPGA/MGT_TX0_P",
|
||||
"/FPGA/MGT_TX1_N",
|
||||
"/FPGA/MGT_TX1_P",
|
||||
"/FPGA/MGT_TX2_N",
|
||||
"/FPGA/MGT_TX2_P",
|
||||
"/FPGA/MGT_TX3_N",
|
||||
"/FPGA/MGT_TX3_P",
|
||||
"/Clock Generator/INTREF",
|
||||
"/Clock Generator/ADC_CLK_R_P",
|
||||
"/ADC/ADC_CLK_P",
|
||||
"/ADC/ADC_CLK_N",
|
||||
"/Clock Generator/ADC_CLK_R_N",
|
||||
"Net-(U18H-VCCADC_0)",
|
||||
"/CH1/ATTEN_50X_R",
|
||||
"/CH2/ATTEN_50X_R",
|
||||
"/CH3/ATTEN_50X_R",
|
||||
"/CH4/ATTEN_50X_R",
|
||||
"/CH4/TERM_1M_R",
|
||||
"/CH4/ATTEN_50X",
|
||||
"/CH4/BUF_IN",
|
||||
"/CH4/ATTEN_OUT_R",
|
||||
"/TRIM_1",
|
||||
"/TRIM_2",
|
||||
"/TRIM_3",
|
||||
"/TRIM_4",
|
||||
"+2V5",
|
||||
"Net-(J4-Pad2)",
|
||||
"/FPGA/TCK",
|
||||
"/FPGA/TDI",
|
||||
"/FPGA/TMS",
|
||||
"/FPGA/TDO",
|
||||
"AGND",
|
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"+3V3",
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||||
"+1V8",
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@ -27,16 +57,59 @@
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"-5V",
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"+VBIAS",
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"+3V3_PGA",
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"/CH1/TERM_50Z",
|
||||
"/CH2/TERM_50Z",
|
||||
"/CH3/TERM_50Z",
|
||||
"/CH4/TERM_50Z",
|
||||
"/CH1/BNC_IN",
|
||||
"/CH2/BNC_IN",
|
||||
"/CH3/BNC_IN",
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||||
"+1V8APLL",
|
||||
"/CH4/BNC_IN",
|
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"+5V2",
|
||||
"-VBIAS",
|
||||
"/CH1/TERM_50Z_R",
|
||||
"/CH2/TERM_50Z_R",
|
||||
"/CH3/TERM_50Z_R",
|
||||
"/CH4/ATTEN_IN",
|
||||
"/CH4/TERM_1M",
|
||||
"/CH4/TERM_50Z_R",
|
||||
"/CH4/ATTEN_OUT",
|
||||
"/Front End Trim and Bias/TRIM_SCL",
|
||||
"/Front End Trim and Bias/TRIM_SDA",
|
||||
"/ADC/ADC_CSn",
|
||||
"/ADC/ADC_RSTn",
|
||||
"/ADC/ADC_PD",
|
||||
"/CH1_N",
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||||
"/CH1_P",
|
||||
"/CH2_N",
|
||||
"/CH2_P",
|
||||
"/CH3_P",
|
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"/CH3_N",
|
||||
"/CH4_P",
|
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"/CH4_N",
|
||||
"/FPGA/MGT_RX0_N",
|
||||
"/FPGA/MGT_RX0_P",
|
||||
"/FPGA/MGT_RX1_N",
|
||||
"/FPGA/MGT_RX1_P",
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"/FPGA/MGT_RX2_N",
|
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"/FPGA/MGT_RX2_P",
|
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"/FPGA/MGT_RX3_N",
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"/FPGA/MGT_RX3_P",
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"/Clock Generator/PLL_RSTn",
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"/FPGA/FPGA IO Banks/PLL_SCL",
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"/FPGA/FPGA IO Banks/PLL_SDA",
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"+1V8_ACQ",
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"/Clock Generator/IF1",
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"/Clock Generator/IF0",
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"/Clock Generator/AC0",
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"/Clock Generator/AC1",
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"/Clock Generator/AC2",
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"/Clock Generator/TEST",
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"/FPGA/FPGA IO Banks/PUDC",
|
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"Net-(U18D-INIT_B_0)",
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||||
"Net-(U18D-PROGRAM_B_0)",
|
||||
"Net-(U18E-MGTRREF_216)",
|
||||
"/TERM_1",
|
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"/TERM_2",
|
||||
"/TERM_3",
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@ -49,10 +122,14 @@
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"/PGA_CSn_2",
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||||
"/PGA_CSn_3",
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||||
"/PGA_CSn_4",
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||||
"/CH4/ATTEN_1X",
|
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"/DC_CPL_1",
|
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"/DC_CPL_2",
|
||||
"/DC_CPL_3",
|
||||
"/DC_CPL_4",
|
||||
"/ADC/ADC_SDATA",
|
||||
"/ADC/ADC_SCLK",
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||||
"Net-(U18D-DONE_0)",
|
||||
"GND",
|
||||
"+5V",
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"/ADC/D3B_P",
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@ -75,12 +152,14 @@
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"/ADC/LCLK_P",
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"/ADC/D4A_P",
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"/ADC/D4B_N",
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"/FPGA/FPGA IO Banks/FE_PG",
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"/FPGA/FPGA IO Banks/QSPI_DQ2",
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"/FPGA/FPGA IO Banks/QSPI_DQ0",
|
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"/FPGA/FPGA IO Banks/QSPI_DQ1",
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"/PGA_SDIO",
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"/PGA_SCLK",
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"/FPGA/FPGA IO Banks/QSPI_DQ3",
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"+VUSB",
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"Net-(D1-R)",
|
||||
"Net-(D1-G)",
|
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"Net-(D1-B)",
|
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"+3V3_ACQ",
|
||||
"/TS-PCIe Components/PCIe_PER3_N",
|
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"/TS-PCIe Components/PCIe_PER3_P",
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@ -99,11 +178,19 @@
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"/TS-USB4 Components/M2_PER0_N",
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"/TS-USB4 Components/M2_PER0_P",
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"/TS-PCIe Components/PCIe_REFCLK_N",
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"/MGT_CLK1_N",
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"/TS-PCIe Components/PCIe_REFCLK_P",
|
||||
"/MGT_CLK1_P",
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"/TS-USB4 Components/M2_REFCLK_N",
|
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"/TS-USB4 Components/M2_REFCLK_P",
|
||||
"/REFINOUT",
|
||||
"/TS-USB4 Components/REFINOUT1",
|
||||
"/TS-USB4 Components/SYNC1",
|
||||
"/TS-PCIe Components/REFINOUT2",
|
||||
"/TS-PCIe Components/SYNC2",
|
||||
"/TS-USB4 Components/M2_PET1_P",
|
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"/TS-USB4 Components/M2_PET1_N",
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"/TS-USB4 Components/+VUSB_M2",
|
||||
"/TS-USB4 Components/M2_PET0_N",
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"/TS-USB4 Components/M2_PET2_P",
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"/TS-USB4 Components/M2_PERST#",
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@ -142,59 +229,61 @@
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||||
"/TS-PCIe Components/PCIe_PET3_P",
|
||||
"/TS-PCIe Components/PCIe_PET2_P",
|
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"/TS-PCIe Components/PCIe_PERST#",
|
||||
"/TS-PCIe Components/PRSNT1#",
|
||||
"/TS-PCIe Components/PCIe_PET2_N",
|
||||
"/TS-PCIe Components/PRSNT2#_1",
|
||||
"/TS-PCIe Components/PRSNT2#_4",
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||||
"/TS-PCIe Components/PCIe_PET0_P",
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"/TS-PCIe Components/PCIe_PET0_N",
|
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"/FPGA/FPGA Voltage Regs/PG_1V8",
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"/SYNC",
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"/FPGA/LED_G",
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"/COMP",
|
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"/FPGA/PROBE_COMP",
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"/PERST#",
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"/FPGA/FPGA IO Banks/ACQ_PG",
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"/FPGA/SYNC_OUT_N",
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"/FPGA/SYNC_OUT_P",
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"/FPGA/SYNC_REn",
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"/FPGA/SYNC_DE",
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"/FPGA/LED_R",
|
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"/FPGA/LED_B",
|
||||
"/CH1/SW_COM",
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"/CH1/SW_NO",
|
||||
"/CH2/SW_COM",
|
||||
"/CH2/SW_NO",
|
||||
"/CH3/SW_NO",
|
||||
"/CH3/SW_COM",
|
||||
"/CH1/BUF_IN_AUX",
|
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"/CH2/BUF_IN_AUX",
|
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"/CH3/BUF_IN_AUX",
|
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"/CH1/DC_FB",
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"/CH1/OPA_OUT",
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"/CH2/DC_FB",
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"/CH2/OPA_OUT",
|
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"/CH3/DC_FB",
|
||||
"/CH3/OPA_OUT",
|
||||
"/CH1/+VPGA",
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"/CH2/+VPGA",
|
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"/CH3/+VPGA",
|
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"/CH1/PGA_BIAS",
|
||||
"/CH2/PGA_BIAS",
|
||||
"/CH3/PGA_BIAS",
|
||||
"/CH1/OUT_R_N",
|
||||
"/CH2/OUT_R_N",
|
||||
"/CH3/OUT_R_N",
|
||||
"/CH1/OUT_R_P",
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"/CH2/OUT_R_P",
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"/CH3/OUT_R_P",
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"/CH1/DC_CPLn",
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"/CH2/DC_CPLn",
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"/CH3/DC_CPLn",
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"/CH1/BUF_R_BIAS",
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"/CH2/BUF_R_BIAS",
|
||||
"/CH3/BUF_R_BIAS",
|
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"/CH1/BUF_OUT",
|
||||
"/CH1/BUF_OUT_R",
|
||||
"/CH2/BUF_OUT_R",
|
||||
"/CH2/BUF_OUT",
|
||||
"/CH3/BUF_OUT",
|
||||
"/CH3/BUF_OUT_R",
|
||||
"/CH1/BUF_IN_BIAS",
|
||||
"/CH2/BUF_IN_BIAS",
|
||||
"/CH3/BUF_IN_BIAS",
|
||||
"/CH1/DC_FB_TRIM",
|
||||
"/CH2/DC_FB_TRIM",
|
||||
"/CH3/DC_FB_TRIM"
|
||||
"/FPGA/FPGA Config and Transceivers/QSPI_CS",
|
||||
"/FPGA/FPGA IO Banks/HWID0",
|
||||
"/FPGA/FPGA IO Banks/HWID1",
|
||||
"/FPGA/FPGA IO Banks/HWID2",
|
||||
"/VARIANT",
|
||||
"/FPGA/FPGA IO Banks/ACQ_EN",
|
||||
"/ACQ and FE Voltage Regs/FE_EN",
|
||||
"/FPGA/FPGA Voltage Regs/PG_1V0",
|
||||
"/FPGA/FPGA Config and Transceivers/QSPI_CLK",
|
||||
"/FPGA/SYNC_IN_N",
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||||
"/FPGA/SYNC_IN_P",
|
||||
"/FPGA/CLK25",
|
||||
"/CH1/TERM_1M_R",
|
||||
"/CH2/TERM_1M_R",
|
||||
"/CH3/TERM_1M_R",
|
||||
"/CH1/ATTEN_50X",
|
||||
"/CH2/ATTEN_50X",
|
||||
"/CH3/ATTEN_50X",
|
||||
"/CH1/BUF_IN",
|
||||
"/CH1/ATTEN_OUT_R",
|
||||
"/CH2/BUF_IN",
|
||||
"/CH2/ATTEN_OUT_R",
|
||||
"/CH3/BUF_IN",
|
||||
"/CH3/ATTEN_OUT_R",
|
||||
"/CH1/TERM_1M",
|
||||
"/CH1/ATTEN_IN",
|
||||
"/CH2/TERM_1M",
|
||||
"/CH2/ATTEN_IN",
|
||||
"/CH3/TERM_1M",
|
||||
"/CH3/ATTEN_IN",
|
||||
"/CH1/ATTEN_1X",
|
||||
"/CH1/ATTEN_OUT",
|
||||
"/CH2/ATTEN_OUT",
|
||||
"/CH2/ATTEN_1X",
|
||||
"/CH3/ATTEN_1X",
|
||||
"/CH3/ATTEN_OUT"
|
||||
],
|
||||
"high_contrast_mode": 0,
|
||||
"net_color_mode": 1,
|
||||
@ -223,6 +312,7 @@
|
||||
"vias",
|
||||
"footprint_text",
|
||||
"footprint_anchors",
|
||||
"ratsnest",
|
||||
"grid",
|
||||
"footprints_front",
|
||||
"footprints_back",
|
||||
@ -238,7 +328,7 @@
|
||||
"conflict_shadows",
|
||||
"shapes"
|
||||
],
|
||||
"visible_layers": "00000000_00000000_00000008_82002237",
|
||||
"visible_layers": "00000000_00000000_00000008_82002227",
|
||||
"zone_display_mode": 0
|
||||
},
|
||||
"git": {
|
||||
|
||||
@ -516,17 +516,7 @@
|
||||
"wire_width": 6
|
||||
},
|
||||
{
|
||||
"clearance": 0.1524,
|
||||
"name": "FE_50Z",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 3,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.213,
|
||||
"via_diameter": 2.0,
|
||||
"via_drill": 1.0
|
||||
},
|
||||
{
|
||||
"name": "LVDS",
|
||||
"name": "FE_100Z_Diff",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 0,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
@ -534,18 +524,52 @@
|
||||
"via_drill": 0.2032
|
||||
},
|
||||
{
|
||||
"name": "PCIe",
|
||||
"clearance": 0.1524,
|
||||
"name": "FE_50Z",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 6,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.213,
|
||||
"via_diameter": 2.0,
|
||||
"via_drill": 1.0
|
||||
},
|
||||
{
|
||||
"name": "LVDS_ADC",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 3,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"via_diameter": 0.4064,
|
||||
"via_drill": 0.2032
|
||||
},
|
||||
{
|
||||
"name": "LVDS_SYNC",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 1,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"via_diameter": 0.4064,
|
||||
"via_drill": 0.2032
|
||||
},
|
||||
{
|
||||
"name": "LVDS_USRIO",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 2,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"via_diameter": 0.4064,
|
||||
"via_drill": 0.2032
|
||||
},
|
||||
{
|
||||
"name": "PCIe",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 5,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"via_diameter": 0.4064,
|
||||
"via_drill": 0.2032
|
||||
},
|
||||
{
|
||||
"clearance": 0.1524,
|
||||
"name": "PWR",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 1,
|
||||
"priority": 4,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.254,
|
||||
"via_diameter": 0.4064,
|
||||
@ -615,16 +639,44 @@
|
||||
"pattern": "GND"
|
||||
},
|
||||
{
|
||||
"netclass": "LVDS",
|
||||
"netclass": "LVDS_ADC",
|
||||
"pattern": "/ADC/*_N"
|
||||
},
|
||||
{
|
||||
"netclass": "LVDS",
|
||||
"netclass": "LVDS_ADC",
|
||||
"pattern": "/ADC/*_P"
|
||||
},
|
||||
{
|
||||
"netclass": "LVDS",
|
||||
"netclass": "LVDS_USRIO",
|
||||
"pattern": "*USRIO*"
|
||||
},
|
||||
{
|
||||
"netclass": "PCIe",
|
||||
"pattern": "*MGT_*"
|
||||
},
|
||||
{
|
||||
"netclass": "LVDS_SYNC",
|
||||
"pattern": "*SYNC_IN*"
|
||||
},
|
||||
{
|
||||
"netclass": "LVDS_SYNC",
|
||||
"pattern": "*SYNC_OUT*"
|
||||
},
|
||||
{
|
||||
"netclass": "FE_100Z_Diff",
|
||||
"pattern": "/CH1_*"
|
||||
},
|
||||
{
|
||||
"netclass": "FE_100Z_Diff",
|
||||
"pattern": "/CH2_*"
|
||||
},
|
||||
{
|
||||
"netclass": "FE_100Z_Diff",
|
||||
"pattern": "/CH3_*"
|
||||
},
|
||||
{
|
||||
"netclass": "FE_100Z_Diff",
|
||||
"pattern": "/CH4_*"
|
||||
}
|
||||
]
|
||||
},
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
(footprint "GEN_TP_PCB"
|
||||
(version 20241030)
|
||||
(version 20241229)
|
||||
(generator "pcbnew")
|
||||
(generator_version "8.99")
|
||||
(generator_version "9.0")
|
||||
(layer "F.Cu")
|
||||
(property "Reference" "REF**"
|
||||
(at 3.935902 -9.118755 90)
|
||||
@ -29,19 +29,6 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "Footprint" ""
|
||||
(at 0 0 180)
|
||||
(layer "B.Fab")
|
||||
(hide yes)
|
||||
(uuid "688453d1-583c-49cf-9037-defd6883a68b")
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
(thickness 0.15)
|
||||
)
|
||||
(justify mirror)
|
||||
)
|
||||
)
|
||||
(property "Datasheet" ""
|
||||
(at 0 0 180)
|
||||
(layer "B.Fab")
|
||||
@ -75,15 +62,15 @@
|
||||
(width 0.05)
|
||||
(type solid)
|
||||
)
|
||||
(fill none)
|
||||
(fill no)
|
||||
(layer "F.CrtYd")
|
||||
(uuid "3bc318e6-aac3-4569-bcd1-d11ea49947e9")
|
||||
)
|
||||
(pad "1" smd circle
|
||||
(at 0 0)
|
||||
(size 1 1)
|
||||
(layers "F.Cu" "F.Mask" "F.Paste")
|
||||
(solder_paste_margin -1)
|
||||
(property pad_prop_testpoint)
|
||||
(layers "F.Cu" "F.Mask")
|
||||
(thermal_bridge_angle 90)
|
||||
(uuid "aba2b2be-fbd6-4e69-a700-39f4f588208f")
|
||||
)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user