Final signal routing WIP

Hardware/KiCad/Thunderscope_Rev5/Thunderscope_Rev5.kicad_prl

@@ -1,6 +1,6 @@
 {
   "board": {
-    "active_layer": 2,
+    "active_layer": 8,
     "active_layer_preset": "",
     "auto_track_width": false,
     "hidden_netclasses": [
@@ -8,14 +8,7 @@
       "PWR"
     ],
     "hidden_nets": [
-      "/VCM",
-      "Net-(U18H-VCCADC_0)",
-      "/TRIM_1",
-      "/TRIM_2",
-      "/TRIM_3",
-      "/TRIM_4",
       "+2V5",
-      "AGND",
       "+3V3",
       "+1V8",
       "+1V2_MGT",
@@ -27,39 +20,11 @@
       "+1V8APLL",
       "+5V2",
       "-VBIAS",
-      "/Front End Trim and Bias/TRIM_SCL",
-      "/Front End Trim and Bias/TRIM_SDA",
       "+1V8_ACQ",
-      "Net-(U18D-INIT_B_0)",
-      "Net-(U18D-PROGRAM_B_0)",
-      "Net-(U18E-MGTRREF_216)",
-      "/TERM_1",
-      "/TERM_2",
-      "/TERM_3",
-      "/TERM_4",
-      "/ATTEN_1",
-      "/ATTEN_2",
-      "/ATTEN_3",
-      "/ATTEN_4",
-      "/PGA_CSn_1",
-      "/PGA_CSn_2",
-      "/PGA_CSn_3",
-      "/PGA_CSn_4",
-      "/DC_CPL_1",
-      "/DC_CPL_2",
-      "/DC_CPL_3",
-      "/DC_CPL_4",
-      "Net-(U18D-DONE_0)",
       "GND",
       "+5V",
-      "/PGA_SDIO",
-      "/PGA_SCLK",
       "+VUSB",
-      "+3V3_ACQ",
-      "/FPGA/LED_G",
-      "/FPGA/PROBE_COMP",
-      "/FPGA/LED_R",
-      "/FPGA/LED_B"
+      "+3V3_ACQ"
     ],
     "high_contrast_mode": 0,
     "net_color_mode": 1,
@@ -103,7 +68,7 @@
       "conflict_shadows",
       "shapes"
     ],
-    "visible_layers": "00000000_00000000_00000000_02000005",
+    "visible_layers": "00000000_00000000_00000000_02000000",
     "zone_display_mode": 0
   },
   "git": {

Hardware/KiCad/Thunderscope_Rev5/Thunderscope_Rev5.kicad_pro

@@ -157,7 +157,7 @@
         "max_error": 0.005,
         "min_clearance": 0.127,
         "min_connection": 0.127,
-        "min_copper_edge_clearance": 0.5,
+        "min_copper_edge_clearance": 0.3,
         "min_groove_width": 0.0,
         "min_hole_clearance": 0.25,
         "min_hole_to_hole": 0.25,