Added DDR3 Wraparound and Wraparound_Overflow Flags

Firmware/XDMA/bd/top_bd_200t.tcl

@@ -20,7 +20,7 @@ set script_folder [_tcl::get_script_folder]
 ################################################################
 # Check if script is running in correct Vivado version.
 ################################################################
-set scripts_vivado_version 2020.1
+set scripts_vivado_version 2023.2
 set current_vivado_version [version -short]
 
 if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
@@ -356,7 +356,7 @@ proc create_hier_cell_PCIe { parentCell nameHier } {
  ] $axi_dwidth_converter_0
 
   # Create instance: util_ds_buf_0, and set properties
-  set util_ds_buf_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_0 ]
+  set util_ds_buf_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf_0 ]
   set_property -dict [ list \
    CONFIG.C_BUF_TYPE {IBUFDSGTE} \
  ] $util_ds_buf_0
@@ -801,10 +801,10 @@ proc create_hier_cell_Memory { parentCell nameHier } {
  ] $mig_7series_0
 
   # Create instance: util_ds_buf_0, and set properties
-  set util_ds_buf_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_0 ]
+  set util_ds_buf_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf_0 ]
 
   # Create instance: util_ds_buf_1, and set properties
-  set util_ds_buf_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_1 ]
+  set util_ds_buf_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf_1 ]
   set_property -dict [ list \
    CONFIG.C_BUF_TYPE {BUFG} \
  ] $util_ds_buf_1
@@ -1303,7 +1303,7 @@ proc create_hier_cell_AXI_LITE_IO { parentCell nameHier } {
  ] $axi_crossbar_0
 
   # Create instance: axi_fifo_mm_s_0, and set properties
-  set axi_fifo_mm_s_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_fifo_mm_s:4.2 axi_fifo_mm_s_0 ]
+  set axi_fifo_mm_s_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_fifo_mm_s:4.3 axi_fifo_mm_s_0 ]
   set_property -dict [ list \
    CONFIG.C_USE_RX_DATA {0} \
    CONFIG.C_USE_TX_CTRL {0} \

Firmware/XDMA/hdl/100t_200t/dso_top.v

@@ -75,6 +75,7 @@ module dso_top
   wire axi_aresetn;
  
   wire [31:0]gpio2_io_i;
+  wire [31:0]gpio2_io_o_0;
   wire [31:0]gpio_io_o_0;
 
   wire s2mm_err;
@@ -247,6 +248,7 @@ module dso_top
     .s2mm_wr_xfer_cmplt(s2mm_wr_xfer_cmplt),
     .gpio_io_o_0(gpio_io_o_0),
     .gpio2_io_i(gpio2_io_i),
+    .gpio2_io_o_0(gpio2_io_o_0),
     .serdes_ready (serdes_ready),
     .ddr_ready(ddr_ready)
   );
@@ -298,6 +300,7 @@ module dso_top
     .axi_aclk(axi_aclk),
     .axi_aresetn(axi_aresetn),
     .gpio2_io_i(gpio2_io_i),
+    .gpio2_io_o_0(gpio2_io_o_0),
     .gpio_io_o_0(gpio_io_o_0),
     .pcie_clk_n(pcie_clk_n),
     .pcie_clk_p(pcie_clk_p),

Firmware/XDMA/hdl/adc_to_datamover.v

@@ -18,6 +18,7 @@ module adc_to_datamover(
     input s2mm_wr_xfer_cmplt,
     input[31:0] gpio_io_o_0,
     output[31:0] gpio2_io_i,
+    input[31:0] gpio2_io_o_0,
     input serdes_ready,
     input ddr_ready
     );
@@ -95,7 +96,7 @@ module adc_to_datamover(
     fifo_full_cdc <= { fifo_full_cdc[1:0], fifo_full};
   assign fifo_full_aclk = fifo_full_cdc[2];
   
-  reg [13:0] fifo_full_counter;
+  reg [11:0] fifo_full_counter;
   always @(posedge axi_aclk) begin
     if (!S01_ARESETN) begin
         fifo_full_counter <= 0;
@@ -105,9 +106,29 @@ module adc_to_datamover(
     end
   end
   
+  reg wraparound = 0;
+  reg wraparound_overflow = 0;
+  always @(posedge axi_aclk) begin
+    if (!S01_ARESETN) begin
+        wraparound <= 0;
+        wraparound_overflow <= 0;
+    end
+    else if (gpio2_io_o_0[16]) begin
+        wraparound <= 0;
+    end
+    else if (gpio2_io_o_0[17]) begin
+        wraparound_overflow <= 0;
+    end
+    else if (address == 28'hFFFF000) begin
+        wraparound <= 1;
+        if (wraparound) begin
+            wraparound_overflow <= 1;
+        end
+    end
+  end
 
   //Status GPIOs
-  assign gpio2_io_i = {s2mm_err,fifo_full_aclk,fifo_full_counter,transfer_counter};
+  assign gpio2_io_i = {s2mm_err,fifo_full_aclk,fifo_full_counter,wraparound_overflow,wraparound,transfer_counter};
   assign S01_ARESETN = (axi_aresetn & gpio_io_o_0[1]);
   assign s2mm_halt = ~gpio_io_o_0[0];
 

Firmware/XDMA/output/xdma_prj_200t_full.prm

@@ -8,7 +8,7 @@ Start Address      0x00000000
 End Address        0x01FFFFFF
 
 Addr1         Addr2         Date                    File(s)
-0x00000000    0x003765E7    May 11 02:50:24 2024    ./output/xdma_prj_200t_gold.bit
-0x0097FC00    0x0097FFFF    Apr 13 15:25:20 2024    ./cfg/timer1.bin
-0x00980000    0x00CF65E7    May 11 02:49:54 2024    ./output/xdma_prj_200t.bit
-0x01300000    0x0130003B    Apr 13 15:25:20 2024    ./cfg/timer2.bin
+0x00000000    0x003B0567    Jul  7 03:46:18 2024    ./output/xdma_prj_200t_gold.bit
+0x0097FC00    0x0097FFFF    Jul  7 02:21:45 2024    ./cfg/timer1.bin
+0x00980000    0x00D30567    Jul  7 03:44:59 2024    ./output/xdma_prj_200t.bit
+0x01300000    0x0130003B    Jul  7 02:21:45 2024    ./cfg/timer2.bin

Firmware/XDMA/output/xdma_prj_200t_update.prm

@@ -8,4 +8,4 @@ Start Address      0x00000000
 End Address        0x01FFFFFF
 
 Addr1         Addr2         Date                    File(s)
-0x00980000    0x00CF65E7    May 11 02:49:54 2024    ./output/xdma_prj_200t.bit
+0x00980000    0x00D30567    Jul  7 03:44:59 2024    ./output/xdma_prj_200t.bit

Firmware/XDMA/xdma_gen.tcl

@@ -1,5 +1,5 @@
 #*****************************************************************************************
-# Vivado (TM) v2020.1 (64-bit)
+# Vivado (TM) v2023.2 (64-bit)
 #
 #
 #*****************************************************************************************