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Added bitstreams
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2058d4001e
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Firmware/XDMA/output
xdma_prj_100t.binxdma_prj_100t.bitxdma_prj_100t_full.mcsxdma_prj_100t_full.prmxdma_prj_100t_gold.binxdma_prj_100t_gold.bitxdma_prj_100t_update.mcsxdma_prj_100t_update.prmxdma_prj_200t.binxdma_prj_200t.bitxdma_prj_200t_full.mcsxdma_prj_200t_full.prmxdma_prj_200t_gold.binxdma_prj_200t_gold.bitxdma_prj_200t_update.mcsxdma_prj_200t_update.prmxdma_prj_50t.binxdma_prj_50t.bitxdma_prj_50t_full.mcsxdma_prj_50t_full.prmxdma_prj_50t_gold.binxdma_prj_50t_gold.bitxdma_prj_50t_update.mcsxdma_prj_50t_update.prm
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Load Diff
@ -8,7 +8,7 @@ Start Address 0x00000000
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End Address 0x01FFFFFF
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Addr1 Addr2 Date File(s)
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0x00000000 0x00277377 Sep 11 20:19:55 2024 ./output/xdma_prj_100t_gold.bit
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0x00000000 0x002620D3 Sep 13 00:41:17 2024 ./output/xdma_prj_100t_gold.bit
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0x0097FC00 0x0097FFFF Apr 13 15:25:20 2024 ./cfg/timer1.bin
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0x00980000 0x00BF7377 Sep 11 20:19:33 2024 ./output/xdma_prj_100t.bit
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0x00980000 0x00BE20D3 Sep 13 00:40:56 2024 ./output/xdma_prj_100t.bit
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0x01300000 0x0130003B Apr 13 15:25:20 2024 ./cfg/timer2.bin
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@ -8,4 +8,4 @@ Start Address 0x00000000
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End Address 0x01FFFFFF
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Addr1 Addr2 Date File(s)
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0x00980000 0x00BF7377 Sep 11 20:19:33 2024 ./output/xdma_prj_100t.bit
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0x00980000 0x00BE20D3 Sep 13 00:40:56 2024 ./output/xdma_prj_100t.bit
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@ -8,7 +8,7 @@ Start Address 0x00000000
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End Address 0x01FFFFFF
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Addr1 Addr2 Date File(s)
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0x00000000 0x00373D53 Sep 11 08:01:21 2024 ./output/xdma_prj_200t_gold.bit
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0x00000000 0x00388127 Sep 13 00:54:57 2024 ./output/xdma_prj_200t_gold.bit
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0x0097FC00 0x0097FFFF Apr 13 15:25:20 2024 ./cfg/timer1.bin
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0x00980000 0x00CF3D53 Sep 11 08:00:52 2024 ./output/xdma_prj_200t.bit
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0x00980000 0x00D08127 Sep 13 00:54:28 2024 ./output/xdma_prj_200t.bit
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0x01300000 0x0130003B Apr 13 15:25:20 2024 ./cfg/timer2.bin
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Load Diff
@ -8,4 +8,4 @@ Start Address 0x00000000
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End Address 0x01FFFFFF
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Addr1 Addr2 Date File(s)
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0x00980000 0x00CF3D53 Sep 11 08:00:52 2024 ./output/xdma_prj_200t.bit
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0x00980000 0x00D08127 Sep 13 00:54:28 2024 ./output/xdma_prj_200t.bit
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@ -8,7 +8,7 @@ Start Address 0x00000000
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End Address 0x007FFFFF
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Addr1 Addr2 Date File(s)
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0x00000000 0x001833CF Sep 11 21:21:08 2024 ./output/xdma_prj_50t_gold.bit
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0x00000000 0x00182743 Sep 13 00:28:30 2024 ./output/xdma_prj_50t_gold.bit
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0x0023FC00 0x0023FFFF May 11 13:02:37 2024 ./cfg/timer1_50t.bin
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0x00240000 0x003C33CF Sep 11 21:20:51 2024 ./output/xdma_prj_50t.bit
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0x00240000 0x003C2743 Sep 13 00:28:12 2024 ./output/xdma_prj_50t.bit
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0x00480000 0x0048003B May 11 13:02:37 2024 ./cfg/timer2_50t.bin
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Load Diff
@ -8,4 +8,4 @@ Start Address 0x00000000
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End Address 0x007FFFFF
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Addr1 Addr2 Date File(s)
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0x00240000 0x003C33CF Sep 11 21:20:51 2024 ./output/xdma_prj_50t.bit
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0x00240000 0x003C2743 Sep 13 00:28:12 2024 ./output/xdma_prj_50t.bit
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