AllSpiceMirrors/ThunderScope
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Front End Routing Complete

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This commit is contained in:
Aleksa Bjelogrlic 2025-03-13 00:14:14 -04:00
parent 833d8d7c72
commit f7a7227757
3 changed files with 7842 additions and 137232 deletions

Hardware/KiCad/Thunderscope_Rev5/Thunderscope_Rev5.kicad_pcb
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LOADING design file

156
Hardware/KiCad/Thunderscope_Rev5/Thunderscope_Rev5.kicad_prl
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@ -1,10 +1,139 @@
{
"board": {
"active_layer": 2,
"active_layer": 0,
"active_layer_preset": "",
"auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [],
"hidden_netclasses": [
"LVDS",
"PCIe",
"PWR"
],
"hidden_nets": [
"/ADC/ADC_CLK_P",
"/ADC/ADC_CLK_N",
"+2V5",
"Net-(J4-Pad2)",
"AGND",
"+3V3",
"+1V8",
"+1V2_MGT",
"+1V0",
"+1V0_MGT",
"-5V",
"+VBIAS",
"+3V3_PGA",
"+1V8APLL",
"+5V2",
"-VBIAS",
"+1V8_ACQ",
"/TERM_1",
"/TERM_2",
"/TERM_3",
"/TERM_4",
"/ATTEN_1",
"/ATTEN_2",
"/ATTEN_3",
"/ATTEN_4",
"/DC_CPL_1",
"/DC_CPL_2",
"/DC_CPL_3",
"/DC_CPL_4",
"GND",
"+5V",
"/ADC/D3B_P",
"/ADC/D2A_P",
"/ADC/D1B_N",
"/ADC/LCLK_N",
"/ADC/D2B_N",
"/ADC/D1A_N",
"/ADC/D3A_N",
"/ADC/D3A_P",
"/ADC/FCLK_N",
"/ADC/D2B_P",
"/ADC/D1A_P",
"/ADC/D2A_N",
"/ADC/D4B_P",
"/ADC/D3B_N",
"/ADC/D1B_P",
"/ADC/D4A_N",
"/ADC/FCLK_P",
"/ADC/LCLK_P",
"/ADC/D4A_P",
"/ADC/D4B_N",
"+VUSB",
"Net-(D1-R)",
"Net-(D1-G)",
"Net-(D1-B)",
"+3V3_ACQ",
"/TS-PCIe Components/PCIe_PER3_N",
"/TS-PCIe Components/PCIe_PER3_P",
"/TS-USB4 Components/M2_PER3_N",
"/TS-USB4 Components/M2_PER3_P",
"/TS-PCIe Components/PCIe_PER2_N",
"/TS-PCIe Components/PCIe_PER2_P",
"/TS-USB4 Components/M2_PER2_N",
"/TS-USB4 Components/M2_PER2_P",
"/TS-PCIe Components/PCIe_PER1_N",
"/TS-PCIe Components/PCIe_PER1_P",
"/TS-USB4 Components/M2_PER1_N",
"/TS-USB4 Components/M2_PER1_P",
"/TS-PCIe Components/PCIe_PER0_N",
"/TS-PCIe Components/PCIe_PER0_P",
"/TS-USB4 Components/M2_PER0_N",
"/TS-USB4 Components/M2_PER0_P",
"/TS-PCIe Components/PCIe_REFCLK_N",
"/TS-PCIe Components/PCIe_REFCLK_P",
"/TS-USB4 Components/M2_REFCLK_N",
"/TS-USB4 Components/M2_REFCLK_P",
"/TS-USB4 Components/M2_PET1_P",
"/TS-USB4 Components/M2_PET1_N",
"/TS-USB4 Components/M2_PET0_N",
"/TS-USB4 Components/M2_PET2_P",
"/TS-USB4 Components/M2_PERST#",
"/TS-USB4 Components/M2_PET0_P",
"/TS-USB4 Components/M2_PET3_P",
"/TS-USB4 Components/M2_PET3_N",
"/TS-USB4 Components/M2_PET2_N",
"/FPGA/USRIO_9_N",
"/FPGA/USRIO_3_P",
"/FPGA/USRIO_4_N",
"/FPGA/USRIO_5_P",
"/FPGA/USRIO_10_N",
"/FPGA/USRIO_10_P",
"/FPGA/USRIO_3_N",
"/FPGA/USRIO_8_N",
"/FPGA/USRIO_7_N",
"/FPGA/USRIO_5_N",
"/FPGA/USRIO_8_P",
"/FPGA/USRIO_12_N",
"/FPGA/USRIO_9_P",
"/FPGA/USRIO_11_N",
"/FPGA/USRIO_2_P",
"/FPGA/USRIO_1_P",
"/FPGA/USRIO_12_P",
"/FPGA/USRIO_6_N",
"/FPGA/USRIO_4_P",
"/FPGA/USRIO_11_P",
"/FPGA/USRIO_2_N",
"/FPGA/USRIO_7_P",
"/FPGA/USRIO_6_P",
"/FPGA/USRIO_1_N",
"/SPRING",
"/TS-PCIe Components/PCIe_PET3_N",
"/TS-PCIe Components/PCIe_PET1_P",
"/TS-PCIe Components/PCIe_PET1_N",
"/TS-PCIe Components/PCIe_PET3_P",
"/TS-PCIe Components/PCIe_PET2_P",
"/TS-PCIe Components/PCIe_PERST#",
"/TS-PCIe Components/PCIe_PET2_N",
"/TS-PCIe Components/PCIe_PET0_P",
"/TS-PCIe Components/PCIe_PET0_N",
"/FPGA/LED_G",
"/COMP",
"/FPGA/PROBE_COMP",
"/FPGA/LED_R",
"/FPGA/LED_B"
],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
@ -16,22 +145,23 @@
"zones": 0.6
},
"selection_filter": {
"dimensions": true,
"dimensions": false,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": true,
"otherItems": true,
"pads": true,
"text": true,
"graphics": false,
"keepouts": false,
"lockedItems": false,
"otherItems": false,
"pads": false,
"text": false,
"tracks": true,
"vias": true,
"zones": true
"zones": false
},
"visible_items": [
"vias",
"footprint_text",
"footprint_anchors",
"ratsnest",
"grid",
"footprints_front",
"footprints_back",
@ -47,7 +177,7 @@
"conflict_shadows",
"shapes"
],
"visible_layers": "ffffffff_ffffffff_fffffff5_ffffffff",
"visible_layers": "00000000_00000000_00000002_2200888c",
"zone_display_mode": 0
},
"git": {
@ -107,7 +237,7 @@
91,
91,
91,
91
570
],
"custom_group_rules": [],
"expanded_rows": [],

109
Hardware/KiCad/Thunderscope_Rev5/Thunderscope_Rev5.kicad_pro
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@ -48,7 +48,7 @@
"silk_text_thickness": 0.1,
"silk_text_upright": false,
"zones": {
"min_clearance": 0.5
"min_clearance": 0.0
}
},
"diff_pair_dimensions": [
@ -514,6 +514,42 @@
"via_diameter": 0.4064,
"via_drill": 0.2032,
"wire_width": 6
},
{
"clearance": 0.1524,
"name": "FE_50Z",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 3,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.213,
"via_diameter": 2.0,
"via_drill": 1.0
},
{
"name": "LVDS",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 0,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"via_diameter": 0.4064,
"via_drill": 0.2032
},
{
"name": "PCIe",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 2,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"via_diameter": 0.4064,
"via_drill": 0.2032
},
{
"clearance": 0.1524,
"name": "PWR",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 1,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.254,
"via_diameter": 0.4064,
"via_drill": 0.2032
}
],
"meta": {
@ -521,7 +557,76 @@
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
"netclass_patterns": [
{
"netclass": "FE_50Z",
"pattern": "*/TERM_1M*"
},
{
"netclass": "FE_50Z",
"pattern": "*/BNC_IN"
},
{
"netclass": "FE_50Z",
"pattern": "*/TERM_50Z*"
},
{
"netclass": "FE_50Z",
"pattern": "*/ATTEN_IN"
},
{
"netclass": "FE_50Z",
"pattern": "*/ATTEN_1X"
},
{
"netclass": "FE_50Z",
"pattern": "*/ATTEN_50X*"
},
{
"netclass": "FE_50Z",
"pattern": "*/ATTEN_OUT*"
},
{
"netclass": "FE_50Z",
"pattern": "*/BUF_IN"
},
{
"netclass": "PCIe",
"pattern": "*_PER*"
},
{
"netclass": "PCIe",
"pattern": "*_PET*"
},
{
"netclass": "PCIe",
"pattern": "*_REFCLK*"
},
{
"netclass": "PWR",
"pattern": "+*"
},
{
"netclass": "PWR",
"pattern": "-*"
},
{
"netclass": "PWR",
"pattern": "GND"
},
{
"netclass": "LVDS",
"pattern": "/ADC/*_N"
},
{
"netclass": "LVDS",
"pattern": "/ADC/*_P"
},
{
"netclass": "LVDS",
"pattern": "*USRIO*"
}
]
},
"pcbnew": {
"last_paths": {