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Changed Relay & Flash + 1st pass BOM optimizations

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This commit is contained in:
Aleksa Bjelogrlic 2024-12-17 01:59:46 -05:00
parent 4fd001f041
commit f9a3bc2b47
19 changed files with 4000 additions and 3325 deletions

Hardware/KiCad/Thunderscope_Rev5/ACQ_FE_VREG.kicad_sch
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1 2 3 4 5 6 1 2 3 4 5 6 D C B A D C B A Date: Size: A4 Id: / File: blob_7b4a7b2584bfa5ac9fa3823fa79a2d6ab0b3d8bf_562629077.kicad_sch Sheet: / KiCad E.D.A. eeschema 8.99 Aleksa Bjelogrlic Title: ThunderScope Rev: 5 EEVengers C120 10uF R111 10K TP35 R105 20k R97 0.01 C108 10uF IN 10 PAD 11 PG 5 SS_CTRL 6 EN 7 OUT 2 NR/SS 8 FB 3 GND 4 OUT 1 IN 9 U15 TPS7A9101 TP28 TP4 C106 10uF EN 3 IN 1 GND 2 OUT 5 NC 4 U9 TPS7A2033 R96 90.9k R101 10K C76 1uF R98 0.01 TP38 R109 280K R90 0.1 C124 100nF C125 1uF R102 4.7K C126 1uF TP34 TP29 TP1 TP40 C110 10uF C117 10uF C115 10uF C128 22uF L1 1uH R99 4.7K TP39 TP31 C111 10uF R93 280K FB 3 SS_CTRL 6 PAD 11 PG 5 IN 9 GND 4 EN 7 OUT 1 OUT 2 NR/SS 8 IN 10 U14 TPS7A9101 TP26 R89 0.01 C119 10uF C109 10uF C127 22uF R104 4.7K C114 10uF TP37 TP22 R106 0.1 C121 10uF EN 3 IN 1 GND 2 OUT 5 NC 4 U16 TPS7A2033 R91 0.1 C77 100nF R14 0.01 TP30 R103 20k C122 10uF EN 6 PAD 9 C1+ 8 VOUT 4 VFB 5 VIN 1 CPOUT 3 C1- 7 GND 2 U13 LM27761 R100 20k TP21 TP27 TP32 R110 35.7k C116 10uF TP36 TP33 C112 1uF C118 10uF FB 1 SW 5 EN 2 VIN 3 VOUT 6 GND 4 U17 TPS61023 R94 10K C107 10uF C123 100nF -5V +3V3_ACQ +5V GND GND GND GND +2V5 GND PWR_FLAG PWR_FLAG GND GND +VUSB GND GND GND GND GND GND GND GND +5V2 GND PWR_FLAG GND +VUSB GND GND PWR_FLAG +3V3_PGA GND +5V PWR_FLAG GND +1V8_ACQ GND PWR_FLAG GND GND +5V2 +5V2 GND GND GND GND GND GND GND +3V3_ACQ PWR_FLAG GND GND GND GND FE_PG FE_EN ACQ_PG ACQ_EN Vout = 0.8 * (20/3.8 +1) Tss = 0.0129s = 13ms 5V: 728mA post-config 3.3/5 = 66.7% efficiency 5V: 968mA pre-config 5V2: 1.05A pre-config, 0.807A post-config Vout = 0.8 * (R1/R2 +1) Tss = (0.8 × 100nF) / 6.2uA [for SS_CTRL = GND] Vout = -1.22V*(R1+R2)/R2 Vout = 0.8 * (4.7/3.8 +1) Vout = (280/35.7+1)*0.6 = 5.31V 5V: 68.4mA, 70.6mA measured 6ms soft start time on previous LDO, need same or greater Vout = 0.8 * (R1/R2 +1) 85% measured efficiency DONE: Hook up power good, pull up is in FPGA IO Banks Vout = 5.01V 1.8/2.5 = 72% efficiency DONE: Hook up power good, pull up is in FPGA IO Banks Vout = 1.79V Front End Voltage Regulators 5V2: 79.4mA measured Total: 529mA Expected 543mA Measured Acquisition Voltage Regulators Vout = -1.22*(280/90.9+1)= -4.98V Tss = (VREF × Cnr/ss) / Inr/ss The value for R2 must be no less than 50 kΩ. R93 300K R108 680K R109 90.9k R96 90.9k R109 280K R93 280K R110 35.7k GND Vout = -1.22V*(R1+R2)/R2 Vout = (280/35.7+1)*0.6 = 5.31V Vout = -1.22*(280/90.9+1)= -4.98V The value for R2 must be no less than 50 kΩ.
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Hardware/KiCad/Thunderscope_Rev5/ADC.kicad_sch
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1 2 3 4 5 6 1 2 3 4 5 6 D C B A D C B A Date: Size: A4 Id: / File: blob_1d81dcce0cac96c2c333840e2f4e7ce08b308b66_1682198908.kicad_sch Sheet: / KiCad E.D.A. eeschema 8.99 Aleksa Bjelogrlic Title: ThunderScope Rev: 5 EEVengers R18 100 C17 1nF C14 10nF C25 10nF C12 1uF C15 10nF C18 10nF FB1 120@100MHZ C26 1uF C24 1nF C19 10nF R19 100 C21 1uF R22 100 C27 100nF TP5 R16 10K R17 10K C16 1nF FB2 120@100MHZ TP11 SCLK 4 SDATA 3 IN1- 46 IN3+ 41 IN1+ 47 IN2- 43 RSTn 5 IN3- 40 IN4+ 38 IN2+ 44 PD 6 VCM 48 CSn 2 FCLK- 20 D3B+ 23 D1B+ 11 D4A- 26 D4B+ 27 D1A- 10 EPAD 49 LCLK+ 17 CLK+ 35 D3B- 24 IN4- 37 D1A+ 9 D2B- 16 D2A+ 13 D3A+ 21 D1B- 12 D2A- 14 AVSS2 31 CLK- 34 OVDD 33 D2B+ 15 AVDD 36 DVDD 7 LCLK- 18 D3A- 22 AVSS 45 AVDD 1 DVSS 29 D4B- 28 DVDD 30 AVSS 42 DVSS 8 AVDD2 32 FCLK+ 19 D4A+ 25 AVSS 39 U6 HMCAD1520 TP12 R20 100 C13 1uF R21 100 C20 1uF C22 1uF R15 10K TP10 C23 10nF GND GND GND GND GND GND +3V3_ACQ GND GND GND PWR_FLAG GND GND GND +1V8_ACQ GND GND PWR_FLAG GND GND GND GND +1V8_ACQ +3V3_ACQ GND FCLK_N D1A_N LCLK_N D2B_P D3A_P D4B_N ADC_CSn FCLK_P D4A_P ADC_SCLK D3B_N D3B_P D4B_P D2B_N D2A_P +1V8D D1A_P ADC_SDATA D3A_N D2A_N ADC_PD D1B_P ADC_RSTn +1V8A LCLK_P D1B_N D4A_N IN4_N IN3_P ADC_CSn {ADC_LVDS} IN2_P IN1_P IN3_N ADC_CLK_N ADC_SDATA IN1_N IN2_N ADC_SCLK IN4_P VCM ADC_CLK_P 270mA Expected Use ADC reg 0x24 to invert 125mA Expected ADC 0.74W Measured All inputs have polarity swapped 0.71W Expected
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Hardware/KiCad/Thunderscope_Rev5/CON_PCIe_X4.kicad_sch
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1 2 3 4 5 6 1 2 3 4 5 6 D C B A D C B A Date: Size: A4 Id: / File: blob_627112d3b807630629164d9297e61c9e194d6bfd_1754822283.kicad_sch Sheet: / KiCad E.D.A. eeschema 8.99 Aleksa Bjelogrlic Title: ThunderScope Rev: 5 EEVengers R42 0.01 A2 A4 A10 A3 A5 A8 A11 A1 A6 A7 A9 B6 B16 B17 B8 B13 B2 A12 B14 B4 B9 B12 B15 A13 A18 B1 B3 B5 A15 A14 A16 A17 B7 B10 B11 B30 B31 B29 B32 B28 B23 B24 A23 B22 A27 B26 A26 B18 A32 B25 B27 A19 A21 A30 A29 B19 A25 A20 A22 A28 B20 A31 A24 B21 P1 PCIeX4-GF-2D-1000-1K-O64 R41 0 SHLD1 9204 TP14 5015 TP15 5015 +12V_IN GND GND GND 3.3Vaux PCIe_PER0_P PCIe_PET3_P PCIe_PER3_N +12V_PCIe PRSNT2#_1 GND PCIe_PER0_N WAKE# GND GND GND GND PCIe_PET0_N PCIe_PER1_N GND +12V_PCIe PCIe_PET0_P PCIe_PET1_N PCIe_PET3_P PCIe_PER3_N +3V3_PCIe GND PCIe_REFCLK_P GND SMDAT PCIe_PER2_P GND PCIe_PET2_N GND PCIe_PERST# GND PCIe_PER2_N PCIe_PET1_P PCIe_PET3_N PCIe_PER1_P PCIe_PER0_P PCIe_PER1_N +12V_PCIe PCIe_PER2_N PCIe_PET0_P GND PCIe_PER0_N PCIe_PET1_N GND PCIe_PET3_N JTAG3 PCIe_PET0_N JTAG5 +3V3_PCIe +12V_PCIe PCIe_PET2_P SMCLK GND PCIe_PER1_P PCIe_REFCLK_N +12V_PCIe GND JTAG4 PCIe_REFCLK_N PCIe_PER2_P GND PCIe_PET2_P JTAG2 PRSNT1# PCIe_PET2_N PCIe_PERST# PCIe_PET1_P GND PCIe_PER3_P +12V_PCIe JTAG1 GND PCIe_REFCLK_P PCIe_PER3_P GND GND +3V3_PCIe PRSNT2#_4 PCIe_REFCLK_P PCIe_REFCLK_N {PCIe_RX} {PCIe_TX} PCIe_PERST# RSVD RSVD TODO: 12V to VUSB Buck Regulator PCIe bracket RSVD PCIe x4 Edge Connector RSVD
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Hardware/KiCad/Thunderscope_Rev5/FE.kicad_sch
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1 2 3 4 5 6 1 2 3 4 5 6 D C B A D C B A Date: Size: A4 Id: / File: blob_6b7cd1cded5e18e654e37f00a9fe4507c7310fd1_2212503046.kicad_sch Sheet: / KiCad E.D.A. eeschema 8.99 Aleksa Bjelogrlic Title: ThunderScope Rev: 5 EEVengers R12 10K R10 10K C7 100nF R11 10K 10k 10k R13 10K R9 10K TP8 + 3 OUT 6 - 2 V+ 7 N2 8 V- 4 N1 1 U5 OPA140AIDR Q1 DMN62D0UW TP7 LDACn 4 VOUTD 9 RDY 5 SCL 2 SDA 3 VOUTA 6 VOUTC 8 VSS 10 VDD 1 VOUTB 7 U3 MCP4728 C6 100nF VBIAS 1 VREF 5 GND 2 EN 3 VIN 4 U4 REF2025 C8 100nF VSS 6 P1B 7 P3W 1 P2W 14 P3B 2 P2B 13 P0B 10 P0W 9 SDA 5 HVC/A0 3 P1W 8 VDD 12 SCL 4 A1 11 U2 MCP4452-104E TP9 C5 100nF TP6 C3 100nF C4 100nF Q2 DMN62D0UW C11 100nF C2 100nF GND PWR_FLAG +VBIAS +5V +3V3_PGA GND +5V +3V3_PGA GND +VBIAS +5V GND +5V GND +5V GND -5V -5V GND GND GND GND -VBIAS TRIM_SDA TRIM_2 TRIM_SCL TRIM_4 VOUT3 TRIM_SCL_5V TRIM_SDA_5V U5- U5- VOUT4 TRIM_SCL_5V TRIM_1 VOUT2 VOUT1 TRIM_3 VOUT4 VOUT2 TRIM_[4..1] VOUT3 TRIM_SDA_5V VOUT1 TRIM_SCL TRIM_[4..1] TRIM_SDA Bias Voltage Generation Default I2C address: 0101100 Offset Voltage Trim and User Offset Control Use VREF For OUR +VBIAS Default I2C address: 1100000 DONE: Use 100kOhm digipot VBIAS Pin is 1/2 of 2.5V VREF
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Hardware/KiCad/Thunderscope_Rev5/FE_Channel.kicad_sch
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1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 E D C B A E D C B A Date: Size: A3 Id: / File: blob_d3600cfeaf46ee06076dfeb4ce077f248f9cdffb_421323646.kicad_sch Sheet: / KiCad E.D.A. eeschema 8.99 Aleksa Bjelogrlic Title: ThunderScope Rev: 5 EEVengers 4 2 3 K1000B1A Q1004B1 DMN62D0UW 8 1 K1000B1C FTR-B3SA4.5Z R1043B1 2K R1050B1 10K + 3 - 2 OUT 6 V+ 7 N2 8 N1 1 V- 4 U1011B1 OPA140AIDR C1033B1 100nF C1035B1 220pF C1042B1 100nF R1045B1 1K R1037B1 49.9 R1027B1 30 C1024B1 2.4pF J3B1 UFL Q1003B1 DMN62D0UW R1029B1 10K R1021B1 30 C1037B1 10nF R1030B1 10K TP1015B1 C1027B1 10uF R97B1 0 TP1017B1 C1028B1 10uF FB1000B1 120@100MHZ C1044B1 1uF C1048B1 1uF R1041B1 90.9k C1025B1 12pF C1029B1 10uF R1036B1 35.7k C1047B1 1uF D1001B1 1N4148 SHLD1000B1 2118727-2 6 7 5 K1000B1B C1038B1 100nF C1052B1 1uF C1050B1 1uF C1055B1 1uF C1021B1 12pF R1042B1 90.9k R1022B1 10 R1024B1 976k R1035B1 30 SHLD1001B1 2118728-2 R1044B1 10K 8 1 K1001B1C FTR-B3SA4.5Z R1033B1 10K C1022B1 8pF R1026B1 20k R1049B1 5K TRIMPOT AUX_P 1 VDD 12 OUT_N 14 GND 8 PAD 17 SCLK 11 OUT_P 15 VCC 3 VCC 4 IN_P 6 AUX_N 2 AUX_VCM 16 VCM 13 GND 5 IN_N 7 SDIO 10 CSn 9 U1008B1 LMH6518 R1046B1 1K IN 2 PAD 17 IN_Aux 4 NC 9 Vso- 10 Vso+ 12 NC 13 Vs+ 1 IN_Bias 3 Vs- 5 Aux_Bias 6 Vs- 8 OUT 11 CLL 14 NC 16 R_Bias 7 CLH 15 U1009B1 BUF802 C1053B1 1uF TP1014B1 C1041B1 100nF C1034B1 100pF J1002B1 BNC J4B1 UFL C1030B1 1.2nF FB1001B1 120@100MHZ R1028B1 30 R1038B1 909k TP1018B1 R1052B1 10K C1026B1 10uF C1031B1 22nF C1043B1 100nF C1023B1 2.4pF R1032B1 10K R1048B1 DNP C1049B1 1uF C1039B1 1uF NO 2 COM 1 V+ 5 V- 3 IN 4 U1010B1 TS12A4516 C1046B1 1uF C1032B1 100nF 6 7 5 K1001B1B 4 2 3 K1001B1A R1051B1 10K C1057B1 1uF R1031B1 10K C1056B1 1uF TP1016B1 C1051B1 1uF C1036B1 1nF R1039B1 909k C1045B1 1uF C1040B1 1uF R1047B1 90.9k C1054B1 1uF R52B1 0 Q1002B1 DMN62D0UW R1023B1 30 R1025B1 49.9 D1000B1 1N4148 GND GND GND GND GND +5V GND GND GND -VBIAS GND GND +3V3_PGA -5V +3V3_PGA PWR_FLAG GND +5V GND +5V +VUSB GND GND GND GND GND GND +3V3_PGA +VBIAS +VUSB GND +5V GND GND GND GND GND GND GND GND GND -5V GND +5V GND GND -5V +5V GND -5V GND GND GND GND GND DC_CPLn +VPGA ATTEN_OUT DC_CPLn OUT_R_N OUT_R_P ATTEN_OUT +VPGA OUT_N DC_CPL PGA_CSn PGA_SCLK TRIM PGA_SDIO VCM TERM OUT_P ATTEN WK73R2ATTD49R9F DONE: Revert back to non-latched relays to avoid indeterminate state when powered off Termination and Attenuation We add 30 ohms, so relay voltage will be 3.936V at minimum VUSB of 4.75V Input Buffer and AC/DC Coupling DONE: Remove FB4 and FB6 DONE: Revert to Mechanical Trimpot DONE: change to 35.7k Max current for 35.7kOhm R_Bias: 24mA @ V+ and 24mA @ V- FTR-B3SA4.5Z has 145 Ohm Coil Resistance, 3.38V Must Operate Voltage 100k R_Bias wil be lower: 17mA per rail was measured on the EVM DONE: change to 1.2nF DONE: change to 220pF DONE: connect CLL directly to GND 80uA @ V+ and 80uA @ V- DONE: change to 976k Max VDD current: 0.35mA DONE: remove ferrites on +/-5V to make planes easier to keep away from signal Max VCC current before configuration (AUX output on): 0.225A Max VCC current after configuration turns off AUX output: 0.165A DONE: change to 50 ohm 0508 Programmable Gain Amplifier DONE: change to 50Ohm 50x Attenuator DONE: Change Relays to 4.5V Parts as we are now powering them w/ +VUSB FTR-B3SA003Z has 64.3 Ohm Coil Resistance, 2.25V Must Operate Voltage, 0.051A @ 3.3V All 4.5V relays tested worked down to 3V 4 2 3 K1000B1A 8 1 K1000B1C FTR-B3SA4.5Z R1027B1 30 6 7 5 K1000B1B 8 1 K1001B1C FTR-B3SA4.5Z R1028B1 30 6 7 5 K1001B1B 4 2 3 K1001B1A DONE: Revert back to non-latched relays to avoid indeterminate state when powered off We add 30 ohms, so relay voltage will be 3.936V at minimum VUSB of 4.75V FTR-B3SA4.5Z has 145 Ohm Coil Resistance, 3.38V Must Operate Voltage DONE: change to 976k DONE: Change Relays to 4.5V Parts as we are now powering them w/ +VUSB
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Hardware/KiCad/Thunderscope_Rev5/FPGA.kicad_sch
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1 2 3 4 5 6 1 2 3 4 5 6 D C B A D C B A Date: Size: A4 Id: / File: blob_52842b2c43b922f3fdab6d7f9a2670b5bd16f40a_2175352673.kicad_sch Sheet: / KiCad E.D.A. eeschema 8.99 Aleksa Bjelogrlic Title: ThunderScope Rev: 5 EEVengers C32 100nF C38 100nF R28 0 C47 100nF R39 0 2 2 1 1 5 5 4 4 6 6 3 3 J5 R36 0 C39 100nF R37 0 R34 0 C35 100nF R30 0 R27 0 R24 49.9 C45 100nF C29 100nF C40 100nF C37 100nF TP13 C28 100nF R38 0 C34 100nF C30 100nF C43 100nF R23 49.9 C33 100nF C42 100nF C41 100nF C44 100nF C31 100nF R40 0 R26 0 C46 100nF R32 0 R33 0 R29 0 R35 0 R31 0 C36 100nF R25 0 +3V3 GND PCIe_PER2_P M2_PET0_N MGT_RX3_N PCIe_PET3_P PCIe_PET2_N M2_PER0_P M2_PET0_P PCIe_PET1_N PCIe_PET2_N MGT_TX1_P MGT_TX0_N M2_PERST# M2_PER1_N MGT_CLK1_N PCIe_PET3_N MGT_TX0_P MGT_CLK1_P MGT_RX3_N MGT_RX1_P M2_PET1_P M2_PET1_N PCIe_PET0_N M2_PER2_P PCIe_REFCLK_N PCIe_PET1_P MGT_TX2_N M2_PER3_N M2_PET2_P M2_PER0_N PCIe_PER1_P M2_PET1_N M2_PER3_P TMS MGT_RX0_P M2_PER1_P PCIe_PET0_P MGT_TX0_N MGT_RX1_N MGT_RX1_N PCIe_PER3_N PCIe_PER1_N PCIe_PER3_P M2_PET0_N PCIe_PER0_N PCIe_PET2_P MGT_RX2_P PCIe_PET3_P PCIe_PET3_N PCIe_PET2_P M2_PET0_P MGT_TX3_N MGT_TX1_N MGT_TX3_P PCIe_PER3_P PCIe_PER2_N M2_PER3_N PCIe_PER3_N TDO MGT_RX0_P PERST# MGT_RX3_P TDI M2_PET3_P PCIe_PER0_N M2_PET3_N M2_PER1_P MGT_RX3_P M2_PET2_N M2_PER0_P M2_PER1_N M2_PET3_P PCIe_PET1_N M2_PER0_N MGT_TX1_N M2_PET2_P PCIe_PER0_P M2_PET3_N MGT_RX2_P MGT_RX2_N MGT_RX2_N M2_PER2_N TCK MGT_CLK1_N PCIe_PERST# PCIe_PER2_P PCIe_PER1_N MGT_TX2_P M2_PER2_P PCIe_PET1_P PCIe_PET0_N M2_PER3_P MGT_CLK1_P MGT_TX2_N MGT_TX3_P MGT_TX3_N MGT_RX0_N PCIe_REFCLK_P PCIe_PER0_P MGT_TX1_P M2_REFCLK_N M2_PET2_N PERST# M2_REFCLK_P PCIe_PER1_P PCIe_PET0_P MGT_RX1_P M2_PER2_N PCIe_PER2_N MGT_RX0_N MGT_TX2_P M2_PET1_P MGT_TX0_P PLL_SDA M2_REFCLK_N M2_REFCLK_P ACQ_PG ATTEN_[4..1] FE_PG {PCIe_TX} PCIe_REFCLK_P DC_CPL_[4..1] SYNC_OUT_N {ADC_LVDS} ADC_SDIO {LED_RGB} TRIM_SCL TRIM_SDA SYNC_OUT_P SYNC_REn SYNC_DE TERM_[4..1] M2_PERST# {USRIO} ADC_SCLK SYNC_IN_P PCIe_PERST# PGA_SCLK FE_EN {M2_TX} PCIe_REFCLK_N PLL_SCL PGA_CSn_[4..1] PROBE_COMP {M2_RX} ADC_CSn ACQ_EN SYNC_IN_N {PCIe_RX} OSC_OE PGA_SDIO FPGA Power Inputs File: FPGA_PWR.kicad_sch FPGA IO Banks File: FPGA_Bank_IO.kicad_sch FE_EN PROBE_COMP OSC_OE ATTEN_[4..1] TERM_[4..1] DC_CPL_[4..1] PGA_CSn_[4..1] QSPI_CLK ADC_CSn PERST# ADC_SDIO ADC_SCLK PLL_SCL PLL_SDA ACQ_EN PGA_SCLK PGA_SDIO TRIM_SCL TRIM_SDA SYNC_OUT_N SYNC_OUT_P SYNC_IN_P SYNC_IN_N {ADC_LVDS} {USRIO} FE_PG ACQ_PG SYNC_DE SYNC_REn {LED_RGB} FPGA Voltage Regs File: FPGA_VREG.kicad_sch FPGA Transceivers File: FPGA_MGT.kicad_sch MGT_TX3_N MGT_TX2_N MGT_TX1_N MGT_TX0_N MGT_TX3_P MGT_TX2_P MGT_TX1_P MGT_TX0_P MGT_RX3_N MGT_RX3_P MGT_RX2_N MGT_RX2_P MGT_RX1_N MGT_RX1_P MGT_RX0_N MGT_RX0_P MGT_CLK1_N MGT_CLK1_P FPGA Configuration File: FPGA_CFG.kicad_sch TDI TDO TCK TMS QSPI_CLK AC Couple PER Lines with 100nF AC Couple REFCLK Lines with 100nF PCIe Stuffing Options Digilent JTAG Header FPGA
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Hardware/KiCad/Thunderscope_Rev5/FPGA_Bank_IO.kicad_sch
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1 2 3 4 5 6 1 2 3 4 5 6 D C B A D C B A Date: Size: A4 Id: / File: blob_37122ac82996df478050d726d6bd3ea450552747_4288244704.kicad_sch Sheet: / KiCad E.D.A. eeschema 8.99 Aleksa Bjelogrlic Title: ThunderScope Rev: 5 EEVengers R66 10K BANK 15 IO_L1P_T0_AD0P_15 D8 IO_L17P_T2_A26_15 E17 IO_L18N_T2_A23_15 C18 IO_L7N_T1_AD2N_15 A12 IO_L13N_T2_MRCC_15 D15 IO_L20N_T3_A19_15 G16 IO_L21N_T3_DQS_A18_15 F15 IO_L22N_T3_A16_15 F14 IO_L4N_T0_15 B11 IO_L9P_T1_DQS_AD3P_15 C14 IO_L10N_T1_AD11N_15 A15 IO_L16P_T2_A28_15 C16 IO_L10P_T1_AD11P_15 B14 IO_L17N_T2_A25_15 D18 IO_0_15 D10 IO_L3P_T0_DQS_AD1P_15 B9 IO_L3N_T0_DQS_AD1N_15 A9 IO_L5N_T0_AD9N_15 A10 IO_L4P_T0_15 C11 IO_L7P_T1_AD2P_15 B12 IO_L11N_T1_SRCC_15 C13 IO_L12P_T1_MRCC_15 E13 IO_L14N_T2_SRCC_15 D16 IO_L15N_T2_DQS_ADV_B_15 A17 IO_L5P_T0_AD9P_15 B10 IO_L14P_T2_SRCC_15 E16 IO_L6N_T0_VREF_15 C12 IO_L1N_T0_AD0N_15 C8 IO_L2N_T0_AD8N_15 C9 IO_L6P_T0_15 D11 IO_L8P_T1_AD10P_15 A13 IO_L11P_T1_SRCC_15 D13 IO_L12N_T1_MRCC_15 D14 IO_L15P_T2_DQS_15 B16 IO_L2P_T0_AD8P_15 D9 IO_L8N_T1_AD10N_15 A14 IO_L9N_T1_DQS_AD3N_15 B15 IO_L13P_T2_MRCC_15 E15 IO_L16N_T2_A27_15 B17 IO_L18P_T2_A24_15 C17 IO_L19P_T3_A22_15 G17 IO_L19N_T3_A21_VREF_15 F18 IO_L20P_T3_A20_15 H16 IO_L21P_T3_DQS_15 G15 IO_L22P_T3_A17_15 G14 IO_L23P_T3_FOE_B_15 H17 IO_L23N_T3_FWE_B_15 H18 IO_L24P_T3_RS1_15 F17 IO_L24N_T3_RS0_15 E18 IO_25_15 H14 U18B IC FPGA XC7A50T-2CSG325C C130 100nF BANK 14 IO_L21P_T3_DQS_14 V12 IO_L21N_T3_DQS_A06_D22_14 V13 IO_L19N_T3_A09_D25_VREF_14 T13 IO_L17N_T2_A13_D29_14 U16 IO_L17P_T2_A14_D30_14 U15 IO_L18N_T2_A11_D27_14 V17 IO_L19P_T3_A10_D26_14 R13 IO_L18P_T2_A12_D28_14 V16 IO_L20P_T3_A08_D24_14 U14 IO_L20N_T3_A07_D23_14 V14 IO_25_14 U10 IO_L22P_T3_A05_D21_14 T12 IO_L23N_T3_A02_D18_14 V11 IO_L24N_T3_A00_D16_14 V9 IO_L23P_T3_A03_D19_14 U11 IO_L22N_T3_A04_D20_14 U12 IO_L24P_T3_A01_D17_14 U9 IO_L13N_T2_MRCC_14 T15 IO_L3N_T0_DQS_EMCCLK_14 K18 IO_L7N_T1_D10_14 M17 IO_L8P_T1_D11_14 M14 IO_L16P_T2_CSI_B_14 T17 IO_L8N_T1_D12_14 N14 IO_L16N_T2_A15_D31_14 U17 IO_L1P_T0_D00_MOSI_14 K16 IO_L1N_T0_D01_DIN_14 L17 IO_L4P_T0_D04_14 K17 IO_L5P_T0_D06_14 J14 IO_L2N_T0_D03_14 J16 IO_0_14 L14 IO_L2P_T0_D02_14 J15 IO_L5N_T0_D07_14 K15 IO_L6N_T0_D08_VREF_14 M15 IO_L4N_T0_D05_14 L18 IO_L7P_T1_D09_14 M16 IO_L9N_T1_DQS_D13_14 N17 IO_L6P_T0_FCS_B_14 L15 IO_L9P_T1_DQS_14 N16 IO_L10P_T1_D14_14 N18 IO_L10N_T1_D15_14 P18 IO_L3P_T0_DQS_PUDC_B_14 J18 IO_L11P_T1_SRCC_14 P15 IO_L11N_T1_SRCC_14 P16 IO_L12P_T1_MRCC_14 P14 IO_L12N_T1_MRCC_14 R15 IO_L13P_T2_MRCC_14 T14 IO_L14P_T2_SRCC_14 R16 IO_L14N_T2_SRCC_14 R17 IO_L15P_T2_DQS_RDWR_B_14 R18 IO_L15N_T2_DQS_DOUT_CSO_B_14 T18 U18A IC FPGA XC7A50T-2CSG325C R67 10K BANK 34 IO_L5P_T0_34 L4 IO_L6N_T0_VREF_34 M5 IO_L1P_T0_34 K6 IO_L4P_T0_34 K3 IO_L8N_T1_34 N6 IO_L7P_T1_34 M2 IO_L2P_T0_34 J5 IO_L2N_T0_34 J4 IO_L3N_T0_DQS_34 K1 IO_L4N_T0_34 L2 IO_L7N_T1_34 M1 IO_L5N_T0_34 L3 IO_L3P_T0_DQS_34 K2 IO_L9P_T1_DQS_34 N1 IO_L8P_T1_34 M6 IO_L9N_T1_DQS_34 P1 IO_L1N_T0_34 K5 IO_L6P_T0_34 L5 IO_0_34 J6 IO_L16N_T2_34 V2 IO_L22P_T3_34 R7 IO_25_34 R6 IO_L21N_T3_DQS_34 T5 IO_L10P_T1_34 M4 IO_L11N_T1_SRCC_34 N2 IO_L13N_T2_MRCC_34 R1 IO_L20N_T3_34 U5 IO_L18N_T2_34 V4 IO_L14N_T2_SRCC_34 T2 IO_L15N_T2_DQS_34 U1 IO_L17N_T2_34 T3 IO_L23N_T3_34 V6 IO_L24P_T3_34 V8 IO_L15P_T2_DQS_34 U2 IO_L12P_T1_MRCC_34 P4 IO_L13P_T2_MRCC_34 R2 IO_L18P_T2_34 U4 IO_L20P_T3_34 U6 IO_L11P_T1_SRCC_34 N3 IO_L24N_T3_34 V7 IO_L23P_T3_34 U7 IO_L19N_T3_VREF_34 P5 IO_L16P_T2_34 V3 IO_L17P_T2_34 T4 IO_L12N_T1_MRCC_34 P3 IO_L14P_T2_SRCC_34 R3 IO_L19P_T3_34 P6 IO_L21P_T3_DQS_34 R5 IO_L22N_T3_34 T7 IO_L10N_T1_34 N4 U18C IC FPGA XC7A50T-2CSG325C R68 10K SO/SIO1 2 WP#/SIO2 3 HOLD#/SIO3 7 VCC 8 SI/SIO0 5 CS# 1 SCLK 6 GND 4 PAD 9 U19 MX25L6433FZNI-08G R59 10K R112 100 R58 10K C129 100nF EN 1 GND 2 OUT 3 VDD 4 Y2 25MHz +3V3 GND GND +3V3 +3V3 +3V3 +3V3 +3V3 +3V3 GND +3V3 D3B_P USRIO_2_N ACQ_PG USRIO_3_P ATTEN_2 ACQ_EN PUDC QSPI_CS TRIM_SDA ATTEN_3 QSPI_CLK DC_CPL_1 USRIO_11_P PGA_CSn_3 ATTEN_[4..1] D4B_P LCLK_P USRIO_2_P TERM_[4..1] USRIO_8_N USRIO_12_P USRIO_5_N QSPI_DQ0 USRIO_7_P D2B_P D2A_P USRIO_10_N LED_B PGA_CSn_2 TERM_4 QSPI_DQ3 USRIO_4_P LED_R QSPI_DQ1 TRIM_SCL D3A_N USRIO_5_P D4A_P SYNC_DE ADC_SDIO D4A_N FCLK_P DC_CPL_[4..1] D3A_P PGA_CSn_[4..1] FCLK_N USRIO_8_P USRIO_6_P TERM_1 TERM_3 D2A_N QSPI_DQ1 USRIO_9_P D3B_N USRIO_7_N DC_CPL_2 D1A_P LCLK_N TERM_2 PLL_SDA ADC_CSn CLK25 ATTEN_4 LED_G PROBE_COMP USRIO_1_P PGA_CSn_1 ATTEN_1 FE_EN DC_CPL_3 D4B_N OSC_OE QSPI_DQ2 USRIO_6_N DC_CPL_4 PGA_SDIO PGA_SCLK USRIO_12_N PERST# PLL_SCL QSPI_CS USRIO_10_P D1A_N D2B_N D1B_N USRIO_9_N D1B_P FE_PG QSPI_DQ2 QSPI_DQ0 PGA_CSn_4 USRIO_1_N ADC_SCLK USRIO_3_N CLK25 USRIO_11_N SYNC_REn QSPI_DQ3 USRIO_4_N {LED_RGB} SYNC_DE TRIM_SDA ACQ_PG PLL_SCL ADC_CSn QSPI_CLK {ADC_LVDS} PERST# ADC_SCLK ADC_SDIO PGA_SCLK SYNC_IN_N SYNC_REn {USRIO} ACQ_EN PGA_SDIO TRIM_SCL SYNC_OUT_P PLL_SDA FE_PG ATTEN_[4..1] TERM_[4..1] SYNC_IN_P PROBE_COMP SYNC_OUT_N DC_CPL_[4..1] OSC_OE FE_EN PGA_CSn_[4..1] D3B Inversion! D2A Inversion! D4A Inversion! D2B Inversion! FPGA IO Banks NOTE: CLK25 to be connected to MRCC pin DONE: Pullups on CS, DQ2, DQ3 DONE: Replace QSPI with 3V3 capable part D4B Inversion! BANK 34 IO_L5P_T0_34 L4 IO_L6N_T0_VREF_34 M5 IO_L1P_T0_34 K6 IO_L4P_T0_34 K3 IO_L8N_T1_34 N6 IO_L7P_T1_34 M2 IO_L2P_T0_34 J5 IO_L2N_T0_34 J4 IO_L3N_T0_DQS_34 K1 IO_L4N_T0_34 L2 IO_L7N_T1_34 M1 IO_L5N_T0_34 L3 IO_L3P_T0_DQS_34 K2 IO_L9P_T1_DQS_34 N1 IO_L8P_T1_34 M6 IO_L9N_T1_DQS_34 P1 IO_L1N_T0_34 K5 IO_L6P_T0_34 L5 IO_0_34 J6 IO_L16N_T2_34 V2 IO_L22P_T3_34 R7 IO_25_34 R6 IO_L21N_T3_DQS_34 T5 IO_L10P_T1_34 M4 IO_L11N_T1_SRCC_34 N2 IO_L13N_T2_MRCC_34 R1 IO_L20N_T3_34 U5 IO_L18N_T2_34 V4 IO_L14N_T2_SRCC_34 T2 IO_L15N_T2_DQS_34 U1 IO_L17N_T2_34 T3 IO_L23N_T3_34 V6 IO_L24P_T3_34 V8 IO_L15P_T2_DQS_34 U2 IO_L12P_T1_MRCC_34 P4 IO_L13P_T2_MRCC_34 R2 IO_L18P_T2_34 U4 IO_L20P_T3_34 U6 IO_L11P_T1_SRCC_34 N3 IO_L24N_T3_34 V7 IO_L23P_T3_34 U7 IO_L19N_T3_VREF_34 P5 IO_L16P_T2_34 V3 IO_L17P_T2_34 T4 IO_L12N_T1_MRCC_34 P3 IO_L14P_T2_SRCC_34 R3 IO_L19P_T3_34 P6 IO_L21P_T3_DQS_34 R5 IO_L22N_T3_34 T7 IO_L10N_T1_34 N4 U18C IC FPGA XC7A50T-2CSG325C SO/SIO1 2 WP#/SIO2 3 HOLD#/SIO3 7 VCC 8 SI/SIO0 5 CS# 1 SCLK 6 GND 4 PAD 9 U19 MX25L6433FZNI-08G EN 1 GND 2 OUT 3 VDD 4 Y2 25MHz DONE: Replace QSPI with 3V3 capable part

Hardware/KiCad/Thunderscope_Rev5/FPGA_CFG.kicad_sch
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1 2 3 4 5 6 1 2 3 4 5 6 D C B A D C B A Date: Size: A4 Id: / File: blob_cd9f21fa386896b7cdff2e025632ca3eb32e200a_3779316298.kicad_sch Sheet: / KiCad E.D.A. eeschema 8.99 Aleksa Bjelogrlic Title: ThunderScope Rev: 5 EEVengers R113 4.7K TP44 FB11 120@100MHZ TP43 TP45 M2_0 F13 VN_0 L9 M1_0 R11 TDI_0 T9 TDO_0 T8 DONE_0 F12 VREFP_0 L10 TCK_0 F8 CFGBVS_0 E12 DXN_0 M9 VP_0 K10 PROGRAM_B_0 P10 DXP_0 M10 INIT_B_0 T10 TMS_0 R8 VREFN_0 K9 CCLK_0 E8 M0_0 R12 U18D IC FPGA XC7A50T-2CSG325C R114 4.7K +3V3 GND GND AGND TMS TCK TDO QSPI_CLK TDI TMS QSPI_CLK TCK TDO TDI FPGA Configuration M[2:0] = 001
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Hardware/KiCad/Thunderscope_Rev5/FPGA_MGT.kicad_sch
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1 2 3 4 5 6 1 2 3 4 5 6 D C B A D C B A Date: Size: A4 Id: / File: blob_f6f19c12e32b81489447c9444c49a72f471c9d88_1993117637.kicad_sch Sheet: / KiCad E.D.A. eeschema 8.99 Aleksa Bjelogrlic Title: ThunderScope Rev: 5 EEVengers R115 100 MGTPTXN1_216 F1 MGTPRXN3_216 G3 MGTPRXP2_216 C4 MGTPTXP3_216 B2 MGTPRXN2_216 C3 MGTPTXN2_216 D1 MGTRREF_216 A6 MGTREFCLK1P_216 B6 MGTPTXN3_216 B1 MGTPRXP1_216 A4 MGTPRXP0_216 E4 MGTREFCLK0N_216 D5 MGTPTXP2_216 D2 MGTPRXN0_216 E3 MGTPTXN0_216 H1 MGTPTXP1_216 F2 MGTPTXP0_216 H2 MGTREFCLK0P_216 D6 MGTPRXP3_216 G4 MGTREFCLK1N_216 B5 MGTPRXN1_216 A3 U18E IC FPGA XC7A50T-2CSG325C +1V2_MGT MGT_TX0_N MGT_RX3_N MGT_RX1_P MGT_CLK1_P MGT_RX1_N MGT_TX2_N MGT_RX3_P MGT_RX2_N MGT_RX2_P MGT_TX3_P MGT_RX0_P MGT_TX0_P MGT_TX1_N MGT_CLK1_N MGT_TX2_P MGT_TX3_N MGT_TX1_P MGT_RX0_N MGT_RX3_P MGT_TX3_P MGT_TX2_P MGT_TX2_N MGT_RX0_P MGT_TX3_N MGT_RX3_N MGT_TX0_N MGT_RX1_N MGT_TX0_P MGT_TX1_N MGT_CLK1_P MGT_RX0_N MGT_RX2_P MGT_RX1_P MGT_CLK1_N MGT_TX1_P MGT_RX2_N FPGA Transceivers
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Hardware/KiCad/Thunderscope_Rev5/FPGA_PWR.kicad_sch
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1 2 3 4 5 6 1 2 3 4 5 6 D C B A D C B A Date: Size: A4 Id: / File: blob_a1edb0c07105a3e747d9e8517c1405cb4ecf8399_2645941924.kicad_sch Sheet: / KiCad E.D.A. eeschema 8.99 Aleksa Bjelogrlic Title: ThunderScope Rev: 5 EEVengers C150 470nF C170 100nF C148 470nF C147 4.7uF C155 470nF C151 470nF C160 100uF C157 470nF C144 47uF C159 4.7uF C165 470nF C139 470nF C162 4.7uF C141 470nF C169 100nF C163 4.7uF C166 470nF C152 47uF C156 470nF C146 4.7uF MGTAVCC B4 MGTAVTT G2 MGTAVTT E1 MGTAVCC C5 MGTAVTT F3 MGTAVCC F5 MGTAVCC E5 MGTAVTT C1 MGTAVTT A2 U18F IC FPGA XC7A50T-2CSG325C C142 4.7uF C167 470nF C161 47uF C153 47uF C145 47uF C143 4.7uF C138 470nF C149 470nF VCCO_14 U18 VCCO_14 V15 VCCO_34 V5 VCCO_15 D17 VCCO_14 U8 VCCO_14 T11 VCCO_14 P17 VCCO_15 A16 VCCO_15 G18 VCCO_15 H15 VCCO_34 P7 VCCO_0 R10 VCCO_14 L16 VCCO_15 E14 VCCO_15 B13 VCCO_0 E10 VCCO_34 L6 VCCO_34 R4 VCCO_34 T1 VCCO_14 R14 VCCO_15 C10 VCCO_34 M3 U18G IC FPGA XC7A50T-2CSG325C C171 100nF C154 470nF C164 470nF FB13 120@100MHZ FB12 120@100MHZ VCCINT F9 VCCINT F7 VCCINT L12 VCCINT G8 VCCINT M11 VCCAUX M13 VCCAUX P13 VCCINT J8 VCCINT N8 VCCAUX G12 VCCINT M7 VCCINT H7 VCCINT N10 VCCAUX H13 VCCAUX K13 VCCINT N12 VCCBATT_0 E11 VCCINT K11 VCCINT P11 VCCINT J12 VCCINT H9 VCCINT L8 VCCINT K7 VCCINT P9 VCCBRAM F11 VCCBRAM G10 VCCBRAM H11 VCCADC_0 J10 U18H IC FPGA XC7A50T-2CSG325C C173 4.7uF GND J1 GND A8 GND F10 GND G1 GND G6 GND H8 GND K14 GND K8 GND L1 GND M8 GND D7 GND N5 GND J11 GND D4 GND J2 GND N13 GND G11 GND G7 GND H3 GND H12 GND A11 GND E7 GND E9 GND G9 GND A7 GND C2 GND H4 GND A1 GND G13 GND H10 GND E2 GND C6 GND B8 GND C15 GND D3 GND A5 GND B3 GND A18 GND C7 GND F4 GND E6 GND F6 GND D12 GND F16 GND B7 GND B18 GND G5 GND H5 GND H6 GND J7 GND J3 GND J13 GND J17 GND K4 GND K12 GND L7 GND L11 GND L13 GND M12 GND M18 GND N7 GND N9 GND N11 GND P2 GND U13 GND R9 GND V10 GND P8 GND T16 GND N15 GND U3 GND V1 GND P12 GND V18 GNDADC_0 J9 GND T6 U18I IC FPGA XC7A50T-2CSG325C C172 100nF C158 4.7uF C140 470nF C168 4.7uF GND GND +1V0 GND +1V0 GND GND +1V8 GND GND GND PWR_FLAG GND +2V5 GND GND GND GND GND GND GND GND GND +1V0 PWR_FLAG GND GND GND PWR_FLAG GND AGND +1V0_MGT GND GND AGND +3V3 +1V2_MGT GND GND GND GND GND GND GND +3V3 GND GND GND GND GND GND GND FPGA Power Inputs
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Hardware/KiCad/Thunderscope_Rev5/FPGA_VREG.kicad_sch
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1 2 3 4 5 6 1 2 3 4 5 6 D C B A D C B A Date: Size: A4 Id: / File: blob_f763918aea5097285faf241127aeb49464df4eaf_964238701.kicad_sch Sheet: / KiCad E.D.A. eeschema 8.99 Aleksa Bjelogrlic Title: ThunderScope Rev: 5 EEVengers GND 1 EN 4 PG 6 FB 5 VIN 3 SW 2 U8 TPS62A02 R128 90.9k R120 0.01 C10 10uF R70 4.7K R116 0.01 C75 22uF C185 100nF FB 5 VIN 3 GND 1 SW 2 EN 4 PG 6 U20 TPS62A02 R56 20k C174 100pF R130 10K R69 4.7K R125 1K C182 10uF C178 100pF R123 0.01 L4 1uH TP50 R1 90.9k C9 10uF C184 10uF L3 1uH TP49 C180 22uF R129 10K R117 90.9k C176 22uF C187 10uF C183 10uF GND 1 EN 4 PG 6 FB 5 VIN 3 SW 2 U23 TPS62A02 L5 1uH R127 2K C74 100pF R124 10K R121 90.9k OUT 1 OUT 2 FB 3 GND 4 NR/SS 8 IN 9 IN 10 EN 7 PAD 11 SS_CTRL 6 PG 5 U22 TPS7A9101 R119 4.7K C181 10uF R55 90.9k R57 0.01 R122 20k GND 1 PG 6 FB 5 VIN 3 SW 2 EN 4 U21 TPS62A02 C71 10uF R118 10K L2 1uH C186 100pF C179 10uF TP51 C175 10uF C177 22uF C72 10uF C73 10uF R126 0.01 C188 22uF GND GND +1V0 +VUSB PWR_FLAG GND GND GND GND GND GND GND GND +1V8 PWR_FLAG GND GND GND GND GND GND GND GND GND +3V3 +2V5 +VUSB GND GND PWR_FLAG GND GND GND PWR_FLAG GND GND GND GND +VUSB GND +1V2_MGT +1V8 PWR_FLAG +VUSB PG_+1V0 PG_1V8 PG_1V8 PG_1V8 PG_1V8 PG_+1V0 The recommended power-on sequence to achieve minimum current draw for the GTP transceivers is VCCINT, VMGTAVCC, VMGTAVTT Vout = 0.8 * (1/2 +1) Vout = 0.6 * (R1/R2 + 1) Vout = 1.8V FPGA Voltage Regulators Vout = 0.6 * (20/10 + 1) Vout = 0.6 * (R1/R2 + 1) Vout = 0.6 * (90.9/20 + 1) Vout = 0.6 * (10/3.197 + 1) Vout = 1.2V 1V,1V,1.2V Vout = 3.327V Vout = 0.6 * (R1/R2 + 1) Vout = 0.8 * (R1/R2 +1) 1.2/1.8 = 66.7% efficiency Vout = 2.477V The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, and VCCO Vout = 0.6 * (R1/R2 + 1) Vout = 1.008V 1V,1V,1.8V,2.5V and 3.3V Vout = 0.6 * (3.197/4.7 + 1) R55 294K R129 294K R118 66.5k R1 = R2 x (Vout/0.6 -1) R1 = 200k TODO: Replace FB Resistor R1 = 90.9 x (2.5/0.6 -1) R1 = 100 x (1.8/0.6 -1) R1 = 100 x (1/0.6 -1) R1 = 66.67k R1 = R2 x (Vout/0.6 -1) R1 = 409.05k R1 = R2 x (Vout/0.6 -1) R128 90.9k R70 4.7K R116 0.01 R56 20k C174 100pF R130 10K R69 4.7K C178 100pF R1 90.9k R129 10K R117 90.9k C176 22uF C74 100pF R124 10K R121 90.9k R119 4.7K R55 90.9k R122 20k R118 10K C186 100pF C177 22uF GND PWR_FLAG GND GND Vout = 0.6 * (R1/R2 + 1) Vout = 1.8V Vout = 0.6 * (20/10 + 1) Vout = 0.6 * (R1/R2 + 1) Vout = 0.6 * (90.9/20 + 1) Vout = 0.6 * (10/3.197 + 1) Vout = 1.2V Vout = 3.327V Vout = 0.6 * (R1/R2 + 1) Vout = 2.477V Vout = 0.6 * (R1/R2 + 1) Vout = 1.008V Vout = 0.6 * (3.197/4.7 + 1)
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Hardware/KiCad/Thunderscope_Rev5/M2_KEY_M.kicad_sch
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1 2 3 4 5 6 1 2 3 4 5 6 D C B A D C B A Date: Size: A4 Id: / File: blob_6898a00212ca07368e15ca6f761e68b95e98dc78_4188135668.kicad_sch Sheet: / KiCad E.D.A. eeschema 8.99 Aleksa Bjelogrlic Title: ThunderScope Rev: 5 EEVengers R54 0.01 J11 7792 TP19 5015 23 17 35 41 31 39 57 9 13 21 43 67 53 71 75 25 4 6 5 2 3 7 27 1 11 15 19 29 33 37 49 47 51 45 55 69 8 10 73 18 74 36 50 16 54 48 20 72 12 14 22 24 40 46 38 56 26 32 28 30 52 42 77 34 58 70 44 68 76 J8 M.2 Key M TP20 5015 1 1 2 2 J10 009155002852006 GND +VUSB GND GND GND GND +VUSB M2_PET2_N M2_PET1_N M2_REFCLK_P M2_PER0_P M2_PER1_P M2_PER3_N M2_PET3_P M2_PET1_P M2_PET0_N M2_PERST# M2_PET3_N M2_PER0_P M2_PET2_N M2_PER2_N M2_PET1_P M2_REFCLK_N M2_PET3_P M2_PERST# M2_PER3_N M2_PER1_N M2_PET0_N M2_PER0_N M2_REFCLK_N M2_PER1_P M2_PER2_P M2_PET2_P M2_REFCLK_P M2_PET2_P +VUSB_M2 M2_PER3_P M2_PER2_P M2_PET1_N M2_PET0_P M2_PET0_P M2_PER1_N M2_PER3_P M2_PER0_N +VUSB_M2 M2_PET3_N M2_PER2_N GND M2_PERST# M2_REFCLK_P {M2_TX} M2_REFCLK_N {M2_RX} Custom Pinout Main Board Fan Connector NOTE: The TB/USB4 adaptor must be modified to give us VUSB instead of 3V3 M.2 Key M Connector Ground Lug
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Hardware/KiCad/Thunderscope_Rev5/PLL.kicad_sch
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1 2 3 4 5 6 1 2 3 4 5 6 D C B A D C B A Date: Size: A4 Id: / File: blob_981941d95bddcca6d99b5ca32dcaf86c0b9c4c28_45072547.kicad_sch Sheet: / KiCad E.D.A. eeschema 8.99 Aleksa Bjelogrlic Title: ThunderScope Rev: 5 EEVengers R49 1K C66 100nF C68 1uF R52 1K C56 1uF R43 49.9 C67 100nF C50 1uF C60 1uF C54 1uF C63 1uF R44 1K C53 1uF R46 10K R47 10K C61 1uF R53 1K C70 0 C59 1uF TP18 C51 1uF C49 1uF C65 0 C55 1uF J6 UFL VDD 4 EN 1 OUT 3 GND 2 Y1 10MHz C69 0 R45 10K R50 1K C64 0 TP17 FB3 120@100MHZ C58 1uF TP16 C48 1uF C62 1uF R48 1K J7 UFL C52 1uF C57 1uF R51 1K IF1/MISO 26 SDA/MOSI 25 IC3P 20 IC2N 19 IC2P 18 IC1N 16 AC0/GPIO0 23 OC2P/NC 6 AC2/GPIO2 28 VDDOA 7 VDDOB 1 VDDOE 43 VDDL 50 OC6N 48 VDDL 31 XB 13 OC3P 2 VDDH 11 OC3N 3 OC1P 8 VDDH 17 VDDL 14 VDDIO 30 VDDOC 54 VDDOF 36 OC6P 47 VSS-EPAD 57 OC5N/NC 52 VDDL 39 XA 12 OC4N 56 IF0/CSN 27 VDDL 10 VDDOD 46 OC9N 38 OC9P 37 VDDL 33 TEST/GPIO3 21 OC8P 41 OC8N 40 RSTN 29 IC1P 15 VDDL 4 VDDL 51 OC7N/NC 44 OC7P/NC 45 AC1/GPIO1 22 OC1N 9 OC4P 55 OC5P/NC 53 OC2N/NC 5 SCL/SCLK 24 VDDH 32 VDDH 42 VDDL 49 OC10N/NC 34 OC10P/NC 35 U7 ZL30260LDG1 GND GND GND GND GND GND GND GND GND GND GND +1V8APLL +1V8_ACQ GND GND GND +1V8APLL +1V8APLL GND GND GND GND GND GND +3V3_ACQ GND +3V3_ACQ GND PWR_FLAG +3V3_ACQ GND INTREF AC2 ADC_CLK_R_P ADC_CLK_R_N REFINOUT AC0 PLL_RSTn IF1 AC1 IF0 TEST REFINOUT PLL_SDA PLL_RSTn ADC_CLK_N REFINOUT ADC_CLK_P PLL_SCL 3V3: 0.115A Measured I2C Address: 1110100 134mA Measured 0.67W Expected Clock Generator 3.3 + 1.8V operation w/ one input one output: 0.62W Measured DONE: Replace with 50 ohm

16
Hardware/KiCad/Thunderscope_Rev5/Sheet_Template.kicad_wks
View File

@ -93,7 +93,7 @@
)
(tbtext "Date: ${ISSUE_DATE}"
(name "")
(pos 87 6.9)
(pos 87 7.104)
)
(line
(name "")
@ -102,7 +102,7 @@
)
(tbtext "${KICAD_VERSION}"
(name "")
(pos 109 4.1)
(pos 108.949 3.845)
(comment "Kicad version")
)
(line
@ -117,7 +117,7 @@
)
(tbtext "Size: ${PAPER}"
(name "")
(pos 109 6.9)
(pos 108.949 7.104)
(comment "Paper format name")
)
(tbtext "Id: ${#}/${##}"
@ -165,4 +165,14 @@
(start 26 8.5)
(end 26 2)
)
(line
(name "")
(start 54 21.554)
(end 54 18.524)
)
(tbtext "Drawn by: ${COMMENT1}"
(name "")
(pos 52.938 20)
(comment "Paper format name")
)
)

10
Hardware/KiCad/Thunderscope_Rev5/Thunderscope_Rev5.kicad_pro
View File

@ -653,13 +653,13 @@
"group_by": false,
"label": "SUPPLIER 1",
"name": "SUPPLIER 1",
"show": false
"show": true
},
{
"group_by": false,
"label": "SUPPLIER PART NUMBER 1",
"name": "SUPPLIER PART NUMBER 1",
"show": false
"show": true
},
{
"group_by": false,
@ -696,8 +696,8 @@
"group_symbols": true,
"include_excluded_from_bom": false,
"name": "",
"sort_asc": false,
"sort_field": "Reference"
"sort_asc": true,
"sort_field": "${EXCLUDE_FROM_BOARD}"
},
"connection_grid_size": 50.0,
"drawing": {
@ -727,7 +727,7 @@
"version": 1
},
"net_format_name": "",
"page_layout_descr_file": "kicad-embed://Sheet_Template.kicad_wks",
"page_layout_descr_file": "Sheet_Template.kicad_wks",
"plot_directory": "./",
"space_save_all_events": true,
"spice_current_sheet_as_root": false,

Hardware/KiCad/Thunderscope_Rev5/Thunderscope_Rev5.kicad_sch
View File

1 2 3 4 5 6 1 2 3 4 5 6 D C B A D C B A Date: Size: A4 Id: / File: blob_2d749f82a137e00a9f4d12dee106a894d08f64f5_1781868642.kicad_sch Sheet: / KiCad E.D.A. eeschema 8.99 Aleksa Bjelogrlic Title: ThunderScope Rev: 5 EEVengers TP2 5019 FID4 FID3 FID5 FID1 FID8 FID2 TP3 5019 FID7 FID6 GND GND PGA_SCLK CH1_N PGA_SCLK PGA_SCLK PGA_CSn_1 PGA_SCLK CH4_P DC_CPL_2 ATTEN_[4..1] PGA_SDIO CH3_N VCM CH3_P CH2_N PGA_CSn_4 TERM_3 CH1_P CH3_P ATTEN_1 DC_CPL_4 PGA_SDIO TERM_4 TRIM_[4..1] TRIM_2 VCM CH4_N VCM VCM DC_CPL_[4..1] TERM_1 CH1_N CH3_N CH2_P ATTEN_3 DC_CPL_1 TRIM_3 PGA_CSn_2 ATTEN_2 PGA_CSn_3 PGA_CSn_[4..1] ATTEN_4 TRIM_4 CH4_N CH1_P CH2_N PGA_SDIO PGA_SDIO CH4_P DC_CPL_3 TRIM_1 TERM_2 PGA_SCLK VCM CH2_P TERM_[4..1] PGA_SDIO CH2 File: FE_Channel.kicad_sch OUT_P VCM OUT_N TRIM ATTEN DC_CPL PGA_CSn PGA_SCLK PGA_SDIO TERM FPGA File: FPGA.kicad_sch OSC_OE ADC_CSn FE_EN ATTEN_[4..1] DC_CPL_[4..1] PGA_CSn_[4..1] PCIe_REFCLK_N PCIe_PERST# PCIe_REFCLK_P M2_REFCLK_N M2_PERST# M2_REFCLK_P TERM_[4..1] PROBE_COMP {ADC_LVDS} PGA_SDIO PGA_SCLK PLL_SCL PLL_SDA TRIM_SCL TRIM_SDA ADC_SDIO ADC_SCLK ACQ_EN SYNC_IN_P SYNC_IN_N SYNC_OUT_N SYNC_OUT_P FE_PG ACQ_PG {PCIe_TX} {PCIe_RX} {M2_TX} {M2_RX} {USRIO} SYNC_REn SYNC_DE {LED_RGB} M.2_Key_M File: M2_KEY_M.kicad_sch M2_REFCLK_N M2_PERST# M2_REFCLK_P {M2_TX} {M2_RX} User IO File: User_IO.kicad_sch PROBE_COMP REFINOUT SYNC_IN_P SYNC_IN_N SYNC_OUT_N SYNC_OUT_P SYNC_DE SYNC_REn {USRIO} {LED_RGB} Clock Generator File: PLL.kicad_sch ADC_CLK_P ADC_CLK_N PLL_RSTn PLL_SDA PLL_SCL REFINOUT PCIe_x4 File: CON_PCIe_X4.kicad_sch PCIe_REFCLK_P PCIe_REFCLK_N PCIe_PERST# {PCIe_RX} {PCIe_TX} ADC File: ADC.kicad_sch IN4_N IN4_P IN3_N IN3_P IN2_N IN2_P VCM IN1_N IN1_P ADC_CSn ADC_SDATA ADC_SCLK ADC_CLK_P ADC_CLK_N {ADC_LVDS} Front End Trim and Bias File: FE.kicad_sch TRIM_SCL TRIM_SDA TRIM_[4..1] CH1 File: FE_Channel.kicad_sch OUT_P VCM OUT_N TRIM ATTEN DC_CPL PGA_CSn PGA_SCLK PGA_SDIO TERM CH3 File: FE_Channel.kicad_sch OUT_P VCM OUT_N TRIM ATTEN DC_CPL PGA_CSn PGA_SCLK PGA_SDIO TERM ACQ and FE Voltage Regs File: ACQ_FE_VREG.kicad_sch FE_EN ACQ_EN FE_PG ACQ_PG CH4 File: FE_Channel.kicad_sch OUT_P VCM OUT_N TRIM ATTEN DC_CPL PGA_CSn PGA_SCLK PGA_SDIO TERM
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Hardware/KiCad/Thunderscope_Rev5/Thunderscope_Rev5.kicad_sym
View File

Name
Comment
Description

BIN
Hardware/KiCad/Thunderscope_Rev5/Thunderscope_Rev5.pdf
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Note: AllSpice cannot diff pdf files. Rendering head (latest) version below.
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Hardware/KiCad/Thunderscope_Rev5/User_IO.kicad_sch
View File

1 2 3 4 5 6 1 2 3 4 5 6 D C B A D C B A Date: Size: A4 Id: / File: blob_0c1927b87fec4f775fcf23eb5fbcf78685670b3a_207139093.kicad_sch Sheet: / KiCad E.D.A. eeschema 8.99 Aleksa Bjelogrlic Title: ThunderScope Rev: 5 EEVengers 2 2 1 1 J4 TSW-101-16-G-Q-RA C1 1uF J1 BNC R5 0 R62 10K R60 100 D2 TPD1E1B04 R3 0 R8 10K D3 TPD1E1B04 D5 TPD1E1B04 R7 100 R61 10K D R RI- 9 GND 7 DO+ 12 ~{RE} 8 DO- 11 NC 13 DE 1 RI+ 10 NC 6 NC 5 VCC 14 RO 4 NC 3 DI 2 U10 FIN1019MTCX R63 49.9 D4 TPD1E1B04 9 9 5 5 3 3 2 2 4 4 6 6 1 1 7 7 8 8 10 10 J3 1.27mm 6 Pin TH R65 1K C78 1uF R64 1K R4 0 10 10 1 1 30 30 17 17 34 34 4 4 8 8 16 16 25 25 9 9 32 32 28 28 20 20 12 12 14 14 7 7 21 21 13 13 15 15 19 19 11 11 5 5 22 22 3 3 2 2 6 6 18 18 23 23 24 24 26 26 27 27 29 29 31 31 33 33 35 35 36 36 SH1 SH1 SH2 SH2 J9 F300-1B7H1-11036-E100 C79 10uF J2 BNC VCC 5 NC 1 GND 3 IN 2 OUT 4 U1 SN74LVC1G17 R2 0 R G B D1 RGB R6 1K GND GND GND GND PWR_FLAG +3V3 +3V3_PGA GND GND GND GND GND GND GND GND GND GND GND GND GND GND USRIO_10_P USRIO_12_N USRIO_3_N USRIO_1_P USRIO_11_N USRIO_11_P USRIO_2_N USRIO_8_P USRIO_7_P USRIO_1_N REFINOUT1 USRIO_9_P REFINOUT2 SYNC1 SYNC1 LED_B USRIO_2_P USRIO_6_P USRIO_4_N REFINOUT SYNC2 USRIO_7_N USRIO_4_P USRIO_3_P USRIO_12_P USRIO_8_N SYNC USRIO_6_N USRIO_5_P REFINOUT1 USRIO_5_N LED_G SYNC2 USRIO_9_N USRIO_10_N LED_R REFINOUT2 {LED_RGB} SYNC_DE SYNC_OUT_N SYNC_IN_P SYNC_IN_N SYNC_OUT_P REFINOUT SYNC_REn {USRIO} PROBE_COMP Reference Clock and Sync TEST: LED resistor values on Mech Board DONE: Change Status LED to RGB DONE: 36 pin FFC for LVDS Status LED Probe Compensation User IO Flat Flex Connector DONE: FIN1019MTCX LVDS XCVR for Sync