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Author	SHA1	Message	Date
Andrew Lapadat	6033281321	Update README.md	2019-09-16 21:50:16 -04:00
Andrew Lapadat	5f5bfe1e05	Update README.md	2019-09-16 21:36:03 -04:00
Andrew Lapadat	aec73c1ca7	Update README.md	2019-09-16 21:25:29 -04:00
Andrew Lapadat	5a33cbd345	Merge pull request #9 from AleksaBjelogrlic/SW/andrew/yarn-conversion ... Switching from npm to yarn	2019-09-16 21:20:28 -04:00
andrewlapadat	8661cc6b14	fix	2019-09-16 21:16:32 -04:00
andrewlapadat	5e345c6f51	change readme	2019-09-16 21:13:14 -04:00
andrewlapadat	2e73426bf1	switch to yarn	2019-09-16 20:25:32 -04:00
Andrew Lapadat	9fc91b75bb	Merge pull request #8 from AleksaBjelogrlic/SW/andrew/electron-react ... Adding the React with Electron Desktop App	2019-09-15 23:52:11 -04:00
andrewlapadat	5bace02534	AHEM	2019-09-15 23:49:28 -04:00
andrewlapadat	a18de84dfa	ahem	2019-09-15 23:49:09 -04:00
andrewlapadat	6cba0447a5	UPDATE README	2019-09-15 23:48:04 -04:00
andrewlapadat	e01c4407f0	update README	2019-09-15 23:42:17 -04:00
andrewlapadat	dd70dd3fe0	more README	2019-09-15 23:41:26 -04:00
andrewlapadat	24bbb4309b	fix README	2019-09-15 23:40:13 -04:00
andrewlapadat	5e0a6926ba	add desktop app	2019-09-15 23:33:04 -04:00
Aleksa Bjelogrlic	78e3453e73	Merge pull request #7 from AleksaBjelogrlic/FW/Aleksa/FT6_Write_Test ... Changed 32 bit counter to 8 bit counter replicated across all 4 channels for ease of testing	2019-09-15 14:31:23 -04:00
Aleksa Bjelogrlic	c2dd65c3e5	Changed 32 bit counter to 8 bit counter replicated across all 4 channels for ease of testing	2019-09-15 14:24:59 -04:00
Aleksa Bjelogrlic	4458a47fb3	Merge pull request #6 from AleksaBjelogrlic/FW/Aleksa/BasicSerial ... Reduced FPGA resource requirements from 38 slices to 18. Now safely ignores any additional 4 byte packets until serial data is sent.	2019-09-15 04:20:04 -04:00
Aleksa Bjelogrlic	b1c0354f7b	Reduced FPGA resource requirements from 38 slices to 18. Now safely ignores any additional 4 byte packets until serial data is sent.	2019-09-15 04:16:32 -04:00
Aleksa Bjelogrlic	8d8fcb1721	Merge pull request #5 from AleksaBjelogrlic/FW/Aleksa/BasicSerial ... Changed clock and data output to 8MHz and refactored code to match verilog best practices.	2019-09-14 22:37:55 -04:00
Aleksa Bjelogrlic	6ff4697ca3	Changed clock and data output to 8MHz and refactored code to match verilog best practices.	2019-09-14 22:34:30 -04:00
Aleksa Bjelogrlic	bb833ed3d6	Merge pull request #4 from AleksaBjelogrlic/FW/Aleksa/BasicSerial ... Basic Serial Output	2019-08-24 13:13:13 -04:00
Aleksa Bjelogrlic	ddfef529ea	Basic Serial Output	2019-08-24 13:11:38 -04:00
Daniel Vasile	e1fa3a8bba	New GUI/Processing/Data Transefer Thread Files Made	2019-08-12 11:43:30 -04:00
Daniel Vasile	373424313b	Basic Functional USB 3.0 Reading Implemented	2019-07-30 20:05:51 -04:00
Daniel Vasile	817b5c6b02	Merge pull request #2 from AleksaBjelogrlic/Daniel_Branch ... Got FTDI Example working in Xcode	2019-07-26 18:33:34 -04:00
Daniel Vasile	cccfd8b8d2	Got FTDI Example working in Xcode	2019-07-26 18:28:09 -04:00
Daniel Vasile	7bf8795046	Added Software Folder and Project	2019-07-26 12:40:11 -04:00
Aleksa Bjelogrlic	41da2ff2a1	Added FT6_Write_Test	2019-07-24 22:00:17 -04:00
Aleksa Bjelogrlic	931543de07	Added FT2_Read_Test	2019-07-19 22:27:10 -04:00
Aleksa Bjelogrlic	fc639f85e7	Merge remote-tracking branch 'origin/master'	2019-07-15 11:58:14 -04:00
Aleksa Bjelogrlic	d6c8452b8a	Added older bscan bit file	2019-07-15 11:58:07 -04:00
Aleksa Bjelogrlic	a982063761	Changed file name	2019-07-15 11:57:22 -04:00
Aleksa Bjelogrlic	b957511273	Removed user directory on readme	2019-07-15 11:54:20 -04:00
Aleksa Bjelogrlic	6a7cd1ae3b	Added FPGA programming instructions	2019-07-15 11:01:44 -04:00
Aleksa Bjelogrlic	7904c32fcc	Added OpenOCD Bit Files	2019-07-15 10:48:36 -04:00
Aleksa Bjelogrlic	e1282edaf3	Merge remote-tracking branch 'origin/master'	2019-07-15 09:42:11 -04:00
Aleksa Bjelogrlic	865e9e7029	Adding bit files for FPGA tools setup	2019-07-15 09:42:02 -04:00
andrewlapadat	0b9e15d9a3	remvoing submodule	2019-07-09 22:11:05 -04:00
Aleksa Bjelogrlic	a694630ddc	Finished Hardware Section ... Firmware Section WIP	2019-07-09 17:18:09 -04:00
Aleksa Bjelogrlic	972aac86be	Merge remote-tracking branch 'origin/master'	2019-07-09 16:53:27 -04:00
Aleksa Bjelogrlic	0ba51d255e	"no spaces plz" - Andrew	2019-07-09 16:53:08 -04:00
Aleksa Bjelogrlic	ba304b27f8	Readme WIP ... Gotta fix the spaces on the Digital Interface folder	2019-07-09 16:51:28 -04:00
Aleksa Bjelogrlic	b2512a3d7b	Readme WIP ... Good documentation is hard	2019-07-08 00:55:46 -04:00
Aleksa Bjelogrlic	545e9dab61	Finished DI_Breakout	2019-07-05 22:36:59 -04:00
Aleksa Bjelogrlic	d73d2569a7	Merge remote-tracking branch 'origin/master'	2019-07-01 00:22:07 -04:00
Aleksa Bjelogrlic	8686561f03	Digital Interface Breakout WIP ... Also added programming issue warning (M1 pin being used twice) to digital interface schematic.	2019-07-01 00:20:52 -04:00
Aleksa Bjelogrlic	1b81e8f504	Readme WIP	2019-06-30 23:36:06 -04:00
Aleksa Bjelogrlic	c8e9d0115e	Merge remote-tracking branch 'origin/master'	2019-06-30 23:05:53 -04:00
Aleksa Bjelogrlic	3df8baa568	Added Block Diagram for Readme	2019-06-30 23:02:54 -04:00