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Mono Color

• 5e345c6f51
  change readme andrewlapadat 2019-09-16 21:13:14 -0400
• 2e73426bf1
  switch to yarn andrewlapadat 2019-09-16 20:25:32 -0400
• 9fc91b75bb
  Merge pull request #8 from AleksaBjelogrlic/SW/andrew/electron-react Andrew Lapadat 2019-09-15 23:52:11 -0400
• 5bace02534
  AHEM andrewlapadat 2019-09-15 23:49:28 -0400
• a18de84dfa
  ahem andrewlapadat 2019-09-15 23:49:09 -0400
• 6cba0447a5
  UPDATE README andrewlapadat 2019-09-15 23:48:04 -0400
• e01c4407f0
  update README andrewlapadat 2019-09-15 23:42:17 -0400
• dd70dd3fe0
  more README andrewlapadat 2019-09-15 23:41:26 -0400
• 24bbb4309b
  fix README andrewlapadat 2019-09-15 23:40:13 -0400
• 5e0a6926ba
  add desktop app andrewlapadat 2019-09-15 23:33:04 -0400
• 78e3453e73
  Merge pull request #7 from AleksaBjelogrlic/FW/Aleksa/FT6_Write_Test Aleksa Bjelogrlic 2019-09-15 14:31:23 -0400
• c2dd65c3e5 Changed 32 bit counter to 8 bit counter replicated across all 4 channels for ease of testing Aleksa Bjelogrlic 2019-09-15 14:24:59 -0400
• 4458a47fb3
  Merge pull request #6 from AleksaBjelogrlic/FW/Aleksa/BasicSerial Aleksa Bjelogrlic 2019-09-15 04:20:04 -0400
• b1c0354f7b Reduced FPGA resource requirements from 38 slices to 18. Now safely ignores any additional 4 byte packets until serial data is sent. Aleksa Bjelogrlic 2019-09-15 04:16:32 -0400
• 8d8fcb1721
  Merge pull request #5 from AleksaBjelogrlic/FW/Aleksa/BasicSerial Aleksa Bjelogrlic 2019-09-14 22:37:55 -0400
• 6ff4697ca3 Changed clock and data output to 8MHz and refactored code to match verilog best practices. Aleksa Bjelogrlic 2019-09-14 22:34:30 -0400
• bb833ed3d6
  Merge pull request #4 from AleksaBjelogrlic/FW/Aleksa/BasicSerial Aleksa Bjelogrlic 2019-08-24 13:13:13 -0400
• ddfef529ea Basic Serial Output Aleksa Bjelogrlic 2019-08-24 13:11:38 -0400
• e1fa3a8bba New GUI/Processing/Data Transefer Thread Files Made Daniel Vasile 2019-08-12 11:43:30 -0400
• 373424313b Basic Functional USB 3.0 Reading Implemented Daniel Vasile 2019-07-30 20:05:51 -0400
• 817b5c6b02
  Merge pull request #2 from AleksaBjelogrlic/Daniel_Branch Daniel Vasile 2019-07-26 18:33:34 -0400
• cccfd8b8d2 Got FTDI Example working in Xcode Daniel Vasile 2019-07-26 18:28:09 -0400
• 7bf8795046 Added Software Folder and Project Daniel Vasile 2019-07-26 12:40:11 -0400
• 41da2ff2a1 Added FT6_Write_Test Aleksa Bjelogrlic 2019-07-24 22:00:17 -0400
• 931543de07 Added FT2_Read_Test Aleksa Bjelogrlic 2019-07-19 22:27:10 -0400
• fc639f85e7 Merge remote-tracking branch 'origin/master' Aleksa Bjelogrlic 2019-07-15 11:58:14 -0400
• d6c8452b8a Added older bscan bit file Aleksa Bjelogrlic 2019-07-15 11:58:07 -0400
• a982063761
  Changed file name Aleksa Bjelogrlic 2019-07-15 11:57:22 -0400
• b957511273
  Removed user directory on readme Aleksa Bjelogrlic 2019-07-15 11:54:20 -0400
• 6a7cd1ae3b
  Added FPGA programming instructions Aleksa Bjelogrlic 2019-07-15 11:01:44 -0400
• 7904c32fcc Added OpenOCD Bit Files Aleksa Bjelogrlic 2019-07-15 10:48:36 -0400
• e1282edaf3 Merge remote-tracking branch 'origin/master' Aleksa Bjelogrlic 2019-07-15 09:42:11 -0400
• 865e9e7029 Adding bit files for FPGA tools setup Aleksa Bjelogrlic 2019-07-15 09:42:02 -0400
• 0b9e15d9a3
  remvoing submodule andrewlapadat 2019-07-09 22:11:05 -0400
• a694630ddc
  Finished Hardware Section Aleksa Bjelogrlic 2019-07-09 17:18:09 -0400
• 972aac86be Merge remote-tracking branch 'origin/master' Aleksa Bjelogrlic 2019-07-09 16:53:27 -0400
• 0ba51d255e "no spaces plz" - Andrew Aleksa Bjelogrlic 2019-07-09 16:53:08 -0400
• ba304b27f8
  Readme WIP Aleksa Bjelogrlic 2019-07-09 16:51:28 -0400
• b2512a3d7b
  Readme WIP Aleksa Bjelogrlic 2019-07-08 00:55:46 -0400
• 545e9dab61 Finished DI_Breakout Aleksa Bjelogrlic 2019-07-05 22:36:59 -0400
• d73d2569a7 Merge remote-tracking branch 'origin/master' Aleksa Bjelogrlic 2019-07-01 00:22:07 -0400
• 8686561f03 Digital Interface Breakout WIP Aleksa Bjelogrlic 2019-07-01 00:19:41 -0400
• 1b81e8f504
  Readme WIP Aleksa Bjelogrlic 2019-06-30 23:36:06 -0400
• c8e9d0115e Merge remote-tracking branch 'origin/master' Aleksa Bjelogrlic 2019-06-30 23:05:53 -0400
• 3df8baa568 Added Block Diagram for Readme Aleksa Bjelogrlic 2019-06-30 23:02:54 -0400
• a93178cf28
  update to be accurate andrewlapadat 2019-06-28 12:39:39 -0400
• 26a0686a92
  no spaces plz andrewlapadat 2019-06-28 12:28:13 -0400
• 09d85dbd04 Created DSO_Firmware Daniel Vasile 2019-06-28 12:26:50 -0400
• 61d73bd454 add useful python stuff andrewlapadat 2019-06-28 12:13:09 -0400
• c717554f12 Revert "add submodules" andrewlapadat 2019-06-28 11:57:30 -0400
• a47b0198c5 Revert "add folder" andrewlapadat 2019-06-28 11:57:27 -0400
• 8dd6586a49 Revert "organizing" andrewlapadat 2019-06-28 11:57:21 -0400
• 0ec7a3d8b2 Revert "Merge branch 'master' of https://github.com/AleksaBjelogrlic/EEVengers" andrewlapadat 2019-06-28 11:57:14 -0400
• 671e4f575e Merge branch 'master' of https://github.com/AleksaBjelogrlic/EEVengers andrewlapadat 2019-06-28 11:49:11 -0400
• fb16a3aaa7 organizing andrewlapadat 2019-06-28 11:49:03 -0400
• 29245d4090
  Delete .gitmodules Andrew Lapadat 2019-06-28 11:48:38 -0400
• f46face048 add folder andrewlapadat 2019-06-28 11:47:02 -0400
• 664068ad12 add submodules andrewlapadat 2019-06-28 11:44:43 -0400
• fe0c8d22f8
  creating TODO andrewlapadat 2019-06-28 11:21:28 -0400
• bd43d20635
  Delete TODO.md Andrew Lapadat 2019-06-28 11:19:52 -0400
• 1cfcc7a141
  Merge pull request #1 from AleksaBjelogrlic/andrewlapadat/signing Andrew Lapadat 2019-06-28 11:17:29 -0400
• b3adca0ba0
  signing try andrewlapadat 2019-06-28 11:16:19 -0400
• 55c9ce4fbb
  add TODO Andrew Lapadat 2019-06-28 11:04:54 -0400
• 9a4aabf1df Google Drive to Github Migration for DSO Hardware and Testing Aleksa Bjelogrlic 2019-06-03 20:12:56 -0400
• 40a1bcb6d1
  Initial commit AleksaBjelogrlic 2019-06-03 11:09:40 -0400