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18 lines
4.3 KiB
Plaintext
18 lines
4.3 KiB
Plaintext
Record=TopLevelDocument|FileName=Main.SchDoc|SheetNumber=1
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Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=ADC|SchDesignator=ADC|FileName=ADC.SchDoc|SheetNumber=5|SymbolType=Normal|RawFileName=ADC.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=CH1|SchDesignator=CH1|FileName=FE_Channel.SchDoc|SheetNumber=2|SymbolType=Normal|RawFileName=FE_Channel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=CH2|SchDesignator=CH2|FileName=FE_Channel.SchDoc|SheetNumber=2|SymbolType=Normal|RawFileName=FE_Channel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=CH3|SchDesignator=CH3|FileName=FE_Channel.SchDoc|SheetNumber=2|SymbolType=Normal|RawFileName=FE_Channel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=CH4|SchDesignator=CH4|FileName=FE_Channel.SchDoc|SheetNumber=2|SymbolType=Normal|RawFileName=FE_Channel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=Clock Generator|SchDesignator=Clock Generator|FileName=PLL.SchDoc|SheetNumber=4|SymbolType=Normal|RawFileName=PLL.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=FPGA|SchDesignator=FPGA|FileName=FPGA.SchDoc|SheetNumber=7|SymbolType=Normal|RawFileName=FPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=Front End Trim and Bias|SchDesignator=Front End Trim and Bias|FileName=FE.SchDoc|SheetNumber=3|SymbolType=Normal|RawFileName=FE.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=M.2_Key_M|SchDesignator=M.2_Key_M|FileName=M2_KEY_M.SchDoc|SheetNumber=14|SymbolType=Normal|RawFileName=M2_KEY_M.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=PCIe_X4|SchDesignator=PCIe_X4|FileName=CON_PCIe_X4.SchDoc|SheetNumber=13|SymbolType=Normal|RawFileName=CON_PCIe_X4.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=POWER|SchDesignator=POWER|FileName=PWR.SchDoc|SheetNumber=6|SymbolType=Normal|RawFileName=PWR.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FPGA Configuration|SchDesignator=FPGA Configuration|FileName=FPGA_CFG.SchDoc|SheetNumber=9|SymbolType=Normal|RawFileName=FPGA_CFG.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FPGA IO Banks|SchDesignator=FPGA IO Banks|FileName=FPGA_Bank_IO.SchDoc|SheetNumber=8|SymbolType=Normal|RawFileName=FPGA_Bank_IO.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FPGA Power|SchDesignator=FPGA Power|FileName=FPGA_PWR.SchDoc|SheetNumber=11|SymbolType=Normal|RawFileName=FPGA_PWR.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FPGA Transceivers|SchDesignator=FPGA Transceivers|FileName=FPGA_MGT.SchDoc|SheetNumber=10|SymbolType=Normal|RawFileName=FPGA_MGT.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Voltage Regulation|SchDesignator=Voltage Regulation|FileName=FPGA_REG.SchDoc|SheetNumber=12|SymbolType=Normal|RawFileName=FPGA_REG.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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