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mirror of https://github.com/issus/altium-library.git synced 2025-04-02 03:36:35 +00:00

Create symbols/MCU - STM32/SCH - MCU - STM32 - ST MICROELECTRONICS STM32MP157AAAX LFBGA448.SchLib

This commit is contained in:
Mark 2023-06-28 04:07:43 +01:00
parent addb05c516
commit 7aae343ea5

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ST MICROELECTRONICS STM32MP157AAAX LFBGA448
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VSS_USBHS Y13 VSS_USBHS Y14 VSS_USBHS Y15 VSS_USBHS AA13 VSS_USBHS AA16 VSS_PLL2 D19 VSS_PLL M5 VSS_DSI C14 VSS_DSI C15 VSS_DSI C16 VSS_DSI C17 VSS_DSI C18 VSS_ANA P5 VSS A1 VSS A19 VSS A22 VSS B2 VSS B19 VSS C3 VSS C8 VSS C11 VSS C19 VSS C20 VSS D4 VSS E5 VSS E19 VSS F6 VSS F7 VSS F8 VSS F16 VSS F20 VSS G4 VSS G6 VSS G8 VSS G10 VSS G12 VSS G14 VSS G17 VSS H7 VSS J9 VSS J11 VSS J13 VSS J17 VSS J20 VSS K3 VSS K7 VSS K10 VSS K12 VSS K14 VSS L9 VSS L11 VSS L13 VSS L17 VSS L19 VSS L20 VSS M7 VSS M10 VSS M12 VSS M14 VSS N9 VSS N11 VSS N13 VSS N17 VSS P3 VSS P7 VSS P10 VSS P12 VSS P14 VSS P20 VSS R8 VSS R17 VSS T7 VSS T9 VSS T11 VSS T19 VSS U7 VSS U13 VSS U15 VSS U17 VSS U20 VSS V5 VSS V16 VSS V18 VSS V19 VSS W17 VSS W19 VSS Y3 VSS Y7 VSS Y10 VSS Y18 VSS Y20 VSS AA4 VSS AA18 VSS AB1 VSS AB18 VSS AB22 VSSA R6 VSSA T6 VSSA U6 VDDQ_DDR E18 VDDQ_DDR F17 VDDQ_DDR G16 VDDQ_DDR H17 VDDQ_DDR J16 VDDQ_DDR K17 VDDQ_DDR L16 VDDQ_DDR M17 VDDQ_DDR N16 VDDQ_DDR P17 VDDQ_DDR R16 VDDQ_DDR T17 VDDQ_DDR U16 VDDQ_DDR V17 VDDQ_DDR W18 VDDQ_DDR Y19 VDDCORE H9 VDDCORE H11 VDDCORE H13 VDDCORE H15 VDDCORE J8 VDDCORE J10 VDDCORE J12 VDDCORE J14 VDDCORE K9 VDDCORE K11 VDDCORE K13 VDDCORE K15 VDDCORE L8 VDDCORE L10 VDDCORE L12 VDDCORE L14 VDDCORE M11 VDDCORE M13 VDDCORE M15 VDDCORE N12 VDDCORE N14 VDDCORE P13 VDDCORE P15 VDDCORE R14 VDDCORE T15 VDD3V3_USBHS AB13 VDD3V3_USBFS AB16 VDD1V2_DSI_REG B18 VDD1V2_DSI_PHY A18 VDD_PLL2 D18 VDD_PLL M6 VDD_DSI A14 VDD_ANA N5 VDD M9 VDD N8 VDD N10 VDD P9 VDD P11 VDD R10 VDD R12 VDD T13 VDD U9 VDD U12 VDD U14 VDDA1V8_REG AB12 VDDA1V8_DSI B14 VDDA1V1_REG AB17 VDDA R5 VBAT M4 VREF+ P6 VREF- N6 BOOT2 P4 BOOT1 N4 BOOT0 N3 PDR_ON V2 NRST R2 VSS_USBHS Y13 VSS_USBHS Y14 VSS_USBHS Y15 VSS_USBHS AA13 VSS_USBHS AA16 VSS_PLL2 D19 VSS_PLL M5 VSS_DSI C14 VSS_DSI C15 VSS_DSI C16 VSS_DSI C17 VSS_DSI C18 VSS_ANA P5 VSS A1 VSS A19 VSS A22 VSS B2 VSS B19 VSS C3 VSS C8 VSS C11 VSS C19 VSS C20 VSS D4 VSS E5 VSS E19 VSS F6 VSS F7 VSS F8 VSS F16 VSS F20 VSS G4 VSS G6 VSS G8 VSS G10 VSS G12 VSS G14 VSS G17 VSS H7 VSS J9 VSS J11 VSS J13 VSS J17 VSS J20 VSS K3 VSS K7 VSS K10 VSS K12 VSS K14 VSS L9 VSS L11 VSS L13 VSS L17 VSS L19 VSS L20 VSS M7 VSS M10 VSS M12 VSS M14 VSS N9 VSS N11 VSS N13 VSS N17 VSS P3 VSS P7 VSS P10 VSS P12 VSS P14 VSS P20 VSS R8 VSS R17 VSS T7 VSS T9 VSS T11 VSS T19 VSS U7 VSS U13 VSS U15 VSS U17 VSS U20 VSS V5 VSS V16 VSS V18 VSS V19 VSS W17 VSS W19 VSS Y3 VSS Y7 VSS Y10 VSS Y18 VSS Y20 VSS AA4 VSS AA18 VSS AB1 VSS AB18 VSS AB22 VSSA R6 VSSA T6 VSSA U6 VDDQ_DDR E18 VDDQ_DDR F17 VDDQ_DDR G16 VDDQ_DDR H17 VDDQ_DDR J16 VDDQ_DDR K17 VDDQ_DDR L16 VDDQ_DDR M17 VDDQ_DDR N16 VDDQ_DDR P17 VDDQ_DDR R16 VDDQ_DDR T17 VDDQ_DDR U16 VDDQ_DDR V17 VDDQ_DDR W18 VDDQ_DDR Y19 VDDCORE H9 VDDCORE H11 VDDCORE H13 VDDCORE H15 VDDCORE J8 VDDCORE J10 VDDCORE J12 VDDCORE J14 VDDCORE K9 VDDCORE K11 VDDCORE K13 VDDCORE K15 VDDCORE L8 VDDCORE L10 VDDCORE L12 VDDCORE L14 VDDCORE M11 VDDCORE M13 VDDCORE M15 VDDCORE N12 VDDCORE N14 VDDCORE P13 VDDCORE P15 VDDCORE R14 VDDCORE T15 VDD3V3_USBHS AB13 VDD3V3_USBFS AB16 VDD1V2_DSI_REG B18 VDD1V2_DSI_PHY A18 VDD_PLL2 D18 VDD_PLL M6 VDD_DSI A14 VDD_ANA N5 VDD M9 VDD N8 VDD N10 VDD P9 VDD P11 VDD R10 VDD R12 VDD T13 VDD U9 VDD U12 VDD U14 VDDA1V8_REG AB12 VDDA1V8_DSI B14 VDDA1V1_REG AB17 VDDA R5 VBAT M4 VREF+ P6 VREF- N6 BOOT2 P4 BOOT1 N4 BOOT0 N3 PDR_ON V2 NRST R2
DSIHOST_D1P/DSIHOST_D1P B17 DSIHOST_D1N/DSIHOST_D1N A17 DSIHOST_D0P/DSIHOST_D0P B15 DSIHOST_D0N/DSIHOST_D0N A15 DSIHOST_CKP/DSIHOST_CKP B16 DSIHOST_CKN/DSIHOST_CKN A16 ANA0/ADC1_INN1/ADC1_INP0/ADC2_INN1/ADC2_INP0 R4 ANA1/ADC1_INP1/ADC2_INP1 T5 BYPASS_REG1V8 AA12 DDR_A0/DDR_A0 K19 DDR_A1/DDR_A1 M18 DDR_A10/DDR_A10 N18 DDR_A11/DDR_A11 P19 DDR_A12/DDR_A12 N19 DDR_A13/DDR_A13 G18 DDR_A14/DDR_A14 P18 DDR_A15/DDR_A15 M19 DDR_A2/DDR_A2 J18 DDR_A3/DDR_A3 J19 DDR_A4/DDR_A4 T18 DDR_A5/DDR_A5 H19 DDR_A6/DDR_A6 U19 DDR_A7/DDR_A7 F18 DDR_A8/DDR_A8 U18 DDR_A9/DDR_A9 H18 DDR_ATO/DDR_ATO AA19 D\D\R\_\B\A\0\/D\D\R\_\B\A\0\ K20 D\D\R\_\B\A\1\/D\D\R\_\B\A\1\ R18 D\D\R\_\B\A\2\/D\D\R\_\B\A\2\ K18 DDR_CASN/DDR_CASN M22 DDR_CKE/DDR_CKE R19 DDR_CLKN/DDR_CLKN N21 DDR_CLKP/DDR_CLKP N20 DDR_CSN/DDR_CSN L18 DDR_DQ0/DDR_DQ0 E21 DDR_DQ1/DDR_DQ1 F21 DDR_DQ10/DDR_DQ10 P21 DDR_DQ11/DDR_DQ11 T20 DDR_DQ12/DDR_DQ12 V20 DDR_DQ13/DDR_DQ13 R20 DDR_DQ14/DDR_DQ14 U21 DDR_DQ15/DDR_DQ15 V21 DDR_DQ16/DDR_DQ16 B21 DDR_DQ17/DDR_DQ17 D21 DDR_DQ18/DDR_DQ18 D22 DDR_DQ19/DDR_DQ19 B20 DDR_DQ2/DDR_DQ2 H21 DDR_DQ20/DDR_DQ20 A20 DDR_DQ21/DDR_DQ21 E22 DDR_DQ22/DDR_DQ22 D20 DDR_DQ23/DDR_DQ23 A21 DDR_DQ24/DDR_DQ24 V22 DDR_DQ25/DDR_DQ25 W20 DDR_DQ26/DDR_DQ26 AB21 DDR_DQ27/DDR_DQ27 AB20 DDR_DQ28/DDR_DQ28 AA21 DDR_DQ29/DDR_DQ29 AA20 DDR_DQ3/DDR_DQ3 E20 DDR_DQ30/DDR_DQ30 W22 DDR_DQ31/DDR_DQ31 W21 DDR_DQ4/DDR_DQ4 J21 DDR_DQ5/DDR_DQ5 H20 DDR_DQ6/DDR_DQ6 H22 DDR_DQ7/DDR_DQ7 G19 DDR_DQ8/DDR_DQ8 N22 DDR_DQ9/DDR_DQ9 R21 DDR_DQM0/DDR_DQM0 G20 DDR_DQM1/DDR_DQM1 T21 DDR_DQM2/DDR_DQM2 C22 DDR_DQM3/DDR_DQM3 AA22 DDR_DQS0N/DDR_DQS0N G21 DDR_DQS0P/DDR_DQS0P G22 DDR_DQS1N/DDR_DQS1N R22 DDR_DQS1P/DDR_DQS1P T22 DDR_DQS2N/DDR_DQS2N B22 DDR_DQS2P/DDR_DQS2P C21 DDR_DQS3N/DDR_DQS3N Y22 DDR_DQS3P/DDR_DQS3P Y21 DDR_DTO0/DDR_DTO0 L22 DDR_DTO1/DDR_DTO1 K21 DDR_ODT/DDR_ODT L21 DDR_RASN/DDR_RASN M20 DDR_RESETN/DDR_RESETN F19 DDR_VREF/DDR_VREF AB19 DDR_WEN/DDR_WEN M21 DDR_ZQ/DDR_ZQ K22 JTCK-SWCLK/DEBUG_JTCK-SWCLK D17 JTDI/DEBUG_JTDI D16 JTDO-TRACESWO/DEBUG_JTDO-SWO E16 JTMS-SWDIO/DEBUG_JTMS-SWDIO E17 NJTRST/DEBUG_JTRST E15 NRST_CORE R1 OTG_VBUS/USB_OTG_HS_VBUS V15 PDR_ON_CORE U2 PWR_LP U1 PWR_ON V1 USB_DM1/USBH_HS1_DM AB15 USB_DM2/USBH_HS2_DM/USB_OTG_HS_DM AA14 USB_DP1/USBH_HS1_DP AA15 USB_DP2/USBH_HS2_DP/USB_OTG_HS_DP AB14 USB_RREF AA17 DSIHOST_D1P/DSIHOST_D1P B17 DSIHOST_D1N/DSIHOST_D1N A17 DSIHOST_D0P/DSIHOST_D0P B15 DSIHOST_D0N/DSIHOST_D0N A15 DSIHOST_CKP/DSIHOST_CKP B16 DSIHOST_CKN/DSIHOST_CKN A16 ANA0/ADC1_INN1/ADC1_INP0/ADC2_INN1/ADC2_INP0 R4 ANA1/ADC1_INP1/ADC2_INP1 T5 BYPASS_REG1V8 AA12 DDR_A0/DDR_A0 K19 DDR_A1/DDR_A1 M18 DDR_A10/DDR_A10 N18 DDR_A11/DDR_A11 P19 DDR_A12/DDR_A12 N19 DDR_A13/DDR_A13 G18 DDR_A14/DDR_A14 P18 DDR_A15/DDR_A15 M19 DDR_A2/DDR_A2 J18 DDR_A3/DDR_A3 J19 DDR_A4/DDR_A4 T18 DDR_A5/DDR_A5 H19 DDR_A6/DDR_A6 U19 DDR_A7/DDR_A7 F18 DDR_A8/DDR_A8 U18 DDR_A9/DDR_A9 H18 DDR_ATO/DDR_ATO AA19 D\D\R\_\B\A\0\/D\D\R\_\B\A\0\ K20 D\D\R\_\B\A\1\/D\D\R\_\B\A\1\ R18 D\D\R\_\B\A\2\/D\D\R\_\B\A\2\ K18 DDR_CASN/DDR_CASN M22 DDR_CKE/DDR_CKE R19 DDR_CLKN/DDR_CLKN N21 DDR_CLKP/DDR_CLKP N20 DDR_CSN/DDR_CSN L18 DDR_DQ0/DDR_DQ0 E21 DDR_DQ1/DDR_DQ1 F21 DDR_DQ10/DDR_DQ10 P21 DDR_DQ11/DDR_DQ11 T20 DDR_DQ12/DDR_DQ12 V20 DDR_DQ13/DDR_DQ13 R20 DDR_DQ14/DDR_DQ14 U21 DDR_DQ15/DDR_DQ15 V21 DDR_DQ16/DDR_DQ16 B21 DDR_DQ17/DDR_DQ17 D21 DDR_DQ18/DDR_DQ18 D22 DDR_DQ19/DDR_DQ19 B20 DDR_DQ2/DDR_DQ2 H21 DDR_DQ20/DDR_DQ20 A20 DDR_DQ21/DDR_DQ21 E22 DDR_DQ22/DDR_DQ22 D20 DDR_DQ23/DDR_DQ23 A21 DDR_DQ24/DDR_DQ24 V22 DDR_DQ25/DDR_DQ25 W20 DDR_DQ26/DDR_DQ26 AB21 DDR_DQ27/DDR_DQ27 AB20 DDR_DQ28/DDR_DQ28 AA21 DDR_DQ29/DDR_DQ29 AA20 DDR_DQ3/DDR_DQ3 E20 DDR_DQ30/DDR_DQ30 W22 DDR_DQ31/DDR_DQ31 W21 DDR_DQ4/DDR_DQ4 J21 DDR_DQ5/DDR_DQ5 H20 DDR_DQ6/DDR_DQ6 H22 DDR_DQ7/DDR_DQ7 G19 DDR_DQ8/DDR_DQ8 N22 DDR_DQ9/DDR_DQ9 R21 DDR_DQM0/DDR_DQM0 G20 DDR_DQM1/DDR_DQM1 T21 DDR_DQM2/DDR_DQM2 C22 DDR_DQM3/DDR_DQM3 AA22 DDR_DQS0N/DDR_DQS0N G21 DDR_DQS0P/DDR_DQS0P G22 DDR_DQS1N/DDR_DQS1N R22 DDR_DQS1P/DDR_DQS1P T22 DDR_DQS2N/DDR_DQS2N B22 DDR_DQS2P/DDR_DQS2P C21 DDR_DQS3N/DDR_DQS3N Y22 DDR_DQS3P/DDR_DQS3P Y21 DDR_DTO0/DDR_DTO0 L22 DDR_DTO1/DDR_DTO1 K21 DDR_ODT/DDR_ODT L21 DDR_RASN/DDR_RASN M20 DDR_RESETN/DDR_RESETN F19 DDR_VREF/DDR_VREF AB19 DDR_WEN/DDR_WEN M21 DDR_ZQ/DDR_ZQ K22 JTCK-SWCLK/DEBUG_JTCK-SWCLK D17 JTDI/DEBUG_JTDI D16 JTDO-TRACESWO/DEBUG_JTDO-SWO E16 JTMS-SWDIO/DEBUG_JTMS-SWDIO E17 NJTRST/DEBUG_JTRST E15 NRST_CORE R1 OTG_VBUS/USB_OTG_HS_VBUS V15 PDR_ON_CORE U2 PWR_LP U1 PWR_ON V1 USB_DM1/USBH_HS1_DM AB15 USB_DM2/USBH_HS2_DM/USB_OTG_HS_DM AA14 USB_DP1/USBH_HS1_DP AA15 USB_DP2/USBH_HS2_DP/USB_OTG_HS_DP AB14 USB_RREF AA17
PI10/ETH1_RX_ER/HDP_HDP0/LTDC_HSYNC/USART3_CTS/U\S\A\R\T\3\_\N\S\S\ W1 PI11/ADC1_EXTI11/ADC2_EXTI11/I2S_CKIN/LTDC_G6/PWR_WKUP5/RCC_MCO_1 T3 PI12/DEBUG_TRACED0/HDP_HDP0/LTDC_HSYNC H2 PI13/DEBUG_TRACED1/HDP_HDP1/LTDC_VSYNC H1 PI14/DEBUG_TRACECLK/LTDC_CLK D2 PI15/ADC1_EXTI15/ADC2_EXTI15/LTDC_G2/LTDC_R0 F3 PA0/ADC1/ETH1/PWR/SAI2/SDMMC2/TIM15/TIM2/TIM5/TIM8/UART4/USART2 AA3 PA1/ADC1/ETH1/LPTIM3/LTDC/QUADSPI/SAI2/TIM15/TIM2/TIM5/UART4/USART2 V4 PA2/ADC1/ETH1/LPTIM4/LTDC/PWR/SAI2/SDMMC2/TIM15/TIM2/TIM5/USART2 AB2 PA3/ADC1_INP15/ETH1_COL/LPTIM5_OUT/L\T\D\C\_\B\2\/L\T\D\C\_\B\5\/PWR_PVD_IN/TIM15_CH2/TIM2_CH4/TIM5_CH4/USART2_RX T4 PA4/ADC1/ADC2/DAC1/DCMI/HDP/I2S1/I2S3/LTDC/SAI4/SPI1/SPI3/SPI6/TIM5/USART2 V6 PA5/ADC1/ADC2/DAC1/I2S1/LTDC/SAI4/SPI1/SPI6/TIM2/TIM8 U5 PA6/ADC1/ADC2/DCMI/I2S1/LTDC/SAI4/SPI1/SPI6/TIM13/TIM1/TIM3/TIM8 W9 PA7/ADC1/ADC2/ETH1/I2S1/QUADSPI/SAI4/SPI1/SPI6/TIM14/TIM1/TIM3/TIM8 Y9 PA8/I2C3/I2S3/LTDC/RCC/SAI4/SDMMC2/SPI3/TIM1/TIM8/UART7/USART1/USB B13 PA9/DAC1_EXTI9/DCMI_D0/I2C3_SMBA/I2S2_CK/LTDC_R5/SDMMC2_CDIR/SDMMC2_D5/SPI2_SCK/TIM1_CH2/USART1_TX A11 PA10/DCMI_D1/I2S3_WS/L\T\D\C\_\B\1\/S\A\I\4\_\F\S\_\B\/S\P\I\3\_\N\S\S\/TIM1_CH3/USART1_RX/USB_OTG_HS_ID Y17 PA11/ADC1/ADC2/FDCAN1/I2C5/I2C6/I2S2/LTDC/SPI2/TIM1/UART4/USART1 Y16 PA12/FDCAN1_TX/I2C5_SDA/I2C6_SDA/LTDC_R5/S\A\I\2\_\F\S\_\B\/TIM1_ETR/UART4_TX/USART1_DE/USART1_RTS W16 PA13/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_1/UART4_TX W3 PA14/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_2 R3 PA15/CEC/ADC1/ADC2/DEBUG/I2S1/I2S3/LTDC/SAI4/SDMMC1/SDMMC2/SPI1/SPI3/SPI6/TIM2/UART4/UART7 E11 PI10/ETH1_RX_ER/HDP_HDP0/LTDC_HSYNC/USART3_CTS/U\S\A\R\T\3\_\N\S\S\ W1 PI11/ADC1_EXTI11/ADC2_EXTI11/I2S_CKIN/LTDC_G6/PWR_WKUP5/RCC_MCO_1 T3 PI12/DEBUG_TRACED0/HDP_HDP0/LTDC_HSYNC H2 PI13/DEBUG_TRACED1/HDP_HDP1/LTDC_VSYNC H1 PI14/DEBUG_TRACECLK/LTDC_CLK D2 PI15/ADC1_EXTI15/ADC2_EXTI15/LTDC_G2/LTDC_R0 F3 PA0/ADC1/ETH1/PWR/SAI2/SDMMC2/TIM15/TIM2/TIM5/TIM8/UART4/USART2 AA3 PA1/ADC1/ETH1/LPTIM3/LTDC/QUADSPI/SAI2/TIM15/TIM2/TIM5/UART4/USART2 V4 PA2/ADC1/ETH1/LPTIM4/LTDC/PWR/SAI2/SDMMC2/TIM15/TIM2/TIM5/USART2 AB2 PA3/ADC1_INP15/ETH1_COL/LPTIM5_OUT/L\T\D\C\_\B\2\/L\T\D\C\_\B\5\/PWR_PVD_IN/TIM15_CH2/TIM2_CH4/TIM5_CH4/USART2_RX T4 PA4/ADC1/ADC2/DAC1/DCMI/HDP/I2S1/I2S3/LTDC/SAI4/SPI1/SPI3/SPI6/TIM5/USART2 V6 PA5/ADC1/ADC2/DAC1/I2S1/LTDC/SAI4/SPI1/SPI6/TIM2/TIM8 U5 PA6/ADC1/ADC2/DCMI/I2S1/LTDC/SAI4/SPI1/SPI6/TIM13/TIM1/TIM3/TIM8 W9 PA7/ADC1/ADC2/ETH1/I2S1/QUADSPI/SAI4/SPI1/SPI6/TIM14/TIM1/TIM3/TIM8 Y9 PA8/I2C3/I2S3/LTDC/RCC/SAI4/SDMMC2/SPI3/TIM1/TIM8/UART7/USART1/USB B13 PA9/DAC1_EXTI9/DCMI_D0/I2C3_SMBA/I2S2_CK/LTDC_R5/SDMMC2_CDIR/SDMMC2_D5/SPI2_SCK/TIM1_CH2/USART1_TX A11 PA10/DCMI_D1/I2S3_WS/L\T\D\C\_\B\1\/S\A\I\4\_\F\S\_\B\/S\P\I\3\_\N\S\S\/TIM1_CH3/USART1_RX/USB_OTG_HS_ID Y17 PA11/ADC1/ADC2/FDCAN1/I2C5/I2C6/I2S2/LTDC/SPI2/TIM1/UART4/USART1 Y16 PA12/FDCAN1_TX/I2C5_SDA/I2C6_SDA/LTDC_R5/S\A\I\2\_\F\S\_\B\/TIM1_ETR/UART4_TX/USART1_DE/USART1_RTS W16 PA13/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_1/UART4_TX W3 PA14/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_2 R3 PA15/CEC/ADC1/ADC2/DEBUG/I2S1/I2S3/LTDC/SAI4/SDMMC1/SDMMC2/SPI1/SPI3/SPI6/TIM2/UART4/UART7 E11
PB0/ADC1/ADC2/DFSDM1/ETH1/LTDC/TIM1/TIM3/TIM8/UART4 AB5 PB1/ADC1_INP5/ADC2_INP5/DFSDM1_DATIN1/ETH1_RXD3/LTDC_G0/LTDC_R6/TIM1_CH3N/TIM3_CH4/TIM8_CH3N AA5 PB2/DEBUG/DFSDM1/I2S3/I2S/QUADSPI/SAI1/SPI3/UART4/USART1 V13 PB3/DEBUG/I2S1/I2S3/SAI4/SDMMC2/SPI1/SPI3/SPI6/TIM2/UART7 A12 PB4/DEBUG/I2S1/I2S2/I2S3/SAI4/SDMMC2/SPI1/SPI2/SPI3/SPI6/TIM16/TIM3/UART7 C13 PB5/DCMI/ETH1/FDCAN2/I2C1/I2C4/I2S1/I2S3/LTDC/SAI4/SPI1/SPI3/SPI6/TIM17/TIM3/UART5 AA8 PB6/CEC/DCMI/DFSDM1/FDCAN2/I2C1/I2C4/QUADSPI/TIM16/TIM4/UART5/USART1 W13 PB7/DCMI_VSYNC/DFSDM1_CKIN5/F\M\C\_\N\L\/I2C1_SDA/I2C4_SDA/SDMMC2_D1/TIM17_CH1N/TIM4_CH2/USART1_RX F11 PB8/DCMI/DFSDM1/ETH1/FDCAN1/HDP/I2C1/I2C4/LTDC/SDMMC1/SDMMC2/TIM16/TIM4/UART4 AB8 PB9/DAC1/DCMI/DFSDM1/FDCAN1/HDP/I2C1/I2C4/I2S2/LTDC/SDMMC1/SDMMC2/SPI2/TIM17/TIM4/UART4 F12 PB10/DFSDM1/ETH1/I2C2/I2S2/LPTIM2/LTDC/QUADSPI/SPI2/TIM2/USART3 V9 PB11/ADC1/ADC2/DFSDM1/DSIHOST/ETH1/I2C2/LPTIM2/LTDC/TIM2/USART3 Y5 PB12/DFSDM1/ETH1/FDCAN2/I2C2/I2C6/I2S2/SPI2/TIM1/UART5/USART3 AA7 PB13/DFSDM1/ETH1/FDCAN2/I2S2/LPTIM2/SPI2/TIM1/UART5/USART3 V10 PB14/DFSDM1/I2S2/SDMMC2/SPI2/TIM12/TIM1/TIM8/USART1/USART3 A13 PB15/ADC1/ADC2/DFSDM1/I2S2/RTC/SDMMC2/SPI2/TIM12/TIM1/TIM8/USART1 B12 PB0/ADC1/ADC2/DFSDM1/ETH1/LTDC/TIM1/TIM3/TIM8/UART4 AB5 PB1/ADC1_INP5/ADC2_INP5/DFSDM1_DATIN1/ETH1_RXD3/LTDC_G0/LTDC_R6/TIM1_CH3N/TIM3_CH4/TIM8_CH3N AA5 PB2/DEBUG/DFSDM1/I2S3/I2S/QUADSPI/SAI1/SPI3/UART4/USART1 V13 PB3/DEBUG/I2S1/I2S3/SAI4/SDMMC2/SPI1/SPI3/SPI6/TIM2/UART7 A12 PB4/DEBUG/I2S1/I2S2/I2S3/SAI4/SDMMC2/SPI1/SPI2/SPI3/SPI6/TIM16/TIM3/UART7 C13 PB5/DCMI/ETH1/FDCAN2/I2C1/I2C4/I2S1/I2S3/LTDC/SAI4/SPI1/SPI3/SPI6/TIM17/TIM3/UART5 AA8 PB6/CEC/DCMI/DFSDM1/FDCAN2/I2C1/I2C4/QUADSPI/TIM16/TIM4/UART5/USART1 W13 PB7/DCMI_VSYNC/DFSDM1_CKIN5/F\M\C\_\N\L\/I2C1_SDA/I2C4_SDA/SDMMC2_D1/TIM17_CH1N/TIM4_CH2/USART1_RX F11 PB8/DCMI/DFSDM1/ETH1/FDCAN1/HDP/I2C1/I2C4/LTDC/SDMMC1/SDMMC2/TIM16/TIM4/UART4 AB8 PB9/DAC1/DCMI/DFSDM1/FDCAN1/HDP/I2C1/I2C4/I2S2/LTDC/SDMMC1/SDMMC2/SPI2/TIM17/TIM4/UART4 F12 PB10/DFSDM1/ETH1/I2C2/I2S2/LPTIM2/LTDC/QUADSPI/SPI2/TIM2/USART3 V9 PB11/ADC1/ADC2/DFSDM1/DSIHOST/ETH1/I2C2/LPTIM2/LTDC/TIM2/USART3 Y5 PB12/DFSDM1/ETH1/FDCAN2/I2C2/I2C6/I2S2/SPI2/TIM1/UART5/USART3 AA7 PB13/DFSDM1/ETH1/FDCAN2/I2S2/LPTIM2/SPI2/TIM1/UART5/USART3 V10 PB14/DFSDM1/I2S2/SDMMC2/SPI2/TIM12/TIM1/TIM8/USART1/USART3 A13 PB15/ADC1/ADC2/DFSDM1/I2S2/RTC/SDMMC2/SPI2/TIM12/TIM1/TIM8/USART1 B12
PC0/ADC1_INP10/ADC2_INP10/DFSDM1_CKIN0/DFSDM1_DATIN4/LPTIM2_IN2/LTDC_R5/Q\U\A\D\S\P\I\_\B\K\2\_\N\C\S\/S\A\I\2\_\F\S\_\B\ U10 PC1/ADC1/ADC2/DEBUG/DFSDM1/ETH1/I2S2/PWR/SAI1/SDMMC2/SPI2/TAMP AB3 PC2/ADC1_INN11/ADC1_INP12/DCMI_PIXCLK/DFSDM1_CKIN1/DFSDM1_CKOUT/ETH1_TXD2/I2S2_SDI/SPI2_MISO Y1 PC3/ADC1_INN12/ADC1_INP13/DEBUG_TRACECLK/DFSDM1_DATIN1/ETH1_TX_CLK/I2S2_SDO/SPI2_MOSI U3 PC4/ADC1_INP4/ADC2_INP4/DFSDM1_CKIN2/ETH1_RXD0/I2S1_MCK/SPDIFRX_IN2 AB6 PC5/ADC1/ADC2/DFSDM1/ETH1/SAI1/SAI4/SPDIFRX AA6 PC6/DCMI/DFSDM1/DSIHOST/HDP/I2S2/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6 E13 PC7/DCMI/DFSDM1/HDP/I2S3/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6 D13 PC8/DCMI_D2/DEBUG_TRACED0/SDMMC1_D0/TIM3_CH3/TIM8_CH3/UART4_TX/UART5_DE/UART5_RTS/USART6_CK E14 PC9/DAC1/DCMI/DEBUG/I2C3/I2S/LTDC/QUADSPI/SDMMC1/TIM3/TIM8/UART5 D14 PC10/DCMI/DEBUG/DFSDM1/I2S3/LTDC/QUADSPI/SAI4/SDMMC1/SPI3/UART4/USART3 F14 PC11/ADC1/ADC2/DCMI/DEBUG/DFSDM1/I2S3/QUADSPI/SAI4/SDMMC1/SPI3/UART4/USART3 D15 PC12/DCMI/DEBUG/I2S3/RCC/SAI4/SDMMC1/SPI3/UART5/USART3 E12 PC13/PWR_WKUP3/RTC_LSCO/RTC_TS/TAMP_IN1/TAMP_OUT2/TAMP_OUT3 N2 PC14-OSC32_IN/RCC_OSC32_IN P1 PC15-OSC32_OUT/ADC1_EXTI15/ADC2_EXTI15/RCC_OSC32_OUT P2 PC0/ADC1_INP10/ADC2_INP10/DFSDM1_CKIN0/DFSDM1_DATIN4/LPTIM2_IN2/LTDC_R5/Q\U\A\D\S\P\I\_\B\K\2\_\N\C\S\/S\A\I\2\_\F\S\_\B\ U10 PC1/ADC1/ADC2/DEBUG/DFSDM1/ETH1/I2S2/PWR/SAI1/SDMMC2/SPI2/TAMP AB3 PC2/ADC1_INN11/ADC1_INP12/DCMI_PIXCLK/DFSDM1_CKIN1/DFSDM1_CKOUT/ETH1_TXD2/I2S2_SDI/SPI2_MISO Y1 PC3/ADC1_INN12/ADC1_INP13/DEBUG_TRACECLK/DFSDM1_DATIN1/ETH1_TX_CLK/I2S2_SDO/SPI2_MOSI U3 PC4/ADC1_INP4/ADC2_INP4/DFSDM1_CKIN2/ETH1_RXD0/I2S1_MCK/SPDIFRX_IN2 AB6 PC5/ADC1/ADC2/DFSDM1/ETH1/SAI1/SAI4/SPDIFRX AA6 PC6/DCMI/DFSDM1/DSIHOST/HDP/I2S2/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6 E13 PC7/DCMI/DFSDM1/HDP/I2S3/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6 D13 PC8/DCMI_D2/DEBUG_TRACED0/SDMMC1_D0/TIM3_CH3/TIM8_CH3/UART4_TX/UART5_DE/UART5_RTS/USART6_CK E14 PC9/DAC1/DCMI/DEBUG/I2C3/I2S/LTDC/QUADSPI/SDMMC1/TIM3/TIM8/UART5 D14 PC10/DCMI/DEBUG/DFSDM1/I2S3/LTDC/QUADSPI/SAI4/SDMMC1/SPI3/UART4/USART3 F14 PC11/ADC1/ADC2/DCMI/DEBUG/DFSDM1/I2S3/QUADSPI/SAI4/SDMMC1/SPI3/UART4/USART3 D15 PC12/DCMI/DEBUG/I2S3/RCC/SAI4/SDMMC1/SPI3/UART5/USART3 E12 PC13/PWR_WKUP3/RTC_LSCO/RTC_TS/TAMP_IN1/TAMP_OUT2/TAMP_OUT3 N2 PC14-OSC32_IN/RCC_OSC32_IN P1 PC15-OSC32_OUT/ADC1_EXTI15/ADC2_EXTI15/RCC_OSC32_OUT P2
PD0/DFSDM1/FDCAN1/FMC/I2C5/I2C6/SAI3/SDMMC3/UART4 C10 PD1/DFSDM1/FDCAN1/FMC/I2C5/I2C6/SAI3/SDMMC3/UART4 B10 PD2/DCMI_D11/I2C5_SMBA/SDMMC1_CMD/TIM3_ETR/UART4_RX/UART5_RX D12 PD3/DCMI/DFSDM1/FMC/HDP/I2S2/LTDC/SDMMC1/SDMMC2/SPI2/USART2 B11 PD4/DFSDM1_CKIN0/F\M\C\_\N\O\E\/SAI3_FS_A/SDMMC3_D1/USART2_DE/USART2_RTS C9 PD5/F\M\C\_\N\W\E\/SDMMC3_D2/USART2_TX A9 PD6/DCMI/DFSDM1/FMC/I2S3/LTDC/SAI1/SPI3/TIM16/USART2 L3 PD7/DEBUG_TRACED6/DFSDM1_CKIN1/DFSDM1_DATIN4/F\M\C\_\N\E\1\/I2C2_SCL/SDMMC3_D3/SPDIFRX_IN0/USART2_CK F10 PD8/DFSDM1_CKIN3/FMC_D13/FMC_DA13/L\T\D\C\_\B\7\/S\A\I\3\_\S\C\K\_\B\/SPDIFRX_IN1/USART3_TX M1 PD9/DAC1_EXTI9/DCMI_HSYNC/DFSDM1_DATIN3/FMC_D14/FMC_DA14/L\T\D\C\_\B\0\/S\A\I\3\_\S\D\_\B\/USART3_RX M2 PD10/DFSDM1/FMC/I2C5/I2S3/LTDC/RTC/SAI3/SPI3/TIM16/USART3 A8 PD11/ADC1/ADC2/FMC/I2C1/I2C4/LPTIM2/QUADSPI/SAI2/USART3 AB9 PD12/FMC/I2C1/I2C4/LPTIM1/LPTIM2/QUADSPI/SAI2/TIM4/USART3 W12 PD13/DSIHOST_TE/FMC_A18/I2C1_SDA/I2C4_SDA/I2S3_MCK/LPTIM1_OUT/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\3\/SAI2_SCK_A/TIM4_CH2 V14 PD14/FMC_D0/FMC_DA0/S\A\I\3\_\M\C\L\K\_\B\/TIM4_CH3/UART8_CTS M3 PD15/ADC1_EXTI15/ADC2_EXTI15/FMC_D1/FMC_DA1/LTDC_R1/SAI3_MCLK_A/TIM4_CH4/UART8_CTS L1 PD0/DFSDM1/FDCAN1/FMC/I2C5/I2C6/SAI3/SDMMC3/UART4 C10 PD1/DFSDM1/FDCAN1/FMC/I2C5/I2C6/SAI3/SDMMC3/UART4 B10 PD2/DCMI_D11/I2C5_SMBA/SDMMC1_CMD/TIM3_ETR/UART4_RX/UART5_RX D12 PD3/DCMI/DFSDM1/FMC/HDP/I2S2/LTDC/SDMMC1/SDMMC2/SPI2/USART2 B11 PD4/DFSDM1_CKIN0/F\M\C\_\N\O\E\/SAI3_FS_A/SDMMC3_D1/USART2_DE/USART2_RTS C9 PD5/F\M\C\_\N\W\E\/SDMMC3_D2/USART2_TX A9 PD6/DCMI/DFSDM1/FMC/I2S3/LTDC/SAI1/SPI3/TIM16/USART2 L3 PD7/DEBUG_TRACED6/DFSDM1_CKIN1/DFSDM1_DATIN4/F\M\C\_\N\E\1\/I2C2_SCL/SDMMC3_D3/SPDIFRX_IN0/USART2_CK F10 PD8/DFSDM1_CKIN3/FMC_D13/FMC_DA13/L\T\D\C\_\B\7\/S\A\I\3\_\S\C\K\_\B\/SPDIFRX_IN1/USART3_TX M1 PD9/DAC1_EXTI9/DCMI_HSYNC/DFSDM1_DATIN3/FMC_D14/FMC_DA14/L\T\D\C\_\B\0\/S\A\I\3\_\S\D\_\B\/USART3_RX M2 PD10/DFSDM1/FMC/I2C5/I2S3/LTDC/RTC/SAI3/SPI3/TIM16/USART3 A8 PD11/ADC1/ADC2/FMC/I2C1/I2C4/LPTIM2/QUADSPI/SAI2/USART3 AB9 PD12/FMC/I2C1/I2C4/LPTIM1/LPTIM2/QUADSPI/SAI2/TIM4/USART3 W12 PD13/DSIHOST_TE/FMC_A18/I2C1_SDA/I2C4_SDA/I2S3_MCK/LPTIM1_OUT/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\3\/SAI2_SCK_A/TIM4_CH2 V14 PD14/FMC_D0/FMC_DA0/S\A\I\3\_\M\C\L\K\_\B\/TIM4_CH3/UART8_CTS M3 PD15/ADC1_EXTI15/ADC2_EXTI15/FMC_D1/FMC_DA1/LTDC_R1/SAI3_MCLK_A/TIM4_CH4/UART8_CTS L1
PE0/DCMI/FMC/I2S3/LPTIM1/LPTIM2/SAI2/SAI4/SPI3/TIM4/UART8 C5 PE1/DCMI_D3/F\M\C\_\N\B\L\1\/I2S2_MCK/LPTIM1_IN2/S\A\I\3\_\S\D\_\B\/UART8_TX D7 PE2/DEBUG_TRACECLK/ETH1_TXD3/FMC_A23/I2C4_SCL/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\2\/SAI1_CK1/SAI1_MCLK_A/SPI4_SCK Y2 PE3/DEBUG_TRACED0/FMC_A19/S\A\I\1\_\S\D\_\B\/SDMMC2_CK/T\I\M\1\5\_\B\K\I\N\ A10 PE4/DCMI/DEBUG/DFSDM1/FMC/LTDC/SAI1/SDMMC1/SDMMC2/SPI4/TIM15 F15 PE5/DCMI/DEBUG/DFSDM1/FMC/LTDC/SAI1/SDMMC1/SDMMC2/SPI4/TIM15 C12 PE6/DCMI/DEBUG/FMC/LTDC/SAI1/SAI2/SDMMC1/SDMMC2/SPI4/TIM15/TIM1 E9 PE7/DFSDM1_DATIN2/FMC_D4/FMC_DA4/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\0\/TIM1_ETR/TIM3_ETR/UART7_RX W10 PE8/DFSDM1_CKIN2/FMC_D5/FMC_DA5/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\1\/TIM1_CH1N/UART7_TX Y12 PE9/DAC1_EXTI9/DFSDM1_CKOUT/FMC_D6/FMC_DA6/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\2\/TIM1_CH1/UART7_DE/UART7_RTS W11 PE10/DFSDM1_DATIN4/FMC_D7/FMC_DA7/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\3\/TIM1_CH2N/UART7_CTS W14 PE11/ADC1/ADC2/DCMI/DFSDM1/FMC/LTDC/SAI2/SPI4/TIM1/USART6 D5 PE12/DFSDM1_DATIN5/FMC_D9/FMC_DA9/L\T\D\C\_\B\4\/S\A\I\2\_\S\C\K\_\B\/SDMMC1_D0DIR/SPI4_SCK/TIM1_CH3N E4 PE13/DCMI_D6/DFSDM1_CKIN5/FMC_D10/FMC_DA10/HDP_HDP2/LTDC_DE/S\A\I\2\_\F\S\_\B\/SPI4_MISO/TIM1_CH3 A4 PE14/FMC/LTDC/SAI2/SDMMC1/SPI4/TIM1/UART8 B4 PE15/ADC1/ADC2/FMC/HDP/LTDC/TIM15/TIM1/UART8/USART2 C4 PE0/DCMI/FMC/I2S3/LPTIM1/LPTIM2/SAI2/SAI4/SPI3/TIM4/UART8 C5 PE1/DCMI_D3/F\M\C\_\N\B\L\1\/I2S2_MCK/LPTIM1_IN2/S\A\I\3\_\S\D\_\B\/UART8_TX D7 PE2/DEBUG_TRACECLK/ETH1_TXD3/FMC_A23/I2C4_SCL/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\2\/SAI1_CK1/SAI1_MCLK_A/SPI4_SCK Y2 PE3/DEBUG_TRACED0/FMC_A19/S\A\I\1\_\S\D\_\B\/SDMMC2_CK/T\I\M\1\5\_\B\K\I\N\ A10 PE4/DCMI/DEBUG/DFSDM1/FMC/LTDC/SAI1/SDMMC1/SDMMC2/SPI4/TIM15 F15 PE5/DCMI/DEBUG/DFSDM1/FMC/LTDC/SAI1/SDMMC1/SDMMC2/SPI4/TIM15 C12 PE6/DCMI/DEBUG/FMC/LTDC/SAI1/SAI2/SDMMC1/SDMMC2/SPI4/TIM15/TIM1 E9 PE7/DFSDM1_DATIN2/FMC_D4/FMC_DA4/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\0\/TIM1_ETR/TIM3_ETR/UART7_RX W10 PE8/DFSDM1_CKIN2/FMC_D5/FMC_DA5/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\1\/TIM1_CH1N/UART7_TX Y12 PE9/DAC1_EXTI9/DFSDM1_CKOUT/FMC_D6/FMC_DA6/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\2\/TIM1_CH1/UART7_DE/UART7_RTS W11 PE10/DFSDM1_DATIN4/FMC_D7/FMC_DA7/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\3\/TIM1_CH2N/UART7_CTS W14 PE11/ADC1/ADC2/DCMI/DFSDM1/FMC/LTDC/SAI2/SPI4/TIM1/USART6 D5 PE12/DFSDM1_DATIN5/FMC_D9/FMC_DA9/L\T\D\C\_\B\4\/S\A\I\2\_\S\C\K\_\B\/SDMMC1_D0DIR/SPI4_SCK/TIM1_CH3N E4 PE13/DCMI_D6/DFSDM1_CKIN5/FMC_D10/FMC_DA10/HDP_HDP2/LTDC_DE/S\A\I\2\_\F\S\_\B\/SPI4_MISO/TIM1_CH3 A4 PE14/FMC/LTDC/SAI2/SDMMC1/SPI4/TIM1/UART8 B4 PE15/ADC1/ADC2/FMC/HDP/LTDC/TIM15/TIM1/UART8/USART2 C4
PF0/FMC_A0/I2C2_SDA/SDMMC3_CKIN/SDMMC3_D0 E10 PF1/FMC_A1/I2C2_SCL/SDMMC3_CDIR/SDMMC3_CMD B9 PF2/FMC_A2/I2C2_SMBA/SDMMC1_D0DIR/SDMMC2_D0DIR/SDMMC3_D0DIR F13 PF3/ETH1_TX_ER/FMC_A3 V3 PF4/FMC_A4/SDMMC3_D1/SDMMC3_D123DIR/USART2_RX F9 PF5/FMC_A5/SDMMC3_D2/USART2_TX D9 PF6/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\3\/S\A\I\1\_\S\D\_\B\/S\A\I\4\_\S\C\K\_\B\/S\P\I\5\_\N\S\S\/TIM16_CH1/UART7_RX AA11 PF7/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\2\/S\A\I\1\_\M\C\L\K\_\B\/SPI5_SCK/TIM17_CH1/UART7_TX AA10 PF8/DEBUG_TRACED12/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\0\/S\A\I\1\_\S\C\K\_\B\/SPI5_MISO/TIM13_CH1/TIM16_CH1N/UART7_DE/UART7_RTS AB10 PF9/DAC1_EXTI9/DEBUG_TRACED13/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\1\/S\A\I\1\_\F\S\_\B\/SPI5_MOSI/TIM14_CH1/TIM17_CH1N/UART7_CTS AB11 PF10/DCMI_D11/LTDC_DE/QUADSPI_CLK/SAI1_D3/SAI1_D4/SAI4_D3/SAI4_D4/T\I\M\1\6\_\B\K\I\N\ V12 PF11/ADC1_EXTI11/ADC1_INP2/ADC2_EXTI11/DCMI_D12/LTDC_G5/S\A\I\2\_\S\D\_\B\/SPI5_MOSI W8 PF12/ADC1_INN2/ADC1_INP6/DEBUG_TRACED4/ETH1_RXD4/FMC_A6 V8 PF13/ADC2_INP2/DEBUG_TRACED5/DFSDM1_DATIN3/DFSDM1_DATIN6/ETH1_RXD5/FMC_A7/I2C1_SMBA/I2C4_SMBA W7 PF14/ADC2_INN2/ADC2_INP6/DEBUG_TRACED6/DFSDM1_CKIN6/ETH1_RXD6/FMC_A8/I2C1_SCL/I2C4_SCL V7 PF15/ADC1_EXTI15/ADC2_EXTI15/DEBUG_TRACED7/ETH1_RXD7/FMC_A9/I2C1_SDA/I2C4_SDA W6 PF0/FMC_A0/I2C2_SDA/SDMMC3_CKIN/SDMMC3_D0 E10 PF1/FMC_A1/I2C2_SCL/SDMMC3_CDIR/SDMMC3_CMD B9 PF2/FMC_A2/I2C2_SMBA/SDMMC1_D0DIR/SDMMC2_D0DIR/SDMMC3_D0DIR F13 PF3/ETH1_TX_ER/FMC_A3 V3 PF4/FMC_A4/SDMMC3_D1/SDMMC3_D123DIR/USART2_RX F9 PF5/FMC_A5/SDMMC3_D2/USART2_TX D9 PF6/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\3\/S\A\I\1\_\S\D\_\B\/S\A\I\4\_\S\C\K\_\B\/S\P\I\5\_\N\S\S\/TIM16_CH1/UART7_RX AA11 PF7/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\2\/S\A\I\1\_\M\C\L\K\_\B\/SPI5_SCK/TIM17_CH1/UART7_TX AA10 PF8/DEBUG_TRACED12/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\0\/S\A\I\1\_\S\C\K\_\B\/SPI5_MISO/TIM13_CH1/TIM16_CH1N/UART7_DE/UART7_RTS AB10 PF9/DAC1_EXTI9/DEBUG_TRACED13/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\1\/S\A\I\1\_\F\S\_\B\/SPI5_MOSI/TIM14_CH1/TIM17_CH1N/UART7_CTS AB11 PF10/DCMI_D11/LTDC_DE/QUADSPI_CLK/SAI1_D3/SAI1_D4/SAI4_D3/SAI4_D4/T\I\M\1\6\_\B\K\I\N\ V12 PF11/ADC1_EXTI11/ADC1_INP2/ADC2_EXTI11/DCMI_D12/LTDC_G5/S\A\I\2\_\S\D\_\B\/SPI5_MOSI W8 PF12/ADC1_INN2/ADC1_INP6/DEBUG_TRACED4/ETH1_RXD4/FMC_A6 V8 PF13/ADC2_INP2/DEBUG_TRACED5/DFSDM1_DATIN3/DFSDM1_DATIN6/ETH1_RXD5/FMC_A7/I2C1_SMBA/I2C4_SMBA W7 PF14/ADC2_INN2/ADC2_INP6/DEBUG_TRACED6/DFSDM1_CKIN6/ETH1_RXD6/FMC_A8/I2C1_SCL/I2C4_SCL V7 PF15/ADC1_EXTI15/ADC2_EXTI15/DEBUG_TRACED7/ETH1_RXD7/FMC_A9/I2C1_SDA/I2C4_SDA W6
PG0/DEBUG_TRACED0/DFSDM1_DATIN0/ETH1_TXD4/FMC_A10 W5 PG1/DEBUG_TRACED1/ETH1_TXD5/FMC_A11 Y4 PG2/DEBUG_TRACED2/ETH1_TXD6/FMC_A12/RCC_MCO_2/T\I\M\8\_\B\K\I\N\ W4 PG3/DEBUG_TRACED3/DFSDM1_CKIN1/ETH1_TXD7/FMC_A13/T\I\M\8\_\B\K\I\N\2\ U4 PG4/ETH1_GTX_CLK/FMC_A14/T\I\M\1\_\B\K\I\N\2\ AB4 PG5/ETH1_CLK125/FMC_A15/TIM1_ETR U8 PG6/DCMI_D12/DEBUG_TRACED14/LTDC_R7/SDMMC2_CMD/T\I\M\1\7\_\B\K\I\N\ D11 PG7/DCMI/DEBUG/LTDC/QUADSPI/SAI1/UART8/USART6 Y11 PG8/DEBUG/ETH1/LTDC/SAI4/SPDIFRX/SPI6/TIM2/TIM8/USART3/USART6 Y8 PG9/DAC1/DCMI/DEBUG/FMC/LTDC/QUADSPI/SAI2/SPDIFRX/USART6 W15 PG10/DCMI_D2/DEBUG_TRACED10/F\M\C\_\N\E\3\/L\T\D\C\_\B\2\/LTDC_G3/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\2\/S\A\I\2\_\S\D\_\B\/UART8_CTS AA9 PG11/ADC1/ADC2/DCMI/DEBUG/ETH1/LTDC/SPDIFRX/UART4/USART1 U11 PG12/ETH1/FMC/LPTIM1/LTDC/SAI4/SPDIFRX/SPI6/USART6 J4 PG13/DEBUG/ETH1/FMC/LPTIM1/LTDC/SAI1/SAI4/SPI6/USART6 AA1 PG14/DEBUG/ETH1/FMC/LPTIM1/LTDC/QUADSPI/SAI4/SPI6/USART6 AA2 PG15/ADC1/ADC2/DCMI/DEBUG/I2C2/SAI1/SDMMC3/USART6 D10 PG0/DEBUG_TRACED0/DFSDM1_DATIN0/ETH1_TXD4/FMC_A10 W5 PG1/DEBUG_TRACED1/ETH1_TXD5/FMC_A11 Y4 PG2/DEBUG_TRACED2/ETH1_TXD6/FMC_A12/RCC_MCO_2/T\I\M\8\_\B\K\I\N\ W4 PG3/DEBUG_TRACED3/DFSDM1_CKIN1/ETH1_TXD7/FMC_A13/T\I\M\8\_\B\K\I\N\2\ U4 PG4/ETH1_GTX_CLK/FMC_A14/T\I\M\1\_\B\K\I\N\2\ AB4 PG5/ETH1_CLK125/FMC_A15/TIM1_ETR U8 PG6/DCMI_D12/DEBUG_TRACED14/LTDC_R7/SDMMC2_CMD/T\I\M\1\7\_\B\K\I\N\ D11 PG7/DCMI/DEBUG/LTDC/QUADSPI/SAI1/UART8/USART6 Y11 PG8/DEBUG/ETH1/LTDC/SAI4/SPDIFRX/SPI6/TIM2/TIM8/USART3/USART6 Y8 PG9/DAC1/DCMI/DEBUG/FMC/LTDC/QUADSPI/SAI2/SPDIFRX/USART6 W15 PG10/DCMI_D2/DEBUG_TRACED10/F\M\C\_\N\E\3\/L\T\D\C\_\B\2\/LTDC_G3/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\2\/S\A\I\2\_\S\D\_\B\/UART8_CTS AA9 PG11/ADC1/ADC2/DCMI/DEBUG/ETH1/LTDC/SPDIFRX/UART4/USART1 U11 PG12/ETH1/FMC/LPTIM1/LTDC/SAI4/SPDIFRX/SPI6/USART6 J4 PG13/DEBUG/ETH1/FMC/LPTIM1/LTDC/SAI1/SAI4/SPI6/USART6 AA1 PG14/DEBUG/ETH1/FMC/LPTIM1/LTDC/QUADSPI/SAI4/SPI6/USART6 AA2 PG15/ADC1/ADC2/DCMI/DEBUG/I2C2/SAI1/SDMMC3/USART6 D10
PH0-OSC_IN/RCC_OSC_IN T1 PH1-OSC_OUT/RCC_OSC_OUT T2 PH2/ETH1_CRS/LPTIM1_IN2/LTDC_R0/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\0\/S\A\I\2\_\S\C\K\_\B\ AB7 PH3/DFSDM1_CKIN4/ETH1_COL/LTDC_R1/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\1\/S\A\I\2\_\M\C\L\K\_\B\ Y6 PH4/I2C2_SCL/LTDC_G4/LTDC_G5 A3 PH5/I2C2_SDA/S\A\I\4\_\S\D\_\B\/S\P\I\5\_\N\S\S\ A2 PH6/DCMI_D8/ETH1_RXD2/I2C2_SMBA/SPI5_SCK/TIM12_CH1 V11 PH7/DCMI_D9/ETH1_RXD3/I2C3_SCL/SPI5_MISO W2 PH8/DCMI_HSYNC/I2C3_SDA/LTDC_R2/TIM5_ETR D6 PH9/DAC1_EXTI9/DCMI_D0/I2C3_SMBA/LTDC_R3/TIM12_CH2 E6 PH10/DCMI_D1/I2C1_SMBA/I2C4_SMBA/LTDC_R4/TIM5_CH1 B1 PH11/ADC1_EXTI11/ADC2_EXTI11/DCMI_D2/I2C1_SCL/I2C4_SCL/LTDC_R5/TIM5_CH2 B3 PH12/DCMI_D3/HDP_HDP2/I2C1_SDA/I2C4_SDA/LTDC_R6/TIM5_CH3 F5 PH13/FDCAN1_TX/LTDC_G2/TIM8_CH1N/UART4_TX D3 PH14/DCMI_D4/FDCAN1_RX/LTDC_G3/TIM8_CH2N/UART4_RX C2 PH15/ADC1_EXTI15/ADC2_EXTI15/DCMI_D11/LTDC_G4/TIM8_CH3N C1 PI0/DCMI_D13/I2S2_WS/LTDC_G5/S\P\I\2\_\N\S\S\/TIM5_CH4 D1 PI1/DCMI_D8/I2S2_CK/LTDC_G6/SPI2_SCK/T\I\M\8\_\B\K\I\N\2\ E2 PI2/DCMI_D9/I2S2_SDI/LTDC_G7/SPI2_MISO/TIM8_CH4 E1 PI3/DCMI_D10/I2S2_SDO/SPI2_MOSI/TIM8_ETR E3 PI4/DCMI_D5/L\T\D\C\_\B\4\/SAI2_MCLK_A/T\I\M\8\_\B\K\I\N\ J6 PI5/DCMI_VSYNC/L\T\D\C\_\B\5\/SAI2_SCK_A/TIM8_CH1 F2 PI6/DCMI_D6/L\T\D\C\_\B\6\/SAI2_SD_A/TIM8_CH2 G5 PI7/DCMI_D7/L\T\D\C\_\B\7\/SAI2_FS_A/TIM8_CH3 F1 PI8/PWR_WKUP4/RTC_LSCO/TAMP_IN2/TAMP_OUT3 N1 PI9/DAC1_EXTI9/FDCAN1_RX/HDP_HDP1/LTDC_VSYNC/UART4_RX J5 PH0-OSC_IN/RCC_OSC_IN T1 PH1-OSC_OUT/RCC_OSC_OUT T2 PH2/ETH1_CRS/LPTIM1_IN2/LTDC_R0/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\0\/S\A\I\2\_\S\C\K\_\B\ AB7 PH3/DFSDM1_CKIN4/ETH1_COL/LTDC_R1/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\1\/S\A\I\2\_\M\C\L\K\_\B\ Y6 PH4/I2C2_SCL/LTDC_G4/LTDC_G5 A3 PH5/I2C2_SDA/S\A\I\4\_\S\D\_\B\/S\P\I\5\_\N\S\S\ A2 PH6/DCMI_D8/ETH1_RXD2/I2C2_SMBA/SPI5_SCK/TIM12_CH1 V11 PH7/DCMI_D9/ETH1_RXD3/I2C3_SCL/SPI5_MISO W2 PH8/DCMI_HSYNC/I2C3_SDA/LTDC_R2/TIM5_ETR D6 PH9/DAC1_EXTI9/DCMI_D0/I2C3_SMBA/LTDC_R3/TIM12_CH2 E6 PH10/DCMI_D1/I2C1_SMBA/I2C4_SMBA/LTDC_R4/TIM5_CH1 B1 PH11/ADC1_EXTI11/ADC2_EXTI11/DCMI_D2/I2C1_SCL/I2C4_SCL/LTDC_R5/TIM5_CH2 B3 PH12/DCMI_D3/HDP_HDP2/I2C1_SDA/I2C4_SDA/LTDC_R6/TIM5_CH3 F5 PH13/FDCAN1_TX/LTDC_G2/TIM8_CH1N/UART4_TX D3 PH14/DCMI_D4/FDCAN1_RX/LTDC_G3/TIM8_CH2N/UART4_RX C2 PH15/ADC1_EXTI15/ADC2_EXTI15/DCMI_D11/LTDC_G4/TIM8_CH3N C1 PI0/DCMI_D13/I2S2_WS/LTDC_G5/S\P\I\2\_\N\S\S\/TIM5_CH4 D1 PI1/DCMI_D8/I2S2_CK/LTDC_G6/SPI2_SCK/T\I\M\8\_\B\K\I\N\2\ E2 PI2/DCMI_D9/I2S2_SDI/LTDC_G7/SPI2_MISO/TIM8_CH4 E1 PI3/DCMI_D10/I2S2_SDO/SPI2_MOSI/TIM8_ETR E3 PI4/DCMI_D5/L\T\D\C\_\B\4\/SAI2_MCLK_A/T\I\M\8\_\B\K\I\N\ J6 PI5/DCMI_VSYNC/L\T\D\C\_\B\5\/SAI2_SCK_A/TIM8_CH1 F2 PI6/DCMI_D6/L\T\D\C\_\B\6\/SAI2_SD_A/TIM8_CH2 G5 PI7/DCMI_D7/L\T\D\C\_\B\7\/SAI2_FS_A/TIM8_CH3 F1 PI8/PWR_WKUP4/RTC_LSCO/TAMP_IN2/TAMP_OUT3 N1 PI9/DAC1_EXTI9/FDCAN1_RX/HDP_HDP1/LTDC_VSYNC/UART4_RX J5
PJ0/DEBUG_TRACED8/LTDC_R1/LTDC_R7 J2 PJ1/DEBUG_TRACED9/LTDC_R2 L6 PJ2/DEBUG_TRACED10/DSIHOST_TE/LTDC_R3 K4 PJ3/DEBUG_TRACED11/LTDC_R4 J1 PJ4/DEBUG_TRACED12/LTDC_R5 K2 PJ5/DEBUG_TRACED2/HDP_HDP2/LTDC_R6 K1 PJ6/DEBUG_TRACED3/HDP_HDP3/LTDC_R7/TIM8_CH2 L5 PJ7/DEBUG_TRACED13/LTDC_G0/TIM8_CH2N L4 PJ8/DEBUG_TRACED14/LTDC_G1/TIM1_CH3N/TIM8_CH1/UART8_TX H6 PJ9/DAC1_EXTI9/DEBUG_TRACED15/LTDC_G2/TIM1_CH3/TIM8_CH1N/UART8_RX L2 PJ10/LTDC_G3/SPI5_MOSI/TIM1_CH2N/TIM8_CH2 J3 PJ11/ADC1_EXTI11/ADC2_EXTI11/LTDC_G4/SPI5_MISO/TIM1_CH2/TIM8_CH2N K6 PJ12/L\T\D\C\_\B\0\/LTDC_G3 B8 PJ13/L\T\D\C\_\B\1\/LTDC_G4 A7 PJ14/L\T\D\C\_\B\2\ B7 PJ15/ADC1_EXTI15/ADC2_EXTI15/L\T\D\C\_\B\3\ C7 PK0/LTDC_G5/SPI5_SCK/TIM1_CH1N/TIM8_CH3 D8 PK1/DEBUG_TRACED4/HDP_HDP4/LTDC_G6/S\P\I\5\_\N\S\S\/TIM1_CH1/TIM8_CH3N E7 PK2/DEBUG_TRACED5/HDP_HDP5/LTDC_G7/T\I\M\1\_\B\K\I\N\/T\I\M\8\_\B\K\I\N\ E8 PK3/L\T\D\C\_\B\4\ B6 PK4/L\T\D\C\_\B\5\ A6 PK5/DEBUG_TRACED6/HDP_HDP6/L\T\D\C\_\B\6\ C6 PK6/DEBUG_TRACED7/HDP_HDP7/L\T\D\C\_\B\7\ A5 PK7/LTDC_DE B5 PJ0/DEBUG_TRACED8/LTDC_R1/LTDC_R7 J2 PJ1/DEBUG_TRACED9/LTDC_R2 L6 PJ2/DEBUG_TRACED10/DSIHOST_TE/LTDC_R3 K4 PJ3/DEBUG_TRACED11/LTDC_R4 J1 PJ4/DEBUG_TRACED12/LTDC_R5 K2 PJ5/DEBUG_TRACED2/HDP_HDP2/LTDC_R6 K1 PJ6/DEBUG_TRACED3/HDP_HDP3/LTDC_R7/TIM8_CH2 L5 PJ7/DEBUG_TRACED13/LTDC_G0/TIM8_CH2N L4 PJ8/DEBUG_TRACED14/LTDC_G1/TIM1_CH3N/TIM8_CH1/UART8_TX H6 PJ9/DAC1_EXTI9/DEBUG_TRACED15/LTDC_G2/TIM1_CH3/TIM8_CH1N/UART8_RX L2 PJ10/LTDC_G3/SPI5_MOSI/TIM1_CH2N/TIM8_CH2 J3 PJ11/ADC1_EXTI11/ADC2_EXTI11/LTDC_G4/SPI5_MISO/TIM1_CH2/TIM8_CH2N K6 PJ12/L\T\D\C\_\B\0\/LTDC_G3 B8 PJ13/L\T\D\C\_\B\1\/LTDC_G4 A7 PJ14/L\T\D\C\_\B\2\ B7 PJ15/ADC1_EXTI15/ADC2_EXTI15/L\T\D\C\_\B\3\ C7 PK0/LTDC_G5/SPI5_SCK/TIM1_CH1N/TIM8_CH3 D8 PK1/DEBUG_TRACED4/HDP_HDP4/LTDC_G6/S\P\I\5\_\N\S\S\/TIM1_CH1/TIM8_CH3N E7 PK2/DEBUG_TRACED5/HDP_HDP5/LTDC_G7/T\I\M\1\_\B\K\I\N\/T\I\M\8\_\B\K\I\N\ E8 PK3/L\T\D\C\_\B\4\ B6 PK4/L\T\D\C\_\B\5\ A6 PK5/DEBUG_TRACED6/HDP_HDP6/L\T\D\C\_\B\6\ C6 PK6/DEBUG_TRACED7/HDP_HDP7/L\T\D\C\_\B\7\ A5 PK7/LTDC_DE B5
PZ0/I2C2_SCL/I2C6_SCL/I2S1_CK/SPI1_SCK/SPI6_SCK/USART1_CK G2 PZ1/I2C2_SDA/I2C4_SDA/I2C5_SDA/I2C6_SDA/I2S1_SDI/SPI1_MISO/SPI6_MISO/USART1_RX H5 PZ2/I2C2_SCL/I2C4_SMBA/I2C5_SMBA/I2C6_SCL/I2S1_SDO/SPI1_MOSI/SPI6_MOSI/USART1_TX K5 PZ3/I2C2_SDA/I2C4_SDA/I2C5_SDA/I2C6_SDA/I2S1_WS/S\P\I\1\_\N\S\S\/S\P\I\6\_\N\S\S\/USART1_CTS/U\S\A\R\T\1\_\N\S\S\ F4 PZ4/I2C2_SCL/I2C4_SCL/I2C5_SCL/I2C6_SCL G1 PZ5/I2C2_SDA/I2C4_SDA/I2C5_SDA/I2C6_SDA/USART1_DE/USART1_RTS H4 PZ6/I2C2_SCL/I2C4_SMBA/I2C6_SCL/I2S1_MCK/USART1_CK/USART1_RX G3 PZ7/I2C2_SDA/I2C6_SDA/USART1_TX H3 PZ0/I2C2_SCL/I2C6_SCL/I2S1_CK/SPI1_SCK/SPI6_SCK/USART1_CK G2 PZ1/I2C2_SDA/I2C4_SDA/I2C5_SDA/I2C6_SDA/I2S1_SDI/SPI1_MISO/SPI6_MISO/USART1_RX H5 PZ2/I2C2_SCL/I2C4_SMBA/I2C5_SMBA/I2C6_SCL/I2S1_SDO/SPI1_MOSI/SPI6_MOSI/USART1_TX K5 PZ3/I2C2_SDA/I2C4_SDA/I2C5_SDA/I2C6_SDA/I2S1_WS/S\P\I\1\_\N\S\S\/S\P\I\6\_\N\S\S\/USART1_CTS/U\S\A\R\T\1\_\N\S\S\ F4 PZ4/I2C2_SCL/I2C4_SCL/I2C5_SCL/I2C6_SCL G1 PZ5/I2C2_SDA/I2C4_SDA/I2C5_SDA/I2C6_SDA/USART1_DE/USART1_RTS H4 PZ6/I2C2_SCL/I2C4_SMBA/I2C6_SCL/I2S1_MCK/USART1_CK/USART1_RX G3 PZ7/I2C2_SDA/I2C6_SDA/USART1_TX H3
ST MICROELECTRONICS STM32MP157AAAX LFBGA448
Part ID
ST MICROELECTRONICS STM32MP157AAAX LFBGA448
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Attributes
Designator
IC?
Comment
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