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README.md

EPS Main Board v2

Subsystem: EPS Status: 🧪 Sample boards ordered for testing

Design Files:

Manufacturing Files:

  • Version: v2r2

  • KiCad: v10

  • Date: 2026-05-04

  • Release: eps-main-board-v2r2

  • Artifacts:

    • Schematics: Included (PDF)
    • Gerbers, Drill and Centroid: Included (ZIP)
    • BOM: Included (CSV, HTML)
    • Panel File: Not Included
    • Instruction:
      • Ordering: Included (PCBWay: TXT)
      • Sourcing: Included (DigiKey: CSV, URL)
      • Assembly: Included (PCBWay: TXT)
    • 3D Model: Included (STEP)
    • 3D Render: Included (WebP)

    3D Render

Table of Contents

  1. Overview
  2. Block Diagram
  3. Specifications
  4. Key Components
  5. Connectors and Interfaces
  6. On-Board Functions
  7. Inhibit Logic
  8. MCU Pinout
  9. MCU Watchdog Behavior
  10. I2C Address Table
  11. Configurable Components
  12. Test Points, Indicators & Buttons
  13. Known Limitations & Design Decisions
  14. Revision History
  15. Notes
  16. License
  17. Contributing
  18. Supporting This Project

1. Overview

The EPS main board is the central component of the Build a CubeSat electrical power system. Version 2 introduces an STM32F405 MCU and uses the updated bacBus pinout v4r1.

This version comes with one position for a DC-DC converter module and one position for a solar charging module. Apart from CANbus, the board does not currently feature full component-level redundancy (see 13.). USB-C PD input is available, set to 12V, 2.5A by default but adjustable (see 11.11).

The board connects to bacBus on the Ym side (bacBus A). BacBus B on the Yp side is a pass-through only. Side panel connectors are now pads designed for pogo pins on the upcoming side panels (in development), with 14 pins per side – of which 2 per side are reserved for magnetorquers (in development). See 5.1 for the side panel pinout.

The battery pack connects through a pair of battery contact PCBs (unchanged from v1), supporting flexible battery pack configuration. The development kit uses 2s2p, but the design has no roadblocks to 4s or 4p configurations.

Since RBF and deployment switch features are not yet present in the current prototype, this board exposes the related lines via jumpers for manual pull-down during development. See 7. for inhibit logic details.

2. Block Diagram

flowchart TB
    PANELS["4x side panels\nPogo pin pads"] --> SOLAR["Solar (PV)"]
    SOLAR --> MUX["Power mux\nTPS2121"]
    USB["USB-C PD\n12 V, 2.5 A default"] --> MUX
    BAT["Battery pack\n2s2p, 7.2 V nom"] --> LSW["Load switch\nTPS1HB08 + ADS1113"]
    MUX --> CHGR["Charger module\nINA219 sensing"]
    CHGR --> VBAT(("VBAT"))
    LSW --> VBAT
    MUX -. "Battery bypass jumper\n(JP401, default open)" .-> VBAT
    VBAT --> LDO["LDO + UVLO\nLDO40L, 3V3_AUX"] & VREG["Regulator module\n2x INA219, 3V3_MAIN and 5V_MAIN"]
    MCU["STM32F405 MCU\nWatchdog, RTC backup"] <--> LSW & CAN["2x TCAN334\nCAN FD, redundant"] & SWD["SWD / JTAG\nARM 2x5 header"] & UART["UART debug\n1x4 header"]
    MCU <== DC system signals ==> BUS["bacBus A (Ym)\nPower + signals"]
    CAN <--> BUS
    VREG == "3.3V, 5V" ==> BUS
    USB -- "USB 2.0" --> MCU

3. Specifications

  • Dimensions: 91.5 mm × 91.5 mm
  • Thickness: 1.6 mm
  • Layer Count: 4
  • Copper Weight: 1 oz outer, 1 oz inner, 70% residual
  • Stackup: PCBWay standard 4L
    1. F.Cu-SIG
    2. In1.Cu-GND
    3. In2.Cu-PWR
    4. B.Cu-MIX
  • Impedance Targets: Not controlled.
    • USB 2.0 FS differential pair: 0.25 mm trace / 0.2 mm gap
    • CAN differential pairs: 0.14 mm trace / 0.14 mm gap.
  • Panelization: No
  • Mounting: Top of EPS bay with standoffs and M3x30 bolts and nuts
  • Stacking: bacBus connection on Ym using bacBus pinout v4r1
  • ECAD: Schematic and layout created in KiCad 9.0.8 and migrated to KiCad 10 for release

4. Key Components

Designator Part Function Grade Upgrade Path
U201 TI TPS1HB08AQPWPRQ1 Load switch (battery disconnect) Automotive –
U202 TI ADS1113IRUG ADC, battery voltage/current sensing Industrial ADS1113QNKSRQ1 (automotive, different footprint: UQFN)
U301 ST LDO40LPU33RY 3.3 V LDO (3V3_AUX bootstrap) Automotive –
U302 TI TMP1075DSG Temperature sensor (LDO) Industrial –
U303 TI TPS3842A010DRLR Under-voltage lockout Industrial TPS3842A010DRLRQ1 (automotive)
U401 TI INA219BIDCN Current sensor on charger module Industrial –
U601 TI INA219BIDCN Current sensor on regulator module (5 V rail) Industrial –
U602 TI INA219BIDCN Current sensor on regulator module (3.3 V rail) Industrial –
U801 ST STM32F405RGT7 MCU Industrial –
U802 TI TPS3813K33DBV External watchdog Industrial TPS3813K33QDBVRQ1 (automotive), TPS3813K33MDBVREP (high-rel/EP)
U901 TI TCAN334G CAN FD transceiver (CAN-1) Industrial TCAN3403DDFRQ1 / TCAN3404DDFRQ1 (automotive, different footprint: TSOT 23-8)
U1001 TI TCAN334G CAN FD transceiver (CAN-2) Industrial TCAN3403DDFRQ1 / TCAN3404DDFRQ1 (automotive, different footprint: TSOT 23-8)
U1101 Diodes AP33771CFBZ-13-FA01 USB-C PD 3.1 sink controller Industrial –
U1102 TI TPS2121 Power mux (PV vs. USB-C) Industrial –

5. Connectors and Interfaces

  • bacBus A (Ym): 2x Amphenol MDT350M01001VT (M.2 connector), bacBus pinout v4r1. BacBus B (Yp) is a pass-through only. Minimal bacBus interconnect length to Zm side is 32.5 mm, which limits component height on the first board below the EPS to ~5 mm. 37.5 mm is recommended if ~10 mm max. component height is needed.
  • Battery Pack: 4x 2 Mill-Max 0630-0-15-15-30-27-10-0 press-fit receptacles for battery contact PCBs
  • USB-C: USB 2.0 receptacle with PD 3.1 sink controller (AP33771C). 12 V, 2.5 A default, adjustable (see 11.11).
  • SWD / JTAG (J801): ARM Cortex debug connector, 2x5 pin, 1.27 mm pitch. Hybrid footprint also compatible with Tag-Connect (unlegged, TC2050-IDC-NL). Ships unpopulated in Dev Kit v1; a right-angle header is included in the box for user-soldered in-stack access. Straight headers work too, or the footprint can be used directly with Tag-Connect. See 11.15 for population options.
  • UART Debug (J803): 1x4 pin header footprint, 2.54 mm pitch, unpopulated. Pin 1: +3V3, Pin 2: GND, Pin 3: UART_RX, Pin 4: UART_TX. UART4 on PC10 (TX) / PC11 (RX). Intended as a secondary debug console alongside USB CDC.
  • Communication: CAN FD on bacBus via 2x TCAN334 (redundant). Split termination via solder jumpers (see 11.9). 2 I2C buses used locally on-board (see 10.).

5.1 Side Panel Connectors

Each side of the EPS main board (Xm, Xp, Ym, Yp) has a 1x14 pad array (J1201–J1204) intended as pogo pin targets for the upcoming side panels and magnetorquers (both in development). The pinout is identical across all four sides, with net names prefixed by side (e.g. MTQ_Xp_A, VPV_Xp). Two pins per side reserved for magnetorquers (1, 14). In this version of the board, two pins are omitted (12, 13) and not all connections are routed (please refer to the table below). Each pad has a THT test point that can be used for experimentation. Pad numbering is on the back silkscreen.

Pin Net Function Notes
1 MTQ_x_A Magnetorquer A Future use, currently NC
2 3V3_x 3.3 V supply to panel To be added: Switch and PANEL_x_EN signal
3 GND System ground
4 VPV Solar panel voltage input Connected to power mux via ESD protection (ESD751)
5 PANEL_x_SDA I2C data Future use, currently NC. When connected, external pull-ups will be required on the side panel – the on-board I2C pull-ups (see §11.10) are for the local bus only.
6 PANEL_x_SCL I2C clock Future use, currently NC. See pin 5.
7 VPV Solar panel voltage input Second VPV pin for redundancy, currently merged with pin 4
8 GND System ground
9 RBF Remove before flight Directly connected to inhibit logic (see 7.)
10 DEPLOY_SW_1 Deployment switch 1 DSW_1 and DSW_2 are functionally coupled in this revision but may be separated for redundancy in future revisions
11 DEPLOY_SW_2 Deployment switch 2 See pin 10
12 NC – Future use, currently excluded
13 NC – Future use, currently excluded
14 MTQ_x_B Magnetorquer B Future use, currently NC

6. On-Board Functions

  • Main battery pack disconnect load switch
  • Local 3V3 LDO for system bootstrapping, with under-voltage protection
  • RBF and deployment switch simulation (pull-down via jumpers), implemented via load switch and LDO (see 7.)
  • Power routing between inputs (battery, solar or USB-C), charger module, voltage regulator module and bacBus A
  • Power sequencing and measurement via the MCU and peripherals (load switch, ADS1113 ADC, INA219 sensors)
  • Monitoring and control of system-wide signals:
    • A_EPS_OK
    • SYNC_PULSE
    • SAFE_MODE
    • A_3V3_AUX_EN
    • HDRM_EN
    • RF_EN
    • A_PAYLOAD_EN
  • Inter-board communication via redundant CAN FD controllers (TCAN334). A_CAN_1 and A_CAN_2 on bacBus A
  • Load switch and LDO temperature measurement (load switch: SNS output, LDO: via TMP1075)
  • MCU reliability enhancement via external watchdog (TPS3813K33, see 9.) and rechargeable RTC backup battery for timekeeping continuity (6.8x2.1-2.6 mm, Seiko MS621T recommended)

7. Inhibit Logic

The EPS implements a two-stage inhibit system to prevent the satellite from powering up before deployment. Three inhibit lines are exposed via jumpers for development use.

7.1. Lines

  • RBF (Remove Before Flight): Controls the LDO enable path. When pulled low, the LDO is disabled, 3V3_AUX is not generated, and the system cannot bootstrap. During development, this line can be held low by a physical jumper (JP101) that is removed before launch.
  • DSW_1 / DSW_2 (Deployment Switches): Control the load switch enable path. When pulled low, the load switch disconnects the battery pack from VBAT. During development, these lines can be held low by physical jumpers (JP102, JP103) that are removed before launch. When the system is integrated in a deployer, these lines are held low by the deployment switches and released after separation. Note: Currently, DSW_1 and DSW_2 merge at the load switch input, so only one header position is needed. This is subject to change in future revisions.

7.2. Pull-Up and Pull-Down Logic

All three inhibit lines are pulled up to battery voltage via redundant 100k resistor pairs:

  • LDO_EN: R301 + R302 (2x 100k to VBAT). RBF jumper (JP101) pulls to GND.
  • LSW_EN: R203 + R204 (2x 100k to VBAT). DSW_1 jumper (JP102) and DSW_2 jumper (JP103) pull to GND.

With no jumpers populated, all lines float high and the system powers up normally. During development, all three jumpers are populated to keep the system inhibited. Removing them simulates the flight power-up sequence.

7.3. Power-Up Sequence

  1. RBF released – LDO is armed but not yet powered
  2. DSW_1 / DSW_2 released – Load switch connects battery pack to VBAT, LDO is powered
  3. 3V3_AUX available – MCU boots, firmware takes over power sequencing

8. MCU Pinout

MCU: ST STM32F405RGT7 (LQFP-64)

Some system signal pins change direction depending on the assigned system role (EPS or OBC). The Dir column reflects the default EPS role. See Notes for OBC role behavior.

Pin STM32 Net Dir Peripheral Function Notes
1 VBAT VBAT_RTC – – RTC backup battery
2 PC13 WDI_EXT O GPIO External watchdog input Pulled low
3 PC14 32KHZ_IN – RCC 32.768 kHz crystal in
4 PC15 32KHZ_OUT – RCC 32.768 kHz crystal out
5 PH0 20MHZ_IN – RCC 20 MHz crystal in
6 PH1 20MHZ_OUT – RCC 20 MHz crystal out
7 NRST RESET – SYS MCU reset
8 PC0 A_VREG_1_EN O GPIO Regulator module output 1 enable Pulled low
9 PC1 A_VREG_2_PGOOD I GPIO Regulator module output 2 power good
10 PC2 A_VREG_1_PGOOD I GPIO Regulator module output 1 power good
11 PC3 A_VREG_2_EN O GPIO Regulator module output 2 enable Pulled low
12 VSSA GND – – Analog ground
13 VDDA VDD – – Analog supply
14 PA0 A_CHG_STAT I GPIO Charger module status
15 PA1 A_CHG_STB O GPIO Charger module standby Pulled low on charger module
16 PA2 LSW_DIA_EN O GPIO Load switch diagnostics enable Pulled low
17 PA3 LSW_SEL O GPIO Load switch latch select floating
18 VSS GND – – Ground
19 VDD VDD – – Digital supply
20 PA4 – – – Reserved for LDO_MUX_STAT in v3 NC
21 PA5 – – – Unused NC
22 PA6 – – – Unused NC
23 PA7 A_EPS_OK O GPIO EPS OK signal Pulled low
24 PC4 SYNC_PULSE I GPIO Sync pulse O in OBC role, no bias
25 PC5 SAFE_MODE I GPIO Safe mode signal O in OBC role, pulled low
26 PB0 A_3V3_AUX_EN O GPIO 3V3_AUX rail enable Pulled low
27 PB1 HDRM_EN I GPIO Hold-down and release mechanism enable O in OBC role, pulled low
28 PB2 RF_EN I GPIO RF enable O in OBC role, pulled low
29 PB10 I2C_2_SCL IO I2C2 I2C bus 2 clock
30 PB11 I2C_2_SDA IO I2C2 I2C bus 2 data
31 VCAP_1 – – – Internal regulator cap
32 VDD VDD – – Digital supply
33 PB12 A_CAN_2_RX I CAN2 CAN bus 2 receive
34 PB13 A_CAN_2_TX O CAN2 CAN bus 2 transmit
35 PB14 A_CAN_2_STB O GPIO CAN transceiver 2 standby Pulled high
36 PB15 A_CAN_2_SHDN O GPIO CAN transceiver 2 shutdown Pulled high
37 PC6 – – – Unused NC
38 PC7 – – – Unused NC
39 PC8 – – – Unused NC
40 PC9 – – – Unused NC
41 PA8 – – – Unused NC
42 PA9 USB_VBUS_SNS I USB_OTG_FS USB VBUS sensing
43 PA10 USB_MUX_STAT I GPIO USB mux status
44 PA11 USB_DN IO USB_OTG_FS USB D–
45 PA12 USB_DP IO USB_OTG_FS USB D+
46 PA13 SWDIO IO SYS SWD data
47 VCAP_2 – – – Internal regulator cap
48 VDD VDD – – Digital supply
49 PA14 SWCLK I SYS SWD clock
50 PA15 LED O GPIO User LED
51 PC10 UART_TX O UART4 UART debug TX
52 PC11 UART_RX I UART4 UART debug RX
53 PC12 – – – Unused NC
54 PD2 A_PAYLOAD_EN I GPIO Payload enable O in OBC role, pulled low
55 PB3 SWO O SYS SWD trace output
56 PB4 A_CAN_1_STB O GPIO CAN transceiver 1 standby Pulled low
57 PB5 A_CAN_1_SHDN O GPIO CAN transceiver 1 shutdown Pulled low
58 PB6 I2C_1_SCL IO I2C1 I2C bus 1 clock
59 PB7 I2C_1_SDA IO I2C1 I2C bus 1 data
60 BOOT0 BOOT I SYS Boot mode select
61 PB8 A_CAN_1_RX I CAN1 CAN bus 1 receive
62 PB9 A_CAN_1_TX O CAN1 CAN bus 1 transmit
63 VSS GND – – Ground
64 VDD VDD – – Digital supply

9. MCU Watchdog Behavior

The external watchdog (TPS3813K33, U802) monitors the MCU and issues a hardware reset if the firmware stops responding. See 11.7 for jumper configuration.

9.1. Default Configuration: Simple Timeout Mode

Solder jumper JP802 connects WDR to GND (factory default). WDT is tied to GND, setting a 2.5 s timeout.

After the 3.3 V rail crosses the 2.93 V threshold, RESET deasserts with a 25 ms delay. From that moment, the watchdog expects a signal edge on WDI within 2.5 s. If no edge arrives, it pulls NRST low for 25 ms and the MCU resets. This cycle repeats indefinitely.

WDI is held low by a pull-down when the GPIO (PC13) is not driven. The watchdog triggers on edges, not levels – the firmware must toggle the pin periodically. Any edge resets the 2.5 s counter.

In timeout mode there is no lower time limit. The firmware should configure the GPIO and begin toggling early in startup, before the 2.5 s window expires.

9.2. Optional: Windowed Mode

Moving solder jumper JP802 to connect WDR to VDD enables the lower window boundary. With the default timeout (WDT to GND, 2.5 s), the window ratio is 1:124.9 – the firmware must pet WDI between approximately 20 ms and 2.5 s after the previous kick. A pet that arrives too early or too late both trigger a reset.

The lower boundary is disabled for the first pet after reset deasserts, but fully enforced from the second kick onward. If a capacitor is fitted on WDT for a custom timeout, the window ratio changes to 1:64.5.

10. I2C Address Table

All devices are on the local I2C buses (I2C1 and I2C2). No I2C devices are currently addressed via bacBus or side panel connectors. On-board pull-up resistors are fitted for both buses (I2C-1: R807/R808, I2C-2: R809/R810, all 10k). No external pull-ups are required on the charger module, regulator module, or any bacBus peripheral connecting to these buses.

10.1. I2C Bus 1

Device Designator Function Binary Hex Dec
ADS1113 U202 ADC, battery sensing 1001000 0x48 72
TMP1075 U302 LDO temperature sensor 1001001 0x49 73

10.2. I2C Bus 2

Device Designator Function Binary Hex Dec
INA219 U401 Current sensor, charger module 1000010 0x42 66
INA219 U601 Current sensor, regulator 5 V rail 1000101 0x45 69
INA219 U602 Current sensor, regulator 3.3 V rail 1000000 0x40 64

11. Configurable Components

11.1. Load Switch (U201, TPS1HB08)

Ref Default Function Notes
R205 See schematic Current limit (ILIM) Sets overcurrent trip point
R206 See schematic Sensing range Sets voltage sensing range for diagnostics

11.2. ADC (U202, ADS1113)

Ref Default Function Notes
ADDR pin GND (0x48) I2C address GND = 0x48, VDD = 0x49, SDA = 0x4A, SCL = 0x4B
R207/R208 See schematic Input voltage divider Sized for up to 4s battery pack as-is

11.3. LDO Temperature Sensor (U302, TMP1075)

Ref Default Function Notes
A0 pin VDD (0x49) I2C address GND = 0x48, VDD = 0x49, SDA = 0x4A, SCL = 0x4B

11.4. UVLO (U303, TPS3842A010)

Ref Default Function Notes
R303 90k UVLO threshold, upper resistor R_top / R_bottom sets threshold. Default: turn-off 7.0 V, turn-on 7.7 V (2s Li-ion, 3.50 V/cell off, 3.85 V/cell on)
R304 10k UVLO threshold, lower resistor 10% hysteresis with current divider ratio of 0.1

11.5. Charger Module INA219 (U401)

Ref Default Function Notes
A0/A1 pins SDA/GND (0x42) I2C address See INA219 address selection table in datasheet

11.6. Regulator Module INA219 (U601, U602)

Ref Default Function Notes
U601 A0/A1 VS+/VS+ (0x45, dec 69) I2C address, 5 V rail See INA219 address selection table in datasheet
U602 A0/A1 GND/GND (0x40, dec 64) I2C address, 3.3 V rail See INA219 address selection table in datasheet

11.7. Watchdog (U802, TPS3813K33)

Ref Default Function Notes
JP802 WDR to GND Watchdog mode GND = simple timeout, VDD = windowed mode (see 9.)

11.8. RTC Backup Battery (BT801)

Ref Default Function Notes
R805 1k Charge resistor 1k for rechargeable (Seiko MS621T), 0R for non-rechargeable, DNP if no battery

11.9. CAN Bus Termination

Ref Default Function Notes
JP901 Open CAN-1 split termination Close to enable 2x 59R + 4.7 nF split termination
JP1001 Open CAN-2 split termination Close to enable 2x 59R + 4.7 nF split termination

11.10. I2C Pull-Ups

Ref Default Function Notes
R807/R808 10k I2C-1 pull-ups (SDA/SCL) Sized for standard mode (100 kHz). Reduce to 4.7k for fast mode (400 kHz). Lower values give sharper edges but increase static current draw.
R800/R810 10k I2C-2 pull-ups (SDA/SCL) See above.

11.11. USB-C PD (U1101, AP33771C)

Ref Default Function Notes
R1101 66k Voltage selection (VSEL) Sets PD voltage request. DS rev 10–2, p. 9
R1102 39k Current selection (ISEL) Sets PD current request. 39k = 2.5 A. Use 100k for auto on FA02 parts. DS rev 10–2, p. 9
D1101 Populated USB power LED Can be removed (DNP) for power saving
R1107 10k Power LED current limit

11.12. USB Power Mux (U1102, TPS2121)

Ref Default Function Notes
R1110 39k Output current limit (ILIM) Sets current limit to approximately 3.2 A. DS rev F, p. 8
R1111–R1118 See schematic PR1/CP2/OV1/OV2 dividers XCOMP mode. Switchover to PV when USB drops below approximately 7.6 V. OVP set to approximately 14.8 V for both inputs. Use 100k R_top for approximately 21.8 V. DS rev F, p. 25

11.13. Battery Bypass (JP401)

Ref Default Function Notes
JP401 Open Battery bypass Close to connect VBAT directly to VIN (solar or USB-C), allowing operation without a battery pack. Located next to the charger module socket. See 13. for caveats.

11.14. User LED

Ref Default Function Notes
D801 Populated User LED on MCU Can be removed (DNP) for power saving
R802 10k User LED current limit

11.15. Debug and Mechanical

Ref Default Function Notes
SW801 Populated Reset button Horizontal side-actuated, accessible on Xp side when integrated. Can be DNP to reduce plastic parts on the board.
J801 Unpopulated SWD / JTAG header Ships with right-angle header included separately. Alternatives: straight header for lower cost and better availability, or left unpopulated for Tag-Connect use only (footprint is Tag-Connect TC2050-IDC-NL compatible).
J803 Unpopulated UART debug header 1x4, 2.54 mm pitch. Can be populated with standard pin header for debug console access.

12. Test Points, Indicators & Buttons

12.1. Test Points

Test points are arranged in a 2.54 mm grid from the center (KiCad parlance: grid origin) of the board, so a perf board with pogo pins can be used to create a testing jig. Each side panel connector pad has a PTH integrated in the footprints for testing and experimentation (J1201-J1204, see 5.1); these do not align with the 2.54 mm grid.

Ref Net Function
TP101 VBAT Battery voltage
TP102 VPV Solar panel voltage
TP103 VIN USB-C input voltage
TP104 +3V3 3.3 V rail (3V3_AUX)
TP106 GND System ground
TP107 SAFE_MODE Safe mode signal
TP108 SYNC_PULSE Sync pulse signal
TP109 HDRM_EN Hold-down and release mechanism enable
TP110 RF_EN RF enable
TP111 A_3V3_AUX_EN 3V3_AUX rail enable
TP112 A_EPS_OK EPS OK signal
TP113 A_PAYLOAD_EN Payload enable

12.2. Indicators

  • D1101: Power LED on USB-C (active when VBUS present)
  • D801: User LED on MCU (PA15, active low)

12.3. Buttons

  • SW801: Reset button (CK KMS223GP LFG). Horizontal side-actuated SMD part, accessible on the Xp side even with the board integrated in the stack. Can be DNP – see 11.15.

12.4. Jumpers

Ref Function Default
JP101 RBF inhibit pull-down Populated (inhibit active)
JP102 DSW_1 inhibit pull-down Populated (inhibit active)
JP103 DSW_2 inhibit pull-down Unpopulated (merged with DSW_1)
JP801 Boot mode select Open (normal boot)
JP802 Watchdog mode (WDR) GND (simple timeout)
JP901 CAN-1 split termination Open (no termination)
JP1001 CAN-2 split termination Open (no termination)

13. Known Limitations & Design Decisions

  • Single charger and regulator module: Only one position each for charger and voltage regulator modules. No hot-redundancy for power conversion.
  • Limited side panel connectivity: Not all side panel lines are routed (see 5.1), but THT test points are supplied in the side panel pad footprints for experimentation (J1201-J1204).
  • No cell balancing: The modular nature does not accommodate for cell balancing cleanly. In future versions which will be intended for qualification and flight, cell balancing will be implemented.
  • No component-level redundancy (except CAN): The load switch, LDO, UVLO, MCU, and USB-C PD controller are all single points of failure. The two CAN FD transceivers (TCAN334) are the only redundant on-board components.
  • bacBus B is pass-through only: The Yp side M.2 connector carries power and signals through but is not actively managed by the EPS MCU. No CAN transceiver or sensing on this side.
  • DSW_1 and DSW_2 merge at load switch: Currently both deployment switch lines connect to the same load switch enable input. Only one jumper header position is needed. This may change in future revisions. See 7.1.
  • Only one VPV line: Solar input is merged into one line (VPV). Four pins are reserved for power input at the charger module, with the idea of having a separate line for each side in the future for per-side MPPT.
  • No LDO current limiting: The LDO40LPU33RY (U301) does not have built-in current limiting. The 3V3_AUX rail is protected by the UVLO only.
  • Side panel I2C unused: The I2C lines routed to the side panel pogo pin pads are present but not connected to any peripheral in the current design. See 5.1.
  • PA4 reserved: PA4 on the MCU is reserved for LDO_MUX_STAT in v3 and is currently unconnected. See 8.
  • INA219 shunt resistors fixed at 2 mOhm: The current sensing shunt resistors on the charger and regulator modules are not routed for easy swapping. Changing them would require recalibrating the INA219 full-scale range in firmware.
  • USB-C limited to USB 2.0 FS: No high-speed data lines are routed. The USB-C connector is used for power delivery and basic USB 2.0 FS communication only.
  • RTC backup battery: The Keystone 2998 holder accepts 6.8 mm diameter coin cells (MS621T or equivalent). The charge circuit assumes a rechargeable cell by default – a non-rechargeable cell requires changing R805 to 0R, and omitting the battery requires DNP on R805. See 11.8.
  • SWD header footprint is hybrid Tag-Connect / 2x5 pin header compatible, allowing flexible population depending on assembly needs. See 11.15.
  • Battery bypass jumper (JP401): When closed, VBAT is connected directly to VIN, bypassing the charger module and battery pack. The UVLO threshold and load switch behavior may not be appropriate for all input voltages in this configuration. Use with caution. See 11.13.
  • Not flight-qualified: This board is designed for development and suborbital test environments.

14. Revision History

Version Date Summary
v2r2 2026-05-04 New edge cuts and minor fixes versus the never-released v2r1
v2r1 Unreleased Complete redesign. Added STM32F405 MCU, USB-C PD, CAN FD, power muxing, load switch current and temp sensing, UVLO, external watchdog, and I2C current and temp sensing for LDO, charger and regulator. Reduced to one charger and one regulator module position for Dev Kit 1 release. Side panel connectors changed to pogo pin pads (14 pins). bacBus pinout v4r1. CERN OHL-S 2.0 license.
v1r1 minimal 2025-04-03 Simplified variant of v1r1. Reduced to two charger and two regulator module positions with no telemetry. Easier to assemble. No MCU. CC BY-SA 4.0 license.
v1r1 2024-10-06 Initial EPS main board. No MCU. Passive power routing with two charger and two regulator module positions. Redundant side panel and bacBus connections. All telemetry routed to bacBus.

15. Notes

Designed for development and suborbital test environments. Not flight-qualified.

16. License

CERN OHL-S 2.0

17. Contributing

Contributions to the Build a CubeSat hardware ecosystem are highly appreciated! To keep things structured, here's how you can contribute:

Fixes & Improvements to Existing Designs

  1. Create a new feature branch (git checkout -b feature/your-feature-name)
  2. Commit your changes (git commit -m 'Brief description of change')
  3. Push to the branch (git push origin feature/your-feature-name)
  4. Submit a Pull Request (PR) with a clear description of the changes

New Designs & Community Contributions

  • Create your own repository
  • Share a link in community discussions or open an issue
  • If relevant, it will be referenced in the docs 🙌

18. Supporting This Project

If you'd like to support the Build a CubeSat project further, consider these options: