gusmanb-logicanalyzer/Electronics/LogicAnalyzer/LogicAnalyzerV2/designs/jitx-design/kicad/output/CPL.csv

1	Designator	Val	Package	Mid X	Mid Y	Rotation	Layer
2	C1	100n	Pkg0402_6	128.184379	-90.766140	-90.000000	top
3	C2	100n	Pkg0402_3	128.284379	-127.710388	-90.000000	top
4	C3	100n	Pkg0402_1	128.184379	-120.321538	-90.000000	top
5	C4	100n	Pkg0402_8	128.184379	-98.154989	-90.000000	top
6	C5	100n	Pkg0402_10	128.184379	-112.932689	-90.000000	top
7	C6	100n	Pkg0402_12	128.184379	-105.543839	-90.000000	top
8	C7	100n	Pkg0402_7	130.647747	-90.762491	90.000000	top
9	C8	100n	Pkg0402_11	130.747747	-127.710388	90.000000	top
10	C9	100n	Pkg0402_13	130.647747	-120.320808	90.000000	top
11	C10	100n	Pkg0402	130.647747	-98.152070	90.000000	top
12	C11	100n	Pkg0402_4	130.647747	-112.931229	90.000000	top
13	C12	100n	Pkg0402_2	130.647747	-105.541650	90.000000	top
14	D1	~	LL_34_L3_5_W1_5_RD	136.915062	-80.798588	90.000000	top
15	J1	~	HDR_TH_3P_P2_54_H_F_W10_0_N	129.508688	-80.551297	180.000000	top
16	J2	~	HDR_TH_32P_P2_54_H_M_R2_C16_S2_54_1	112.600441	-112.450949	-90.000000	top
17	J3	~	HDR_TH_3P_P2_54_H_M_W10_0	129.508688	-141.017927	180.000000	top
18	R1	100K	Pkg0402_9	136.915062	-84.452309	0.000000	top
19	R2	8K2	Pkg0402_5	139.363090	-82.928795	0.000000	top
20	S1	~	SW_TH_SK_13D01_G030	113.128033	-83.279627	-90.000000	top
21	U1	~	TSSOP_14_L5_0_W4_4_P0_65_LS6_4_BL_1	129.408407	-94.417618	-90.000000	top
22	U2	~	TSSOP_14_L5_0_W4_4_P0_65_LS6_4_BL	129.508407	-131.231539	-90.000000	top
23	U3	~	TSSOP_14_L5_0_W4_4_P0_65_LS6_4_BL_2	129.408407	-123.868755	-90.000000	top
24	U4	~	TSSOP_14_L5_0_W4_4_P0_65_LS6_4_BL_5	129.408407	-101.780402	-90.000000	top
25	U5	~	TSSOP_14_L5_0_W4_4_P0_65_LS6_4_BL_3	129.408407	-116.505971	-90.000000	top
26	U6	~	TSSOP_14_L5_0_W4_4_P0_65_LS6_4_BL_4	129.408407	-109.143187	-90.000000	top
27	U7	~	COMM_SMD_L51_0_W21_0_P2_54_SC0916	154.030966	-102.615410	-90.000000	top