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hw-ignitionlet/ignitionlet-config.kicad_sch
Nathanael Huffman 3ec1f26edf
Initial commit after restructure
2023-02-27 21:05:59 -06:00

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(text "Ignition Program/Debug Header" (at 27.94 83.82 0)
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(text "The SDI/SDO signals of the FPGA SPI port switch direction\ndepending on whether the FPGA acts as controller or\nperipheral. U7 handles this reversal of the signals allowing\nthe FPGA to be programmed by reading from the SPI flash,\nor by another controller. The logic is as follows:"
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(text "FPGA_MODE\nH: SPI Master (default)\nL: SPI Slave" (at 269.24 167.64 0)
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(text "Fit one of two SPI flash\noptions." (at 203.2 119.38 0)
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(text "Intended to allow a Gimletlet\nto program either SPI flash\nor the FPGA."
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(text "Operating Modes" (at 25.4 218.44 0)
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(text "ColdBoot Header/Test Points" (at 335.28 144.78 0)
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(text "Intended for hacking and/or\nforced reset/write protect."
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(text "- Program the FPGA SRAM from IGNITION_TARGET_HDR\n\nThe FTDI programmer can program the FPGA SRAM (or NVCM) directly if the user\ninstalls a jumper on the FPGA_MODE signal. This will cause the SPI flash to\nremain in reset and ignore any SPI traffic while mux beteen the header and FPGA\nSPI port will switch the SDO/SDI lines appropriately. The programmer then asserts\nSPI_SS while toggling SPI_RESET. This causes the FPGA to (re-)initialize, sampling\nthe SS pin, and initialize as SPI peripheral instead of master when it finds this signal\nlow. The programmer then writes to the FPGA as per Lattice FPGA-TN-02001-3.2.\n\nHolding the flash in reset can potentially be automated by connecting\nFLASH_RESET to an additional GPIO pin on the programming adapter and modifying\nthe (open source) programming software to assert this pin during the programming\ncycle. This may already be supported in software, but is not tested.\n\n- Program the FPGA SRAM from PMOD_2A\n\nIn the same way as stated above the PMOD header can be used to program the FPGA\nSRAM from an attached Gimletlet using software running on the SP. This mode\nassumes the SPI flash is disabled during programming, either using the described\nFLASH_RESET jumper, or by connecting the FLASH_RESET signal to an SP GPIO using\na Dupont wire, allowing flash reset to happen under software control."
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(text "Header/Jumpers/Test Points" (at 27.94 125.73 0)
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(text "2A\nSPI_MISO\nSPI_MOSI\n" (at 307.34 167.64 0)
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(text "PMOD 2A Peripheral (optional)" (at 76.2 30.48 0)
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(text "Intended to mate with Adafruit\nFT232H + adapter to allow\nsoftware compatibility with both\nLattice and open source\nprogramming tools.\n\nThe pinout is compatible with a\nstraight PMOD 2A connector to\nallow for alternative adapters if\ndesired.\n\nWhatever connects to this header\nis expected to bring slew limiting\nresistors."
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(text "If the SPI flash is programmed with an appropriate\nColdBoot applet and the FPGA boots in SPI Master\nmode, these headers can be used to select one of\nfour bitstreams as defined in the applet.\n\nSee Lattice FPGA-TN-02001-3.2 for details."
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(text "1A\nSPI_MOSI\nSPI_MISO\n" (at 294.64 167.64 0)
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(text "FPGA SPI Mode MUX" (at 269.24 144.78 0)
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(text "- FPGA as SPI Master (default)\n\nThe default operating mode for this board is with the FPGA acting as SPI master.\nWithout anything driving SPI_SS this signal is pulled high. On init (after PoR\nor asserting CRESET) the FPGA will sample this pin. With the pin pulled high it\nwill resume its init sequence as SPI master. Consequently it will then assert\nSPI_SS and drive SPI_SCK, allowing it to read a bitstream from SPI flash and\nenter the user application.\n\n- Program the SPI flash from IGNITION_TARGET_HDR\n\nThe second mode is to program the SPI flash via the IGNITION_TARGET_HDR using an\nFTDI USB programmer. The programmer will assert both SPI_RESET and SPI_SS,\ncausing the FPGA to go/stay in reset while selecting the SPI flash as\nperipheral. The programmer then writes to SPI flash as normal."
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