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hw-ignitionlet/ignitionlet.kicad_sch
Nathanael Huffman 3ec1f26edf
Initial commit after restructure
2023-02-27 21:05:59 -06:00

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(kicad_sch (version 20230121) (generator eeschema)
(uuid 5d237724-842f-435d-9680-7fc6c477e93f)
(paper "A3")
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(title "Ignition Target")
(date "2021-07-21")
(rev "2")
(company "Oxide Computer Co.")
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(text "CMDx LEDs" (at 355.6 83.82 0)
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(text "The board assumes the width of two standard\n0.80” PMOD boards. J16 is intended for additional\nmechanical stability, but is connected to J17 as a\nType 1 interface, providing GPIOs for prototyping\nwhich for example can be wired to CDONE or\nFLASH_RESET when connected to an appropriate\nhost board."
(at 322.58 170.18 0)
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(text "LVDS TX" (at 182.88 58.42 0)
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(text "Ignition Target" (at 17.78 48.26 0)
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(text "Mechanical" (at 294.64 127 0)
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(text "Fault Pin Straps" (at 292.1 20.32 0)
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(text "Command bits are exposed on a header\nfor easy probing and/or alternative\nprototyping."
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(text "The LVDS transmitter pair is implemented as per Lattice FPGA-TN-1253 using PIO pin pairs in Bank 3.\nThe resistor values above were derived using the equations on p. 4 and the following assumptions:\n\nZ0 = 50 ohm\nVCCIO = 2.5V\nV_OD = 0.35V\nR_OUTPUT = 30 ohm\n\nR_P = 2 * ((Z0 * VCCIO) / (VCCIO - (2 * V_OD)))\n = 2 * (165 / 1.8)\n = 139 ohm\n\nR_S = ((Z0 * R_P / 2) / ((R_P / 2) - Z0) - R_OUTPUT\n = (3472 / 19) - 30\n = 149 ohm\n\nThe series resistor is broken into two pieces of 75 ohm each. The intend here is that one pin of a 100\nmil header/ footprint is inserted between the two resistors. If done using a tight layout this via should\nadd minimal disruption at the edge rates of these transmitters.\n\nInserting the via would allow for IO pin to be reused for alternative prototyping by not fitting the second\nseries resistor, parallel resistor and SMA connector, while using the first resistor footprint as slew limiting\nresistor or for series termination.\n\nOne possible application of this alternative scheme is to allow the Ignition protocol to be carried using\nsingle ended LVCMOS signaling at 3.3V between this broad and an ECP5 dev board without requiring\nSMA connectors for the link partner. This would simplify initial prototyping work.\n\nThe AC couping capacitors near the SMA connector are optional in case one wants to experiment. The\nlayout should allow for some copper nearby connected to ground so experiments with a choke are\npossible. If not in use 0 ohm resistors should be fitted."
(at 182.88 223.52 0)
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(text "LVDS RX" (at 17.78 58.42 0)
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(text "ID Straps" (at 355.6 20.32 0)
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(text "CMD Bits Header" (at 294.64 83.82 0)
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(text "Fault pin straps allow setting fixed fault values.\nThe switch attached to PWR_FLT0 provides a\nconvenient way to cause fault interrupts during\nintegration tests. The header allows reuse of\nthese pins for alternative prototyping.\n\nThe FPGA should use programmable\npull-up/pull-down on these poins if required."
(at 294.64 73.66 0)
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(text "Programming & Configuration" (at 353.06 215.9 0)
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(text "The LVDS transmitter pair is implemented as per Lattice FPGA-TN-1253 using\nPIO pin pairs in Bank 3. The iCE40 inputs expect a proper LVDS signal so the\ninputs are biased after the AC-coupling cap. Resistor and capacitor values\ncan be tuned where required.\n\nAn optional header footprint/via is placed near the SMA connector to allow for\nalternate prototyping, using either single-ended or differential signaling. The\nzero ohm resistor footprint can be used for termination or slew limiting\nresistors if desired."
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(text "ID straps allow setting the desired value.\nThe header allows reuse of these pins\nfor alternative prototyping.\n\nSee RFD 142 for currently allocated ID\nvalues. The FPGA should use programmable\npull-up/pull-down on these pins if required."
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(text "If: 5mA\nVf: 1.9V\nRlim: ~300Ω" (at 391.16 99.06 0)
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(text "Power" (at 314.96 215.9 0)
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(text "TODO:\n\n- Check TX/RX cap values againt bit rate" (at 121.92 195.58 0)
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(label "ID0" (at 383.54 33.02 0)
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(label "CMD1" (at 304.8 96.52 0)
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(label "ID5" (at 127 152.4 0)
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(label "~{PWR_FLT0}" (at 127 111.76 0)
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(label "ID1" (at 383.54 35.56 0)
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(label "~{SYS_RST}" (at 127 132.08 0)
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