mirror of
https://gitlab.com/hyperglitch/jellyfish.git
synced 2025-04-07 10:45:09 +00:00
79 lines
2.0 KiB
Makefile
79 lines
2.0 KiB
Makefile
# SPDX-FileCopyrightText: 2025 Igor Brkic <igor@hyperglitch.com>
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# SPDX-License-Identifier: GPL-3.0-or-later
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PROJ = jellyfishopp
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DEVICE = hx1k
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BUILDDIR = build
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SRCDIR = src
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TESTDIR = test
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# Default board
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#BOARD ?= jellyfish
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# Board-specific settings
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ifeq ($(BOARD), jellyfish)
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PIN_DEF = jellyfish.pcf
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PACKAGE = tq144
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else ifeq ($(BOARD), evb)
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PIN_DEF = ice40hx1k-evb.pcf
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PACKAGE = vq100
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else
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$(error Invalid BOARD specified. Choose 'jellyfish' or 'evb')
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endif
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VERILOG_FILES = $(wildcard $(SRCDIR)/*.v)
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TESTBENCH_FILES = $(wildcard $(TESTDIR)/*.sv)
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TESTBENCH_TARGETS = $(patsubst $(TESTDIR)/%.sv,$(BUILDDIR)/%.out,$(TESTBENCH_FILES))
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all: $(BUILDDIR)/$(PROJ).rpt $(BUILDDIR)/$(PROJ).bin
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$(BUILDDIR):
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mkdir -p $(BUILDDIR)
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$(BUILDDIR)/%.json: $(VERILOG_FILES) | $(BUILDDIR)
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yosys -p 'read_verilog -lib +/ice40/cells_sim.v; hierarchy -check -top top; synth_ice40 -top top -json $@' $(VERILOG_FILES)
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$(BUILDDIR)/%.asc: $(BUILDDIR)/%.json
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nextpnr-ice40 -q --$(DEVICE) --pcf $(PIN_DEF) --asc $@ --package $(PACKAGE) --json $^
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$(BUILDDIR)/%.bin: $(BUILDDIR)/%.asc
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icepack $< $@
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$(BUILDDIR)/%.rpt: $(BUILDDIR)/%.asc
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icetime -d $(DEVICE) -mtr $@ $<
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prog: $(BUILDDIR)/$(PROJ).bin
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# -S to copy to SRAM
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iceprog -d i:0x0403:0x6010 -I B -S $<
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prog-flash: $(BUILDDIR)/$(PROJ).bin
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# -S to copy to SRAM
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iceprog -d i:0x0403:0x6010 -I B $<
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# Pattern rule for running a specific testbench
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$(BUILDDIR)/%.out: $(TESTDIR)/%.v $(VERILOG_FILES) | $(BUILDDIR)
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@echo "Running testbench $<..."
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iverilog -g2012 -o $@ -DBUILDDIR=\"$(BUILDDIR)\" $(VERILOG_FILES) $<
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vvp $@
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# Rule for running all testbenches
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test: $(TESTBENCH_TARGETS)
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# Rule for running a specific testbench by name
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test-%: | $(BUILDDIR)
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@echo "Running specific testbench $*..."
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iverilog -g2012 -o $(BUILDDIR)/$*.out $(VERILOG_FILES) $(TESTDIR)/$*.sv test/_modules.sv
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vvp $(BUILDDIR)/$*.out
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# try to synthesize one module
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synth-%: $(BUILDDIR)
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yosys -p 'hierarchy -check -top top; synth_ice40 -top top -json build/synth-$*.json' src/spi_dac.v synth/$*_top.v
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clean:
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rm -rf $(BUILDDIR)
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.PHONY: all prog clean
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