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42 lines
938 B
Markdown
42 lines
938 B
Markdown
# JellyfishOPP FPGA code
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This directory contains the Verilog code for the JellyfishOPP. The code is still under development. Currently the code includes the basic functionality verification of th JellyfishOPP peripherals.
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### Prerequisites
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The open source toolchain is required to build the code. The toolchain can be downloaded from [https://github.com/YosysHQ/oss-cad-suite-build](https://github.com/YosysHQ/oss-cad-suite-build).
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### Building the code
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```
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make BOARD=jellyfish
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```
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### Running the tests
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Tests are currently broken due to the bug in the implementation of the behavioral model of ICE40 specific modules (SB_IO, SB_RAM40_4K)
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```
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make BOARD=jellyfish test-<test_name>
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```
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### Programming the FPGA
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```
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make BOARD=jellyfish prog
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```
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## License
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Verilog code is licensed under the GPLv3 license.
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<!--
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SPDX-FileCopyrightText: 2025 Igor Brkic <igor@hyperglitch.com>
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SPDX-License-Identifier: GPL-3.0-or-later
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-->
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