AllSpiceMirrors/jellyfish-powersupply
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21a3dedb0c
jellyfish-powersupply/hw/dac.kicad_sch
Igor Brkic 21a3dedb0c routing done 90%, board layout defined
2024-06-22 18:39:47 +02:00

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1 2 3 4 5 6 1 2 3 4 5 6 D C B A D C B A Date: 2024-04-10 Size: A4 Id: / File: blob_df8a220ee562960e2e1c33a7025b161cac4232ef_3344486999.kicad_sch Sheet: / KiCad E.D.A. eeschema 8.0 SPDX-FileCopyrightText: 2024 Igor Brkic <igor@hyperglitch.com> SPDX-License-Identifier: CERN-OHL-S-2.0 Title: JellyfishOPP Rev: 1 HYPERGLITCH Ltd C210 100nF R177 100k VDD 1 VREFIO 10 VOUT 2 AGND 4 SPI2C 5 SCLK/SCL 6 ~{SYNC}/A0 7 SDIN/SDA 8 U42 DAC70501ZDGSR C211 4.7uF R72 0R C207 4.7uF R178 0R C208 4.7uF C209 4.7uF R176 100k L11 6.8uH +3.3V +5VA +3.3V DAC_VDD DAC_SCK DAC_SDI DAC_~{CS} VOUT {CTRL_DAC} DAC: 80501 - 16bit 70501 - 14bit 60501 - 12bit settling time: 3-5us
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